JPH09129726A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH09129726A JPH09129726A JP27878995A JP27878995A JPH09129726A JP H09129726 A JPH09129726 A JP H09129726A JP 27878995 A JP27878995 A JP 27878995A JP 27878995 A JP27878995 A JP 27878995A JP H09129726 A JPH09129726 A JP H09129726A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wirings
- insulating film
- semiconductor device
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、多層配線構造を
有する半導体装置およびその製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multi-layer wiring structure and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】近年、ＬＳＩ素子の高集積化を図るた
め、配線の多層化が進み、かつ配線の幅および配線間隔
が小さくなりつつある。2. Description of the Related Art In recent years, in order to achieve high integration of LSI elements, the number of wiring layers has been increased, and the width and spacing between wirings have become smaller.
【０００３】以下では、まず従来の多層配線を有する半
導体装置の一例について、図５を参照しながら説明す
る。図５は従来の多層配線構造を有する半導体装置の概
略断面図を示したものであり、ここでは簡明化のため、
二層配線部分のみを示し、半導体基板上のトランジスタ
ー領域等の各構造は従来と変わらないものとして省略す
る。図５に示すように、半導体基板１上に、半導体基板
１上の回路素子（図示せず）を覆うように酸化珪素膜２
からなる層間絶縁膜が形成され、酸化珪素膜２上にアル
ミニウム合金からなる第１の配線３が設けられている。
そして、この配線を覆うように酸化珪素膜からなる層間
絶縁膜５が設けられている。またこの層間絶縁膜５上に
は、アルミニウム合金からなる第２の配線６が設けら
れ、上記の第２の配線６はタングステンなどの導電物か
ら成るプラグ４を介して第１の配線３と接続されてい
る。In the following, an example of a conventional semiconductor device having a multi-layer wiring will be described with reference to FIG. FIG. 5 is a schematic cross-sectional view of a conventional semiconductor device having a multilayer wiring structure. Here, for simplification,
Only the two-layer wiring portion is shown, and each structure such as a transistor region on the semiconductor substrate is omitted since it is the same as the conventional one. As shown in FIG. 5, a silicon oxide film 2 is formed on the semiconductor substrate 1 so as to cover circuit elements (not shown) on the semiconductor substrate 1.
Is formed, and the first wiring 3 made of an aluminum alloy is provided on the silicon oxide film 2.
Then, an interlayer insulating film 5 made of a silicon oxide film is provided so as to cover this wiring. A second wiring 6 made of an aluminum alloy is provided on the interlayer insulating film 5, and the second wiring 6 is connected to the first wiring 3 via a plug 4 made of a conductive material such as tungsten. Has been done.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記の
ような半導体装置は、デバイスの高集積化に伴う配線の
間隔縮小や多層化により配線間の寄生容量が増大し、デ
バイスの動作速度が遅くなるという問題が顕著になりつ
つある。配線の寄生容量は同層配線間の寄生容量（隣接
する配線間の寄生容量）と異層配線間の寄生容量（上下
配線間の容量）に分離でき、後者の寄生容量を軽減する
対策としては、層間絶縁膜の厚さを厚くする方法で解決
することができる。However, in the semiconductor device as described above, the parasitic capacitance between the wirings increases due to the reduction of the wiring spacing and the increase in the number of wirings accompanying the high integration of the device, and the operating speed of the device becomes slow. That problem is becoming more prominent. The parasitic capacitance of the wiring can be divided into a parasitic capacitance between the wirings in the same layer (parasitic capacitance between adjacent wirings) and a parasitic capacitance between the wirings in different layers (capacitance between the upper and lower wirings), and as a measure to reduce the latter parasitic capacitance, The problem can be solved by increasing the thickness of the interlayer insulating film.
【０００５】しかしながら、前者の寄生容量に関して
は、配線間隔を広げることも考えられるが、デバイスの
高集積化の観点から実現は困難である。However, regarding the former parasitic capacitance, it is possible to increase the wiring interval, but it is difficult to realize it from the viewpoint of high integration of the device.
【０００６】したがって、この発明の目的は、配線間の
寄生容量を低減し、デバイスの動作速度を向上する半導
体装置およびその製造方法を提供することである。Therefore, an object of the present invention is to provide a semiconductor device which reduces parasitic capacitance between wirings and improves the operation speed of the device, and a method of manufacturing the same.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に本発明の半導体装置は、半導体基板上に設けた多層配
線において同層の配線間が真空であるかもしくはガスが
存在する構造を備えたものである。In order to achieve the above object, a semiconductor device of the present invention has a structure in which, in a multi-layer wiring provided on a semiconductor substrate, there is a vacuum or a gas is present between the wirings of the same layer. It is a thing.
【０００８】また本発明の製造方法は、半導体基板上に
直接又は絶縁膜を介して第１の配線を形成し、第１の配
線の上面のみに絶縁膜を形成し、この絶縁膜にスルーホ
ール（開口部）を形成し、この絶縁膜上に第２の配線を
形成する工程を有するものである。Further, according to the manufacturing method of the present invention, the first wiring is formed on the semiconductor substrate directly or via the insulating film, the insulating film is formed only on the upper surface of the first wiring, and the through hole is formed in this insulating film. The step of forming (opening) and forming the second wiring on the insulating film is included.
【０００９】また、本発明の半導体装置は、半導体基板
上に設けた多層配線において同層の配線間および異層の
配線間が真空であるかもしくはガスが存在する構造を備
えたものである。Further, the semiconductor device of the present invention has a structure in which, in the multi-layered wiring provided on the semiconductor substrate, there is a vacuum or a gas between the wirings of the same layer and between the wirings of different layers.
【００１０】また本発明の製造方法は半導体基板上に直
接又は絶縁膜を介して第１のの配線を形成し、第１の配
線および絶縁膜上に粘性流体を回転塗布し、熱処理を施
してこの粘性流体から被膜を形成し、被膜にスルーホー
ル（開口部）を形成し、被膜上に第２の配線を形成した
後、この被膜をエッチング除去するものである。According to the manufacturing method of the present invention, the first wiring is formed on the semiconductor substrate directly or through the insulating film, the viscous fluid is spin-coated on the first wiring and the insulating film, and heat treatment is performed. A coating is formed from this viscous fluid, a through hole (opening) is formed in the coating, a second wiring is formed on the coating, and then the coating is removed by etching.
【００１１】[0011]
【発明の実施の形態】第一の発明の半導体装置およびそ
の製造方法によれば、同層の配線間は真空であるかもし
くはガスが存在するため、同層配線間の寄生容量が非常
に小さく、デバイスの動作速度が遅いという問題を防止
できる。According to the semiconductor device and the method of manufacturing the same of the first aspect of the present invention, since a vacuum or a gas exists between the wirings in the same layer, the parasitic capacitance between the wirings in the same layer is very small. The problem that the operation speed of the device is slow can be prevented.
【００１２】また、第二の発明の半導体装置およびその
製造方法によれば、同層および異層の配線間が真空であ
るかもしくはガスが存在するため、配線間の寄生容量は
さらに小さくなり、デバイスの動作速度が遅いという問
題を防止できる。Further, according to the semiconductor device and the method of manufacturing the same of the second invention, since a vacuum or a gas exists between the wirings in the same layer and different layers, the parasitic capacitance between the wirings is further reduced, It is possible to prevent the problem that the operation speed of the device is slow.
【００１３】（実施例１）以下では本発明第１の実施例
における多層配線構造を有する半導体装置について図１
を参照しながら説明する。図１は、本実施例における多
層配線構造を有する半導体装置の概略断面図を示したも
のであるが、簡明化のため、二層配線部分のみを示し、
半導体基板上のトランジスター領域等の各構造は従来と
変わらないものとする。(Embodiment 1) A semiconductor device having a multilayer wiring structure according to a first embodiment of the present invention will be described below with reference to FIG.
This will be described with reference to FIG. FIG. 1 is a schematic cross-sectional view of a semiconductor device having a multilayer wiring structure according to this embodiment, but for the sake of simplicity, only a two-layer wiring portion is shown.
Each structure such as a transistor region on a semiconductor substrate is assumed to be the same as the conventional structure.
【００１４】図１に示すように、半導体基板１上に、半
導体基板１上の回路素子（図示せず）を覆うように酸化
珪素膜（層間絶縁膜）２が形成され、酸化珪素膜２上に
アルミニウム合金からなる第１の配線３が設けられてい
る。そして、この第１の配線３の間は真空もしくは空気
などのガス７が存在（充填）し、第１の配線３上に例え
ば、ポリイミド膜からなる層間絶縁膜５が設けられてい
る。この層間絶縁膜５上には、アルミニウム合金からな
る第２の配線６が設けられ、この第２の配線６はタング
ステンなどの導電物から成るプラグ４を介して第１の配
線３と接続している。As shown in FIG. 1, a silicon oxide film (interlayer insulating film) 2 is formed on the semiconductor substrate 1 so as to cover a circuit element (not shown) on the semiconductor substrate 1. Is provided with a first wiring 3 made of an aluminum alloy. A gas 7 such as vacuum or air exists (fills) between the first wirings 3, and an interlayer insulating film 5 made of, for example, a polyimide film is provided on the first wirings 3. A second wiring 6 made of an aluminum alloy is provided on the interlayer insulating film 5, and the second wiring 6 is connected to the first wiring 3 via a plug 4 made of a conductive material such as tungsten. There is.
【００１５】次に、以下では上記図１に示した半導体装
置の製造方法を図２の製造工程図により詳しく説明す
る。尚、簡明化のため、二層配線の形成工程のみを示
し、トランジスターなどの回路素子の製造工程は従来と
変わらないものとする。Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described in detail below with reference to the manufacturing process chart of FIG. For simplicity, only the two-layer wiring forming process is shown, and the manufacturing process of circuit elements such as transistors is the same as the conventional process.
【００１６】まず図２（ａ）に示すように、半導体基板
１上のトランジスターどの回路素子（図示せず）を覆う
ように形成された酸化珪素膜２上にアルミ合金から成る
第１の配線３を形成する。この後、図２（ｂ）に示すよ
うに、ポリイミド膜から成る層間絶縁膜５を第１の配線
３に張り付ける。次に、図２（ｃ）に示すように、ホト
レジストをマスクにして層間絶縁膜５をエッチングしス
ルーホール（開口部）を形成した後、スルーホール（開
口部）内のアルミ合金上に例えばＷＦ6／Ｈ2混合ガスを
用いてタングステン（Ｗ）を選択成長し、Ｗプラグ４を
形成する。この後、アルミ合金膜を堆積し、ホトレジス
トをマスクにして塩素系ガスを用いてアルミエッチング
を施し第２の配線６を形成して多層配線の形成を完了す
る。First, as shown in FIG. 2A, a first wiring 3 made of an aluminum alloy is formed on a silicon oxide film 2 formed so as to cover a circuit element (not shown) such as a transistor on a semiconductor substrate 1. To form. Thereafter, as shown in FIG. 2B, the interlayer insulating film 5 made of a polyimide film is attached to the first wiring 3. Next, as shown in FIG. 2C, the interlayer insulating film 5 is etched using a photoresist as a mask to form a through hole (opening), and then, for example, WF is formed on the aluminum alloy in the through hole (opening). Tungsten (W) is selectively grown using a 6 / H 2 mixed gas to form a W plug 4. After that, an aluminum alloy film is deposited and aluminum etching is performed using a chlorine-based gas using a photoresist as a mask to form the second wiring 6, thereby completing the formation of the multilayer wiring.
【００１７】上記のように本実施例の構成によれば、同
一の高さに形成され複数存在する第１の配線間の距離が
短くなったとしても、その空間が誘電率が非常に低いガ
スまたは真空であるため、寄生容量を著しく小さくする
ことができる。As described above, according to the structure of this embodiment, even if the distance between the plurality of first wirings formed at the same height is shortened, the space has a very low dielectric constant. Alternatively, since it is a vacuum, the parasitic capacitance can be significantly reduced.
【００１８】（実施例２）次に以下では本発明第２の実
施例における多層配線構造を有する半導体装置について
図３を参照しながら説明する。図３は、本実施例におけ
る多層配線構造を有する半導体装置の概略断面図を示し
たものであるが、簡明化のため、二層配線部分のみを示
し、半導体基板上のトランジスター領域等の各構造は従
来と変わらないものとし、ここでは省略する。(Embodiment 2) Next, a semiconductor device having a multilayer wiring structure according to a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a schematic cross-sectional view of a semiconductor device having a multilayer wiring structure according to the present embodiment, but for the sake of simplicity, only a two-layer wiring portion is shown and each structure such as a transistor region on a semiconductor substrate is shown. Is the same as the conventional one, and is omitted here.
【００１９】図３に示すように、半導体基板１上に、半
導体基板１上の回路素子（図示せず）を覆うように酸化
珪素膜（層間絶縁膜）２が形成され、酸化珪素膜２上に
アルミニウム合金からなる第１の配線３が設けられてい
る。そして、上記の第１の配線の間および第１の配線と
第２の配線の間には空気が存在（充填）し、アルミニウ
ム合金からなる第２の配線６はタングステンなどの導電
物から成るプラグ４を介して第１の配線３と接続してい
る。As shown in FIG. 3, a silicon oxide film (interlayer insulating film) 2 is formed on the semiconductor substrate 1 so as to cover a circuit element (not shown) on the semiconductor substrate 1, and on the silicon oxide film 2. Is provided with a first wiring 3 made of an aluminum alloy. Air is present (filled) between the first wiring and between the first wiring and the second wiring, and the second wiring 6 made of an aluminum alloy is a plug made of a conductive material such as tungsten. It is connected to the first wiring 3 via 4.
【００２０】次に、以下では上記の図３に示した半導体
装置の製造方法を図４の製造工程図により詳しく説明す
る。尚、簡明化のため、二層配線の形成工程のみを示
し、トランジスターなどの回路素子の製造工程は従来と
変わらないものとし、省略する。Next, a method of manufacturing the semiconductor device shown in FIG. 3 will be described in detail below with reference to the manufacturing process chart of FIG. For the sake of simplification, only the steps for forming the two-layer wiring are shown, and the steps for manufacturing the circuit elements such as transistors are the same as those in the prior art and will be omitted.
【００２１】図４（ａ）に示すように、半導体基板１上
のトランジスターなどの回路素子（図示せず）を覆うよ
うに形成された酸化珪素膜２上にアルミ合金から成る第
１の配線３を形成する。この後、図４（ｂ）に示すよう
に、感光性ポリイミドの前駆体を回転塗布し、通常のリ
ソグラフイー工程を経た後、約４００℃の温度で加熱処
理を施し、ポリイミド膜８およびスルーホール（開口
部）９を形成する。次に、図４（ｃ）に示すように、ス
ルーホール（開口部）内のアルミ合金上に例えばＷＦ6
／Ｈ2混合ガスを用いてタングステン（Ｗ）を選択成長
し、Ｗプラグ４を形成する。この後、アルミ合金膜を堆
積し、ホトレジストをマスクにして塩素系ガスを用いて
アルミエッチングを施し第２の配線６を形成する。最後
に、図４（ｄ）に示すように、ポリイミド膜８を発煙硝
酸およびポリイミド剥離液を用いてエッチング除去し、
多層配線の形成を完了する。As shown in FIG. 4A, a first wiring 3 made of an aluminum alloy is formed on a silicon oxide film 2 formed so as to cover a circuit element (not shown) such as a transistor on the semiconductor substrate 1. To form. Thereafter, as shown in FIG. 4B, a photosensitive polyimide precursor is spin-coated, and after a normal lithographic process, heat treatment is performed at a temperature of about 400 ° C. to remove the polyimide film 8 and the through holes. (Opening part) 9 is formed. Next, as shown in FIG. 4C, WF 6 is formed on the aluminum alloy in the through hole (opening).
Tungsten (W) is selectively grown using a / H 2 mixed gas to form a W plug 4. After that, an aluminum alloy film is deposited and aluminum etching is performed using a chlorine-based gas with a photoresist as a mask to form the second wiring 6. Finally, as shown in FIG. 4D, the polyimide film 8 is removed by etching using fuming nitric acid and a polyimide stripping solution,
The formation of the multilayer wiring is completed.
【００２２】従来例では複数存在する第１の配線間およ
び第１の配線と第２の配線間には比誘電率が約４の酸化
珪素膜が存在するのに対して、上記の第１の実施例の場
合、第１の配線間は比誘電率がほとんど１に近いガスも
しくは比誘電率が１の真空であるため、同層配線間の寄
生容量の低減が可能であり、また、第２の実施例の場
合、第１の配線と第２の配線の間もガスもしくは真空で
あるため、さらに配線容量の低減が可能である。In the conventional example, a silicon oxide film having a relative dielectric constant of about 4 is present between a plurality of first wirings and between the first wiring and the second wiring. In the case of the embodiment, a gas having a relative permittivity close to 1 or a vacuum having a relative permittivity of 1 is used between the first wirings, so that it is possible to reduce the parasitic capacitance between the wirings in the same layer. In the case of the embodiment, since the gas or the vacuum is present between the first wiring and the second wiring, the wiring capacitance can be further reduced.
【００２３】尚、第１および第２の実施例とも第１の配
線間には空気が存在（充填）するが、空気の代わりに窒
素などの気体もしくは真空の場合でもこれらの比誘電率
は従来の酸化珪素膜に比べて極めて小さく、同様の効果
が期待できることは明らかである。Although air is present (filled) between the first wirings in both the first and second embodiments, the relative permittivity of these is not changed even when a gas such as nitrogen or vacuum is used instead of air. It is obvious that the same effect can be expected because it is extremely smaller than that of the silicon oxide film.
【００２４】また、第１の実施例では層間絶縁膜として
有機材料のひとつであるポリイミド膜を用いたが、パリ
レンなど他の有機絶縁膜あるいは無機の絶縁膜を用いて
も同様の効果が期待できることは明らかである。In the first embodiment, the polyimide film, which is one of the organic materials, is used as the interlayer insulating film, but the same effect can be expected by using another organic insulating film such as parylene or an inorganic insulating film. Is clear.
【００２５】また、第２の実施例では、第２の配線形成
後にエッチング除去する被膜としてポリイミド膜を用い
たが、塗布ガラス膜など無機材料を用いた場合でも配線
とのエッチング選択比が十分大きいものであれば、同様
の効果が期待できることは明らかである。Further, in the second embodiment, the polyimide film is used as the film to be removed by etching after the formation of the second wiring. However, even when an inorganic material such as a coated glass film is used, the etching selection ratio with respect to the wiring is sufficiently large. It is clear that the same effect can be expected if it is one.
【００２６】さらに、第１、第２の実施例では、二層配
線について述べたが、三層以上の多層配線においても、
同様の方法を繰り返すことにより同様の効果が期待でき
ることは明らかである。Further, in the first and second embodiments, the two-layer wiring is described, but also in the multi-layer wiring of three layers or more,
It is clear that the same effect can be expected by repeating the same method.
【００２７】[0027]
【発明の効果】以上、本発明によれば、第１の実施例を
用いて示したように、複数存在する第１の配線の間には
誘電率が非常に低いガスもしくは真空であるため、同層
配線間の寄生容量の低減が可能であり、また、第２の実
施例のように、第１の配線と第２の配線の間もガスもし
くは真空にした場合、さらに配線容量の低減が可能であ
るため、デバイスの動作速度が向上することは明らかで
ある。As described above, according to the present invention, as shown by using the first embodiment, a gas or a vacuum having a very low dielectric constant is present between a plurality of first wirings. It is possible to reduce the parasitic capacitance between the wirings in the same layer, and when the gas or the vacuum is also applied between the first wiring and the second wiring as in the second embodiment, the wiring capacitance can be further reduced. Since it is possible, it is clear that the operating speed of the device is increased.
【図１】本発明の一実施例に係る半導体装置の要部断面
図FIG. 1 is a sectional view of an essential part of a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施例に係る製造工程断面図FIG. 2 is a sectional view of a manufacturing process according to an embodiment of the present invention.
【図３】本発明の一実施例に係る半導体装置の要部断面
図FIG. 3 is a cross-sectional view of essential parts of a semiconductor device according to an embodiment of the present invention.
【図４】本発明の一実施例に係る製造工程断面図FIG. 4 is a sectional view of a manufacturing process according to an embodiment of the present invention.
【図５】従来の半導体装置の要部断面図FIG. 5 is a cross-sectional view of a main part of a conventional semiconductor device
１ 半導体基板 ２ 酸化珪素膜 ３ 第一配線 ４ Ｗプラグ ５ 層間絶縁膜 ６ 第二配線 ７ 真空もしくはガス ８ ポリイミド膜 ９ スルーホール 1 Semiconductor Substrate 2 Silicon Oxide Film 3 First Wiring 4 W Plug 5 Interlayer Insulation Film 6 Second Wiring 7 Vacuum or Gas 8 Polyimide Film 9 Through Hole
Claims (4)
線と、前記第１の配線上に形成された無機または有機の
絶縁膜材料からなる層間絶縁膜と、前記層間絶縁膜上に
形成された第２の配線と、前記層間絶縁膜中に埋め込ま
れ前記第１の配線と前記第２の配線とを接続する導電性
を有するプラグとを有する半導体装置であって、複数存
在する前記第１の配線間が真空またはガスが充填されて
いることを特徴とする半導体装置。1. A plurality of first wirings formed on a semiconductor substrate, an interlayer insulating film made of an inorganic or organic insulating film material formed on the first wirings, and an interlayer insulating film formed on the interlayer insulating film. A semiconductor device having a formed second wiring and a conductive plug that is embedded in the interlayer insulating film and connects the first wiring and the second wiring, wherein a plurality of semiconductor devices exist. A semiconductor device characterized in that a vacuum or gas is filled between the first wirings.
線と、前記第１の配線上と導電性を有するプラグを介し
て前記プラグ上に形成された第２の配線とを有する半導
体装置であって、複数存在する前記第１の配線間及び前
記第１の配線と前記第２の配線間が真空またはガスが充
填されていることを特徴とする半導体装置。2. A semiconductor having a plurality of first wirings formed on a semiconductor substrate and a second wiring formed on the plugs via a plug having conductivity with the first wirings. A semiconductor device, wherein a plurality of existing first wirings and a space between the first wirings and the second wirings are filled with vacuum or gas.
上に前記第１の配線のみと接するように無機または有機
の絶縁膜材料からなる層間絶縁膜を形成する工程と、前
記層間絶縁膜を選択的にエッチングして前記第１の配線
に達する開口部を形成する工程と、前記開口部内に導電
性を有するプラグを埋め込む工程と、前記層間絶縁膜及
び前記プラグ上に第２の配線を形成する工程とを有する
半導体装置の製造方法。3. A step of forming an interlayer insulating film made of an inorganic or organic insulating film material on a semiconductor substrate having a plurality of first wirings so as to contact only the first wirings, and the interlayer insulation. A step of selectively etching the film to form an opening reaching the first wiring; a step of embedding a conductive plug in the opening; a second wiring on the interlayer insulating film and the plug; And a step of forming a semiconductor device.
上に粘性流体を回転塗布し複数の前記第１の配線間及び
前記第１の配線上を前記粘性流体により覆う工程と、前
記粘性流体に熱処理を施し被膜を形成する工程と、前記
被膜に前記第１の配線に達する開口部を形成するととも
に前記開口部に内にプラグを埋め込む工程と、残存する
前記被膜及び前記プラグ上に第２の配線を形成する工程
と、前記被膜をエッチング除去する工程とを有する半導
体装置の製造方法。4. A step of spin-coating a viscous fluid on a semiconductor substrate on which a plurality of first wirings are formed, and covering between the plurality of first wirings and on the first wirings with the viscous fluid, A step of heat-treating a viscous fluid to form a coating, a step of forming an opening reaching the first wiring in the coating and embedding a plug in the opening, and a step of forming a coating on the remaining coating and the plug. A method of manufacturing a semiconductor device, comprising: a step of forming a second wiring; and a step of removing the coating film by etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27878995A JPH09129726A (en) | 1995-10-26 | 1995-10-26 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27878995A JPH09129726A (en) | 1995-10-26 | 1995-10-26 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09129726A true JPH09129726A (en) | 1997-05-16 |
Family
ID=17602209
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27878995A Pending JPH09129726A (en) | 1995-10-26 | 1995-10-26 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09129726A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001226599A (en) * | 2000-02-18 | 2001-08-21 | Sumitomo Bakelite Co Ltd | Resin composition for forming multi-layered wiring with void and multi-layered wiring with void using the same |
| US6300667B1 (en) | 1997-11-14 | 2001-10-09 | Nippon Steel Corporation | Semiconductor structure with air gaps formed between metal leads |
-
1995
- 1995-10-26 JP JP27878995A patent/JPH09129726A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6300667B1 (en) | 1997-11-14 | 2001-10-09 | Nippon Steel Corporation | Semiconductor structure with air gaps formed between metal leads |
| US6479366B2 (en) | 1997-11-14 | 2002-11-12 | Nippon Steel Corporation | Method of manufacturing a semiconductor device with air gaps formed between metal leads |
| JP2001226599A (en) * | 2000-02-18 | 2001-08-21 | Sumitomo Bakelite Co Ltd | Resin composition for forming multi-layered wiring with void and multi-layered wiring with void using the same |
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