JPH09121018A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH09121018A
JPH09121018A JP27861395A JP27861395A JPH09121018A JP H09121018 A JPH09121018 A JP H09121018A JP 27861395 A JP27861395 A JP 27861395A JP 27861395 A JP27861395 A JP 27861395A JP H09121018 A JPH09121018 A JP H09121018A
Authority
JP
Japan
Prior art keywords
substrate
insulating substrate
adhered
solder
wide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27861395A
Other languages
Japanese (ja)
Inventor
Seiichi Hayakawa
誠一 早川
Yukio Kamida
行雄 紙田
Tatsuya Shigemura
達也 茂村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP27861395A priority Critical patent/JPH09121018A/en
Publication of JPH09121018A publication Critical patent/JPH09121018A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the manufacturing time by adhering an insulation substrate to the bottom part of a recessed part and to prevent the entry of moisture into a device by filling the inside thereof with a supporting base and resin. SOLUTION: A recessed part 60mm long, 100mm wide and 0mm deep is formed in an insulation substrate and a recessed part 5a 51.8mm long, 46.3mm wide and 6mm deep is formed in a supporting base 5. The center of the part 5a in a horizontal direction is the center of arrangement position of the insulation substrate 3. In addition, since the parts other than the part 5a have the same thickness, the entire thickness of a module can be made small. The insulation substrate 3 51.5mm long, 46mm wide and 0.5mm thick in which metallic layers 4a and 4b 0.2mm thick are adhered to both surface thereof is adhered to the bottom surface of the recessed part 5a with a solder 2a, and a semiconductor element 1 is adhered to the metallic layer 4a on the substrate 3 with solder 2c, further a wiring terminal 6 20mm long, 1mm wide and 35mm high is adhered thereto with solder 2b.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は内部絶縁型の半導体
モジュールに係り、特に比較的大電流容量のパッケージ
型パワー半導体モジュールに好適な半導体装置に関す
る。The present invention relates to an internal insulation type semiconductor module, and more particularly to a semiconductor device suitable for a package type power semiconductor module having a relatively large current capacity.

【０００２】[0002]

【従来の技術】従来のこの種の半導体装置の構造を図２
に示す。2. Description of the Related Art The structure of a conventional semiconductor device of this type is shown in FIG.
Shown in

【０００３】この図において、１は半導体素子、２ａ〜
２ｃはソルダー、３は絶縁基板、４は金属層、５は支持
基板、６は配線端子、７は金属ワイヤ、８はケース、９
はゲル充填物、１０はレジンである。In this figure, 1 is a semiconductor element, 2a ...
2c is a solder, 3 is an insulating substrate, 4 is a metal layer, 5 is a supporting substrate, 6 is a wiring terminal, 7 is a metal wire, 8 is a case, 9
Is a gel filling and 10 is a resin.

【０００４】絶縁基板３は、アルミナなどの絶縁材で作
られ、その一方の面には、配線パターンが形成された金
属層４ａが、他方の面には、半田などのろう材による接
合を可能とするための金属層４ｂがそれぞれ設けられて
いる。The insulating substrate 3 is made of an insulating material such as alumina, and has a metal layer 4a having a wiring pattern formed on one surface thereof and a brazing material such as solder on the other surface thereof. Are provided respectively.

【０００５】そして、複数個の半導体素子１は、絶縁基
板３の一方の面に形成されている金属層４ａの所定の部
分にソルダー２ｃにより接着され、さらに絶縁基板３の
もう一方の面に形成されている金属層４ｂが支持基板５
にソルダー２ｂにより、支持基板５に積層される。そし
て、これらの半導体素子１は、金属ワイヤ７により、金
属層４ａの所定の部分に対して配線が施されている。A plurality of semiconductor elements 1 are adhered to a predetermined portion of the metal layer 4a formed on one surface of the insulating substrate 3 by a solder 2c, and further formed on the other surface of the insulating substrate 3. The supported metal layer 4b is the supporting substrate 5.
Then, it is laminated on the support substrate 5 by the solder 2b. Then, in these semiconductor elements 1, wiring is provided by a metal wire 7 to a predetermined portion of the metal layer 4a.

【０００６】支持基板５は、半導体素子１で発生した熱
を拡散させるヒートシンクを兼ねているが、実装状態で
は所定の冷却フィンに取り付けられる。The support substrate 5 also functions as a heat sink for diffusing the heat generated in the semiconductor element 1, but is mounted on a predetermined cooling fin in the mounted state.

【０００７】配線端子６は、金属層４ａに形成されてい
る配線パターンの所定の部分と外部導線とを接続するも
のである。The wiring terminal 6 connects a predetermined portion of the wiring pattern formed on the metal layer 4a to an external conductor.

【０００８】ケース８は半導体装置の容器を構成するも
ので、絶縁材により、側板部を有する底のない箱形に作
られており、支持基板５に接着することにより内部が封
止されるようになっている。このとき、ケース内部に
は、半導体素子を保護するためのゲル９が封入され、そ
のうえをレジン１０を注入し固化を行う。The case 8 constitutes a container of a semiconductor device, and is made of an insulating material in a box shape having a side plate portion without a bottom. The inside of the case 8 is sealed by being adhered to the supporting substrate 5. It has become. At this time, a gel 9 for protecting the semiconductor element is encapsulated inside the case, and a resin 10 is injected on the gel 9 and solidified.

【０００９】[0009]

【発明が解決しようとする課題】しかしながら、前記の
方法では、半導体素子を基板に接着する工程，絶縁基板
を支持基板に接着する工程，配線端子を絶縁基板に接着
する工程の３工程で位置決めのための治具が必要であ
り、製造コストが高く、また製造時間も多く必要であ
る。However, in the above method, the positioning is performed in three steps: the step of adhering the semiconductor element to the substrate, the step of adhering the insulating substrate to the supporting substrate, and the step of adhering the wiring terminals to the insulating substrate. Jig is required, the manufacturing cost is high, and the manufacturing time is long.

【００１０】また、装置内部が支持基板，ケース，レジ
ンにより、封入されているので、空気中の水分が支持基
板，ケース間の接着が不完全な場合、支持基板，ケース
の隙間から装置内部に浸入し半導体素子の劣化を引き起
こす。Further, since the inside of the device is enclosed by the support substrate, the case, and the resin, when the moisture in the air does not completely bond the support substrate and the case, the inside of the device enters through the gap between the support substrate and the case. Penetrates and causes deterioration of semiconductor devices.

【００１１】本発明は、従来のこのような問題点を解決
するためのもので、その目的は、支持基板と絶縁基板と
の接着において治具を不要とすることで、製造時間を短
縮し、また、半導体素子内部を支持基板とレジンにより
封入することで装置内部への水分の浸入を防止すること
である。The present invention is intended to solve such a conventional problem, and an object thereof is to eliminate the need for a jig for bonding a supporting substrate and an insulating substrate, thereby shortening the manufacturing time, In addition, the inside of the semiconductor element is sealed with a support substrate and a resin to prevent moisture from entering the inside of the device.

【００１２】[0012]

【課題を解決するための手段】この発明は支持基板に絶
縁基板と同じ大きさあるいは絶縁基板の大きさより大き
く、なおかつ支持基板の凹部が絶縁基板の大きさより大
きいことによる絶縁基板のずれが絶縁基板と配線端子の
接続に影響しない程度の大きさを持った凹部を設け、前
記凹部の底面に前記絶縁基板を接着し、前記絶縁基板の
金属層に配線端子を接着し、さらに、前記凹部内部にレ
ジンを注入した半導体装置である。According to the present invention, the displacement of the insulating substrate due to the supporting substrate having the same size as the insulating substrate or larger than the insulating substrate and the concave portion of the supporting substrate being larger than the insulating substrate is prevented. A recess having a size that does not affect the connection between the wiring terminal and the wiring terminal, the insulating substrate is bonded to the bottom surface of the recess, the wiring terminal is bonded to the metal layer of the insulating substrate, and It is a semiconductor device in which a resin is injected.

【００１３】この発明における半導体装置は支持基板に
絶縁基板と同じ大きさあるいは絶縁基板の大きさより大
きく、なおかつ支持基板の凹部が絶縁基板の大きさより
大きいことによる絶縁基板のずれが絶縁基板と配線端子
の接続に影響しない程度の大きさを持った凹部を設けた
ことにより、支持基板に対する絶縁基板の位置決めが治
具なしで容易に行えるため、製造コストを低減でき、時
間も短縮できる。In the semiconductor device according to the present invention, the displacement of the insulating substrate due to the supporting substrate having the same size as or larger than the insulating substrate and the concave portion of the supporting substrate being larger than the insulating substrate is different from that of the insulating substrate. Since the concave portion having a size that does not affect the connection of the insulating substrate is provided, the insulating substrate can be easily positioned with respect to the supporting substrate without using a jig, so that the manufacturing cost can be reduced and the time can be shortened.

【００１４】また、配線端子を絶縁基板上の金属層に接
着後、支持基板内に設けられた凹部にレジンを注入する
ことにより、装置内部が支持基板とレジンにより封入さ
れ、装置内部への空気中の水分の浸入を防ぐことができ
る。Further, after the wiring terminals are adhered to the metal layer on the insulating substrate, the resin is injected into the concave portion provided in the supporting substrate so that the inside of the device is sealed by the supporting substrate and the resin, and the air inside the device is sealed. It is possible to prevent the infiltration of water inside.

【００１５】[0015]

【発明の実施の形態】以下、この発明の実施例を図１に
ついて説明する。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIG.

【００１６】図１において、絶縁基板の長手方向を縦と
して、縦６０mm×横１００mm，高さ１０mm、支持基板５
には縦５１.８mm×横４６.３mm，深さ６mmの凹部５ａが
設けられており、その凹部５ａの水平方向の中心は絶縁
基板３の配置位置の中心である。ここで、支持基板は熱
伝導性の良い銅製である。また凹部以外の部分は同じ厚
みを有しているので、モジュール全体の厚みを薄くでき
る。従って、応用装置に組み込むと、実装スペースを低
減でき装置のサイズを低減できる。In FIG. 1, the longitudinal direction of the insulating substrate is vertical, and the length is 60 mm × width 100 mm, height 10 mm, and the supporting substrate 5
Is provided with a recess 5a having a length of 51.8 mm × width of 46.3 mm and a depth of 6 mm, and the center of the recess 5a in the horizontal direction is the center of the arrangement position of the insulating substrate 3. Here, the supporting substrate is made of copper having good thermal conductivity. Further, since the portions other than the recesses have the same thickness, the thickness of the entire module can be reduced. Therefore, when incorporated in an application device, the mounting space can be reduced and the size of the device can be reduced.

【００１７】支持基板の凹部５ａ底面に厚さ０.２mm の
金属層４ａ，４ｂが両面に貼り付けられた縦５１.５mm
×横４６mm，厚さ０.５mmの絶縁基板３がソルダー２ａ
により接着され、絶縁基板３上の金属層４ａには半導体
素子１がソルダー２ｃにより、また縦２０mm×横１mm，
高さ３５mmの配線端子６がソルダー２ｂにより接着され
ている。この配線端子６と金属層４ａとの接続には位置
決めのための治具が必要になる。また、半導体素子の金
属パッドとそれに対応する金属層４ａとは金属ワイヤ７
にて接続されている。この金属ワイヤ７の金属層４ａか
らの高さ３mmである。さらに凹部５ａ内部にはレジン１
０が注入されている。このレジン１０は配線端子６ａが
金属層４ａと接続された後、凹部５ａ内部に注入され
る。A height of 51.5 mm in which metal layers 4a and 4b having a thickness of 0.2 mm are attached to both sides on the bottom surface of the recess 5a of the supporting substrate.
× Insulating board 3 of width 46mm and thickness 0.5mm is solder 2a
The semiconductor element 1 is bonded to the metal layer 4a on the insulating substrate 3 by the solder 2c, and the length is 20 mm × width 1 mm.
The wiring terminal 6 having a height of 35 mm is adhered by the solder 2b. A jig for positioning is required to connect the wiring terminal 6 and the metal layer 4a. In addition, the metal pad of the semiconductor element and the corresponding metal layer 4a are connected to the metal wire 7
Connected at The height of the metal wire 7 from the metal layer 4a is 3 mm. Furthermore, the resin 1 is placed inside the recess 5a.
0 is injected. The resin 10 is injected into the recess 5a after the wiring terminal 6a is connected to the metal layer 4a.

【００１８】次に配線端子６ａと金属層４ａとの接続に
用いる治具の一例を図３に示す。Next, an example of a jig used for connecting the wiring terminal 6a and the metal layer 4a is shown in FIG.

【００１９】治具１１には縦２０.２mm×横１.２mm，深
さ２５mmの凹部１１ａが設けられており、その凹部１１
ａに配線端子６が挿入できるようになっている。また治
具１１には縦６０.５mm×横１００.５mm，深さ１０mmの
凹部１１ｂが設けられており、支持基板５がはめ込める
ようになっている。配線端子６と金属層４ａとの接続
は、治具１１の凹部１１ａに配線端子６を挿入した後、
ソルダー２ｂを支持基板５と接着してある絶縁基板３上
の金属層４ａの所定位置に滴下し、配線端子６を挿入し
た治具１１を支持基板５にはめ込み、加熱することで行
う。The jig 11 is provided with a recess 11a having a length of 20.2 mm × a width of 1.2 mm and a depth of 25 mm.
The wiring terminal 6 can be inserted into a. Further, the jig 11 is provided with a recess 11b having a length of 60.5 mm × width of 100.5 mm and a depth of 10 mm so that the support substrate 5 can be fitted therein. The wiring terminal 6 and the metal layer 4a are connected by inserting the wiring terminal 6 into the recess 11a of the jig 11 and then
The solder 2b is dropped on a predetermined position of the metal layer 4a on the insulating substrate 3 adhered to the supporting substrate 5, the jig 11 having the wiring terminals 6 inserted therein is fitted into the supporting substrate 5, and heating is performed.

【００２０】次に本実施例の作用について説明する。こ
の発明による半導体装置は放熱板２に凹部を設けたこと
により絶縁基板３の位置決めが治具なしで容易に行え、
製造時間を短縮できる。また構成部品のうち、ケース，
ゲルが不要となるため製造コストを低減できる。さら
に、半導体装置内部が支持基板５とレジン１０により封
入されていることにより、装置内部への空気中水分の浸
入を防止できる。Next, the operation of this embodiment will be described. In the semiconductor device according to the present invention, since the heat dissipation plate 2 is provided with the recess, the insulating substrate 3 can be easily positioned without a jig.
Manufacturing time can be shortened. Among the components, the case,
Since no gel is required, the manufacturing cost can be reduced. Furthermore, since the inside of the semiconductor device is sealed by the support substrate 5 and the resin 10, it is possible to prevent infiltration of moisture in the air into the inside of the device.

【００２１】[0021]

【発明の効果】以上のようにこの発明によれば、放熱板
に凹部を設けその凹部上に絶縁基板を装着できるように
したので、絶縁基板の位置決めが治具なしで容易に行
え、作業性を改善できる。また、構成部品の内、ケー
ス，レジンが不要となるため、製造コストも低減でき
る。さらに、装置内部がレジンと支持基板により封入さ
れているので半導体装置内部への水分の浸入を防止でき
る。As described above, according to the present invention, since the heat sink is provided with the concave portion and the insulating substrate can be mounted on the concave portion, the insulating substrate can be easily positioned without a jig, and the workability is improved. Can be improved. Further, among the constituent parts, the case and the resin are unnecessary, so that the manufacturing cost can be reduced. Further, since the inside of the device is sealed by the resin and the supporting substrate, it is possible to prevent the infiltration of water into the inside of the semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明による半導体装置の一実施例を示す説明
図である。FIG. 1 is an explanatory diagram showing an embodiment of a semiconductor device according to the present invention.

【図２】従来例を示す説明図である。FIG. 2 is an explanatory diagram showing a conventional example.

【図３】本発明による半導体装置の組立方法の一例を示
す説明図である。FIG. 3 is an explanatory diagram showing an example of a method of assembling a semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

１…半導体素子、２ａ…絶縁基板下部のソルダー、２ｂ
…配線端子下部のソルダー、２ｃ…半導体素子下部のソ
ルダー、３…絶縁基板、４…金属層、５…支持基板、６
…配線端子、７…金属ワイヤ、８…ケース、９…ゲル、
１０…レジン、１１ａ…治具内の配線端子挿入用凹部、
１１ｂ…治具内の支持基板挿入用凹部。1 ... Semiconductor element, 2a ... Solder under insulating substrate, 2b
... Solder under wiring terminal, 2c ... Solder under semiconductor element, 3 ... Insulating substrate, 4 ... Metal layer, 5 ... Support substrate, 6
... Wiring terminals, 7 ... Metal wires, 8 ... Case, 9 ... Gel,
10 ... Resin, 11a ... Recess for inserting wiring terminal in jig,
11b ... A recess for inserting a support substrate in the jig.

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】半導体素子及び電極端子を搭載した絶縁基
板と、凹部を有し、凹部以外の部分は大略同じ厚さを有
する金属性支持基板とを有し、 前記絶縁基板は前記凹部の底部に接着されることを特徴
とする半導体装置。1. An insulating substrate on which a semiconductor element and an electrode terminal are mounted, a recessed portion, and a metallic support substrate having substantially the same thickness except the recessed portion, wherein the insulating substrate is a bottom portion of the recessed portion. A semiconductor device characterized by being adhered to. 【請求項２】請求項１の半導体装置において、前記凹部
内に、前記半導体素子を封入するようにレジンを注入す
ることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein a resin is injected into the recess so as to encapsulate the semiconductor element.
JP27861395A 1995-10-26 1995-10-26 Semiconductor device Pending JPH09121018A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27861395A JPH09121018A (en) 1995-10-26 1995-10-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27861395A JPH09121018A (en) 1995-10-26 1995-10-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH09121018A true JPH09121018A (en) 1997-05-06

Family

ID=17599726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27861395A Pending JPH09121018A (en) 1995-10-26 1995-10-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH09121018A (en)

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EP2600399A2 (en) 2011-11-30 2013-06-05 Hitachi Ltd. Power semiconductor device
JP2014146723A (en) * 2013-01-30 2014-08-14 Hitachi Power Semiconductor Device Ltd Power semiconductor device
WO2016016985A1 (en) * 2014-07-31 2016-02-04 三菱電機株式会社 Semiconductor device
JP2018157201A (en) * 2017-03-16 2018-10-04 三菱マテリアル株式会社 Resistance device and manufacturing method of resistance device
EP4099375A4 (en) * 2020-01-28 2024-02-21 Kyocera Corp Electronic component mounting package and electronic device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2600399A2 (en) 2011-11-30 2013-06-05 Hitachi Ltd. Power semiconductor device
JP2013115297A (en) * 2011-11-30 2013-06-10 Hitachi Ltd Power semiconductor device
US9013877B2 (en) 2011-11-30 2015-04-21 Hitachi Power Semiconductor Device, Ltd. Power semiconductor device
JP2014146723A (en) * 2013-01-30 2014-08-14 Hitachi Power Semiconductor Device Ltd Power semiconductor device
WO2016016985A1 (en) * 2014-07-31 2016-02-04 三菱電機株式会社 Semiconductor device
JP2018157201A (en) * 2017-03-16 2018-10-04 三菱マテリアル株式会社 Resistance device and manufacturing method of resistance device
EP4099375A4 (en) * 2020-01-28 2024-02-21 Kyocera Corp Electronic component mounting package and electronic device

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