JPH09116125A - Soi wafer and its manufacture - Google Patents
Soi wafer and its manufactureInfo
- Publication number
- JPH09116125A JPH09116125A JP20822896A JP20822896A JPH09116125A JP H09116125 A JPH09116125 A JP H09116125A JP 20822896 A JP20822896 A JP 20822896A JP 20822896 A JP20822896 A JP 20822896A JP H09116125 A JPH09116125 A JP H09116125A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- bonding
- wafers
- bonded
- polishing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Mechanical Treatment Of Semiconductor (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体ウェーハの貼
り合わせ技術に関するものであり、特にＳＯＩ（silico
n on insulator）ウェーハ及びその製造方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonding technique for semiconductor wafers, and particularly to SOI (silico)
Non-insulator) wafer and its manufacturing method.
【０００２】[0002]
【従来の技術】鏡面研磨された２枚のシリコンウェー
ハ、あるいは少なくとも、その一方にシリコン酸化膜を
形成せしめたシリコンウェーハの鏡面同士を清浄な条件
下で接触させると、接着剤等を用いなくとも、ウェーハ
同士は接着する（以後、この状態を接合と称す）。しか
しこの接合状態は完全なものではないので、その後、こ
れらに熱処理を加えると、ウェーハ同士は強固に結合す
る（以後、この状態を結合と称す）。この後者の、少な
くとも一方のウェーハに表面を酸化した２枚のシリコン
ウェーハを、その酸化膜を介して結合させたものがＳＯ
Ｉウェーハである。このようなＳＯＩウェーハは、ウェ
ーハ間に接着剤等の異種物質を介在させる必要がないた
め、その後の高温処理や各種化学処理が自由にでき、ま
たｐｎ接合や誘電体埋め込みも簡便にできるという利点
を有する。さらに平坦度、清浄度等の薄膜化技術の向上
とあいまって、その実用化が注目されている。2. Description of the Related Art Two mirror-polished silicon wafers, or at least one of the silicon wafers having a silicon oxide film formed on one of them is brought into contact with each other under clean conditions without using an adhesive agent. , The wafers are bonded to each other (hereinafter, this state is referred to as bonding). However, since this bonding state is not perfect, the wafers are strongly bonded to each other by heat treatment thereafter (this state is hereinafter referred to as bonding). In this latter case, two silicon wafers whose surfaces are oxidized to at least one of the wafers are bonded to each other through the oxide film.
I wafer. In such an SOI wafer, it is not necessary to interpose a different substance such as an adhesive between the wafers, so that subsequent high temperature treatment and various chemical treatments can be freely performed, and pn junction and dielectric filling can be easily performed. Have. Further, along with improvement of thinning technology such as flatness and cleanliness, its practical application is drawing attention.
【０００３】特に近年の半導体デバイスの高集積度化、
高速度化により、ＳＯＩウェーハの活性層は薄膜化の傾
向にあり、例えば半導体素子を形成するための活性層を
０．１μｍレベルとするＳＯＩウェーハが要求されるよ
うになっている。このような極薄のＳＯＩウェーハを製
造するには、従来の研削や研磨による機械的な加工によ
る方法では不可能で、その仕上げ研磨方法としては、例
えば不純物によるエッチストップ法（K.Imai,Jpn.J.App
l.Phys.,30(1991)1154) や、ドライエッチング法（特開
平５−３３５３９５号公報参照）等が挙げられる。Particularly, in recent years, high integration of semiconductor devices,
With the increase in speed, the active layer of an SOI wafer tends to be thinned, and for example, an SOI wafer having an active layer of 0.1 μm level for forming a semiconductor element is required. It is impossible to manufacture such an ultra-thin SOI wafer by a conventional mechanical processing method such as grinding or polishing. As a finish polishing method, for example, an etch stop method by impurities (K.Imai, Jpn. .J.App
L. Phys., 30 (1991) 1154), dry etching method (see Japanese Patent Laid-Open No. 5-335395), and the like.
【０００４】ところで不純物によるエッチストップ法を
図３で説明すると、まず、（Ａ）通常の厚さ６００〜１
０００μｍの支持体となる第一のシリコンウェーハ（以
下、これをベースウェーハとする）の鏡面側に、厚さが
１μｍ以下の酸化膜を形成せしめ、一方、半導体素子形
成の活性層となる厚さ６００〜８００μｍの第二のシリ
コンウェーハ（以下これをボンドウェーハとする）の鏡
面側には、Ｂ（ホウ素）不純物を熱拡散法やイオン注入
法により導入し、厚さが約０．５μｍで濃度が１０20cm
-3前後の不純物の高濃度層を形成させる。次に、（Ｂ）
この前処理を施したそれぞれのウェーハの鏡面同士を室
温の清浄な雰囲気下で重ね合わせて接合し、酸素雰囲気
下において７００〜１０００℃で約１時間、結合のため
の熱処理を行う。この熱処理によって不純物はボンドウ
ェーハ中を拡散し、不純物高濃度層の厚さが増すと同時
に、その濃度はいくぶん低下する。（Ｃ）この結合熱処
理により得られた結合ウェーハ（ＳＯＩウェーハの先駆
体）の、ボンドウェーハ側について、その厚さが５〜１
０μｍとなるまで、機械的な研削や研磨によって除去し
薄層化する。次に、（Ｄ）エッチング液としてエチレン
ジアミンピロカテコール水（エチレンジアミン 3400c
c、ピロカテコール 600ｇ、水 1600cc）により１００
〜１１０℃の温度で処理すると、ボンドウェーハにおけ
る不純物濃度の低い部分は速やかにエッチングが進行し
除去されるが、不純物濃度が高くなるにつれエッチング
速度は遅くなり、ある濃度以上になるとエッチングはス
トップする。この不純物によるエッチストップ法により
ボンドウェーハ側を約０．５μｍ厚さの不純物濃度層と
なるまで薄膜化させることができる。次に、（Ｅ）この
状態でボンドウェーハ側を熱酸化すると、不純物はその
表面で成長する酸化膜に取り込まれ、その条件を制御す
ることによって、不純物濃度が１／１０〜１／２０以下
に低下し、その厚さが０．１〜０．２μｍのシリコン薄
層を、前記結合用の酸化膜と、前記表面に成長させた酸
化膜の間に形成させることができ、（Ｆ）この表面酸化
膜を希フッ酸で除去することにより極薄のＳＯＩウェー
ハが製造される、という方法である。An etch stop method using impurities will be described with reference to FIG. 3. First, (A) a normal thickness of 600 to 1
An oxide film having a thickness of 1 μm or less is formed on the mirror surface side of a first silicon wafer (hereinafter, referred to as a base wafer) serving as a support of 000 μm, while a thickness serving as an active layer for semiconductor device formation. B (boron) impurities are introduced into the mirror surface side of a second silicon wafer of 600 to 800 μm (hereinafter referred to as a bond wafer) by a thermal diffusion method or an ion implantation method, and the thickness is about 0.5 μm. Is 10 20 cm
-A high concentration layer of impurities around -3 is formed. Next, (B)
The mirror surfaces of the pretreated wafers are superposed and bonded in a clean atmosphere at room temperature, and a heat treatment for bonding is performed in an oxygen atmosphere at 700 to 1000 ° C. for about 1 hour. This heat treatment causes impurities to diffuse in the bond wafer, increasing the thickness of the high impurity concentration layer and at the same time decreasing its concentration to some extent. (C) The thickness of the bonded wafer (precursor of the SOI wafer) obtained by this bonding heat treatment is 5 to 1 on the bond wafer side.
The layer is removed by mechanical grinding or polishing until it becomes 0 μm, and a thin layer is formed. Next, (D) as an etching solution, ethylenediamine pyrocatechol water (ethylenediamine 3400c
c, 600 g of pyrocatechol, 1600 cc of water)
When the treatment is carried out at a temperature of up to 110 ° C., the portion of the bond wafer having a low impurity concentration is rapidly etched and removed, but the etching rate becomes slower as the impurity concentration becomes higher, and the etching stops when the concentration exceeds a certain level. . By this etch stop method using impurities, the bond wafer side can be thinned to an impurity concentration layer having a thickness of about 0.5 μm. Next, (E) when the bond wafer side is thermally oxidized in this state, the impurities are taken into the oxide film growing on the surface, and the impurity concentration is reduced to 1/10 to 1/20 or less by controlling the conditions. A thin silicon layer having a reduced thickness of 0.1 to 0.2 μm can be formed between the bonding oxide film and the oxide film grown on the surface, (F) this surface In this method, an ultrathin SOI wafer is manufactured by removing the oxide film with dilute hydrofluoric acid.
【０００５】[0005]
【発明が解決しようとする課題】しかしこのような極薄
のＳＯＩウェーハ製造方法においては、前記ＳＯＩ層の
薄層化のための機械的な研削や研磨の工程で、また、こ
のＳＯＩウェーハを使用して半導体デバイスを作製する
工程において、結合が不充分で剥離を起こすという問題
がある。例えば、２枚のウェーハを接合し、熱処理工程
を経て結合ウェーハとなった段階で、ボンドウェーハを
通常５〜１０μｍ程度にまで研削研磨する際にウェーハ
間の剥離が生じるものである。特に、鏡面上に高濃度層
を形成したボンドウェーハと、鏡面を酸化したベースウ
ェーハとの結合によって得られた結合ウェーハの場合に
は、未結合部分（これをボイドという）が生じたり、結
合強度が低下し、結合部分が剥離したりするという問題
が往々にして起こった。However, in such an ultra-thin SOI wafer manufacturing method, this SOI wafer is used in the mechanical grinding and polishing steps for thinning the SOI layer. Then, in the process of manufacturing a semiconductor device, there is a problem that the bond is insufficient and peeling occurs. For example, when two wafers are bonded and a bonded wafer is formed through a heat treatment process, separation between the wafers occurs when the bond wafer is usually ground and polished to about 5 to 10 μm. In particular, in the case of a bonded wafer obtained by bonding a bond wafer with a high-concentration layer formed on the mirror surface to a base wafer with the mirror surface oxidized, an unbonded part (this is called a void) is generated, or the bond strength is increased. Often occurs, and the problem of peeling of the bonded portion often occurs.
【０００６】発明者がその原因を追跡した結果、通常の
鏡面ウェーハ同士の接合の場合は、両面の接合面とも鏡
面であり、その表面粗さは、例えばレーザー光散乱強度
を基にしたヘイズレベルで評価すると、検出電圧７００
Ｖでほぼ１０bit 程度以下である。この鏡面の一方、ま
たは双方を熱酸化させて互いに接合し、結合熱処理を施
し、ＳＯＩウェーハを製造する場合には、良好な結合体
が得られる。しかし、前記ＢやＳｂ（アンチモン）不純
物の高濃度層を有するウェーハの表面は、熱拡散やイオ
ンインプランテーションを施す際に面荒れを生じてお
り、このような面荒れを持つウェーハを結合しても強固
な結合が得られず、ＳＯＩ層の薄膜化における研磨工程
や、薄膜化後の半導体デバイス作製工程で、結合部分が
剥離してしまうことがわかった。本発明はこのような問
題点に鑑み、極薄のＳＯＩウェーハの製造時において、
またこのＳＯＩウェーハより半導体デバイスを作製する
過程において、剥離を発生しない、強固に結合したＳＯ
Ｉウェーハを得ることを目的とする。As a result of tracing the cause by the inventor, in the case of ordinary bonding of mirror-finished wafers, both bonding surfaces are mirror surfaces, and the surface roughness is, for example, the haze level based on the laser light scattering intensity. When evaluated with, the detection voltage is 700
V is about 10 bits or less. When one or both of these mirror surfaces are thermally oxidized to bond them to each other and a bonding heat treatment is performed to manufacture an SOI wafer, a good bonded body is obtained. However, the surface of the wafer having the high-concentration layer of B or Sb (antimony) impurities is roughened when thermal diffusion or ion implantation is performed. It was found that a strong bond was not obtained, and the bonded portion was peeled off in the polishing step in thinning the SOI layer and the semiconductor device manufacturing step after thinning. In view of these problems, the present invention provides a method for manufacturing an extremely thin SOI wafer,
Further, in the process of manufacturing a semiconductor device from this SOI wafer, a strongly bonded SO that does not cause peeling
The purpose is to obtain an I-wafer.
【０００７】[0007]
【課題を解決するための手段】すなわち本発明は、２枚
のシリコン鏡面ウェーハのうち、第一のシリコン鏡面ウ
ェーハの表面に酸化膜を形成し、第二のシリコン鏡面ウ
ェーハに不純物の高濃度層を形成した後、互いに接触さ
せて接合し、これに加熱処理を施して強固に結合させて
なるＳＯＩウェーハにおいて、不純物の高濃度層を形成
した前記第二のウェーハの接合すべき表面を研磨後に、
接合が行われていることを特徴とするＳＯＩウェーハを
要旨とし、またその製造方法をも要旨とするものであ
る。That is, according to the present invention, an oxide film is formed on the surface of a first silicon mirror surface wafer of two silicon mirror surface wafers, and a high concentration layer of impurities is formed on the second silicon mirror surface wafer. In the SOI wafer obtained by contacting with each other and bonding and subjecting to heat treatment to firmly bond the two, after the surfaces to be bonded of the second wafer having the high-concentration layer of impurities formed are polished, ,
The gist is an SOI wafer characterized by being bonded, and the gist is a manufacturing method thereof.
【０００８】以下にこれをさらに詳述する。本発明にお
ける、不純物によるエッチストップ法を用いる極薄のＳ
ＯＩウェーハの製造方法については、図３によって先に
説明した通りであるので、その詳細は省略する。すなわ
ち、本発明は図３における（Ａ）及び（Ｂ）の工程、熱
拡散やイオンインプランテーションにより、鏡面の表面
に不純物の高濃度拡散層を形成したシリコンウェーハ
（ボンドウェーハ）と、鏡面に酸化膜をつけた支持基板
としてのシリコンウェーハ（ベースウェーハ）との鏡面
側同士を接合させるにあたり、前記の拡散処理を施した
ボンドウェーハの接合すべき表面を再度研磨し、然る後
に、この接合されたウェーハに熱処理を施して強固な結
合ウェーハ（ＳＯＩウェーハの先駆体）を得ることを特
徴とするものである。次いで、（Ｃ）〜（Ｆ）の工程順
に従って、この結合ウェーハのボンドウェーハ側を、５
〜１０μｍ厚まで研削研磨した後、この研削研磨面を不
純物によるエッチストップ法によって前記拡散層を表出
させる。さらに熱酸化処理を施すことによって、拡散層
中の不純物濃度を薄めると同時に、ＳＯＩ層の厚さを規
定し、この薄膜化されたシリコン層の上に生じた酸化膜
をＨＦ処理により除去して、約０．２μｍ厚さか、それ
以下のシリコン薄膜を有するＳＯＩウェーハを得、これ
によって本発明は完結する。This will be described in more detail below. In the present invention, ultra-thin S using the impurity-based etch stop method is used.
The method of manufacturing the OI wafer is as described above with reference to FIG. That is, according to the present invention, the steps (A) and (B) in FIG. 3, a silicon wafer (bond wafer) in which a high-concentration diffusion layer of impurities is formed on the surface of the mirror surface by thermal diffusion or ion implantation, and oxidation on the mirror surface are performed. In bonding the mirror surface sides of the silicon wafer (base wafer) as the supporting substrate with the film, the surfaces to be bonded of the bond wafer that has been subjected to the above-mentioned diffusion treatment are polished again, and after that, this bonding is performed. The wafer is heat-treated to obtain a strong bonded wafer (a precursor of the SOI wafer). Then, according to the order of the steps (C) to (F), the bond wafer side of this bonded wafer is set to 5
After grinding and polishing to a thickness of 10 μm, the diffusion layer is exposed on the ground and polished surface by an etch stop method using impurities. By further performing thermal oxidation treatment, the impurity concentration in the diffusion layer is thinned, and at the same time, the thickness of the SOI layer is defined, and the oxide film formed on the thinned silicon layer is removed by HF treatment. An SOI wafer having a silicon thin film having a thickness of about 0.2 μm or less is obtained, which completes the present invention.
【０００９】前記不純物拡散処理を施したボンドウェー
ハ表面の面荒れについてであるが、図４はその面荒れ
を、ＡＦＭ（Atomic Force Microscope:原子間力顕微
鏡）によるＲＭＳ値（単位ｎｍ）で測定した値と、LS-6
000 （日立電子エンジニアリング社製測定器製品名）を
使用し、レーザー光散乱強度によるヘイズレベル（単位
bit ）で測定した値とを比較したものである。その結
果、ＲＭＳ値とbit 値は、大凡の相関関係を示し、例え
ばｐ型鏡面シリコンウェーハにＢ拡散をしたもののＲＭ
Ｓ値＝０．３ｎｍに対し、そのヘイズレベルは検出電圧
７００Ｖ（ＰＶ＝７００Ｖ）において約５４bit の値で
ある。したがって本発明における面荒れの表示は、その
測定が簡便なヘイズレベルを示すbit 値を採用した。な
お、ＰＷ／ｐ型は、導電型がｐ型の鏡面シリコンウェー
ハを、ＰＷ／ｎ型は導電型がｎ型の鏡面シリコンウェー
ハを示し、ＰＷのＢ拡散／ｐ型、ＰＷのＢ拡散／ｎ型
は、その各々についてＢ拡散を行ったものを指してい
る。Regarding the surface roughness of the bond wafer surface subjected to the impurity diffusion treatment, FIG. 4 shows the surface roughness measured by an RMS value (unit: nm) by an AFM (Atomic Force Microscope). Value and LS-6
000 (Hitachi Denshi Engineering Co., Ltd. measuring instrument product name) is used, and the haze level (unit:
It is a comparison with the value measured in bit). As a result, the RMS value and the bit value show a general correlation, for example, the RM of a p-type mirror-polished silicon wafer with B diffusion.
While the S value is 0.3 nm, the haze level is a value of about 54 bits at the detection voltage of 700V (PV = 700V). Therefore, for the display of the surface roughness in the present invention, the bit value indicating the haze level which is easy to measure is adopted. The PW / p type indicates a specular silicon wafer whose conductivity type is p type, and the PW / n type indicates a specular silicon wafer whose conductivity type is n type. PW B diffusion / p type, PW B diffusion / n The mold refers to the B diffusion for each of them.
【００１０】また、前記拡散処理を施したボンドウェー
ハの接合表面の研磨は、公知の鏡面研磨方法によって行
われる。すなわち、その代表的な研磨方法はメカノケミ
カル研磨法で、シリコンウェーハを鏡面化する場合は通
常、１次、２次、仕上げの３段階の研磨を行い、ウェー
ハ表面層の２０μｍ前後が取り代として除去されている
が、本発明の場合はその仕上げ研磨に相当する鏡面研磨
条件で、その取り代も１μｍ以下で０．１〜０．２μｍ
のレベルであれば良い。あるいはこの鏡面研磨の代わり
に、精密研削により同等の処理を行ってもよい。図５
は、上記鏡面研磨法による研磨時間とヘイズレベルとの
関係を見たもので、たまたまこの条件の場合は４分以上
の研磨により２０bit 以下のヘイズレベルに到達してい
ることがわかる。なお、鏡面研磨後の表面粗さは、鏡面
シリコンウェーハと同様の２０bit 以下（図４によれば
ＡＦＭ測定で０．１５ｎｍ以下）が好ましいが、これに
限定されるものではなく、また鏡面研磨の取り代の厚さ
は、拡散層が薄くなり過ぎシート抵抗に影響しない程度
に抑えることが必要である。The polishing of the bonding surface of the bond wafer which has been subjected to the diffusion treatment is performed by a known mirror polishing method. That is, a typical polishing method is a mechanochemical polishing method, and when a silicon wafer is mirror-finished, usually, three-step polishing of primary, secondary, and finishing is performed, and about 20 μm of the wafer surface layer is used as a stock removal. Although removed, in the case of the present invention, the polishing allowance is 0.1 μm or less and 0.1 μm to 0.2 μm under mirror polishing conditions corresponding to the final polishing.
Any level is acceptable. Alternatively, instead of this mirror polishing, an equivalent process may be performed by precision grinding. FIG.
Shows the relationship between the polishing time and the haze level by the mirror polishing method, and it can be seen that, under these conditions, the haze level of 20 bits or less is reached by polishing for 4 minutes or longer. The surface roughness after mirror polishing is preferably 20 bits or less (0.15 nm or less in AFM measurement according to FIG. 4), which is the same as that of a mirror silicon wafer, but is not limited to this. It is necessary to control the thickness of the stock removal to such an extent that the diffusion layer becomes too thin and does not affect the sheet resistance.
【００１１】本発明により、不純物高濃度層の形成時に
生じたシリコンウェーハの面荒れがあっても、拡散層の
シート抵抗に影響を与えないようにして、その面荒れ表
面を研磨することによって十分な結合強度を有するＳＯ
Ｉウェーハを得ることができる。また、本発明は、ベー
スウェーハのみに酸化膜を有するものであるが、酸化膜
を形成させるに際して、ボンドウェーハの不純物拡散層
に影響しない範囲において、酸化膜がボンドウェーハに
あるか、または双方のウェーハにあってもよい。すなわ
ち、Ｂ不純物拡散ボンドウェーハにおいて、酸化膜形成
の温度が９００℃以下であれば、本発明の適用が可能で
あることが確認されている。According to the present invention, even if the surface of the silicon wafer is roughened when the high-concentration impurity layer is formed, it is sufficient to polish the roughened surface without affecting the sheet resistance of the diffusion layer. With strong bond strength
I wafer can be obtained. Further, the present invention has an oxide film only on the base wafer, but when forming the oxide film, the oxide film is present on the bond wafer or both of them within a range that does not affect the impurity diffusion layer of the bond wafer. It may be on the wafer. That is, it has been confirmed that the present invention can be applied to a B-impurity-diffused bond wafer as long as the oxide film formation temperature is 900 ° C. or lower.
【００１２】[0012]
【発明の実施の形態】次に本発明の実施の形態につい
て、実施例、比較例を挙げて説明する。 （実施例、及び比較例１、比較例２）ボンドウェーハと
して直径１２５ｍｍ、厚さ６２５μｍの鏡面研磨したｎ
型シリコンウェーハを用意した。この鏡面ウェーハの表
面粗さをLS-6000 （前出測定器）を用い、検出電圧７０
０Ｖで評価したところ、そのヘイズレベルは１０bitで
あった。このシリコンウェーハは図１（ｂ）の●印で示
され、これを比較例１とした。同じくこのシリコンウェ
ーハについて、その鏡面へＰＢＦ(Poly Boron Film 6M-
10；東京応化工業社製製品名）を塗布し、１０５０℃、
４０分間、Ｎ2 雰囲気の条件でこのＢをウェーハに拡散
させた後、ウェーハをNH4OH ：H2O2：H2O ＝１：１：８
０の洗浄液（以下ＳＣ−１と称す）で洗浄した。その後
ＨＦ５％液、１分間浸漬によりこのウェーハのＢＳＧ
（Boron SilicateGlass）を除去し、次いで８００℃で
５分間、パイロ酸化によりボロンシリサイド除去酸化を
行った。さらにＨＦ５％液、１分間浸漬で酸化膜を除去
した後、ウェーハをＳＣ−１で洗浄し、Ｂ拡散ウェーハ
を作製した。このウェーハの接合面である拡散面の表面
粗さを、LS-6000 （前出測定器）を用い、検出電圧７０
０Ｖで測定したところ、６７bit で、非常に粗かった。
この状態のボンドウェーハは図１（ｂ）の■印で示さ
れ、これを比較例２のボンドウェーハとした。このウェ
ーハの拡散面のシート抵抗の面内分布を測定した結果、
図２（ａ）に示すようになり、その平均シート抵抗ρS
は１２．３５Ω／□であった。BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described with reference to Examples and Comparative Examples. (Examples and Comparative Examples 1 and 2) As a bond wafer, a mirror-polished n having a diameter of 125 mm and a thickness of 625 μm was used.
A type silicon wafer was prepared. The surface roughness of this mirror-finished wafer was measured with an LS-6000 (measurement instrument described above) using a detection voltage of 70.
When evaluated at 0 V, the haze level was 10 bits. This silicon wafer is indicated by a black circle in FIG. 1 (b), which was designated as Comparative Example 1. Similarly, for this silicon wafer, PBF (Poly Boron Film 6M-
10; product name manufactured by Tokyo Ohka Kogyo Co., Ltd., applied at 1050 ° C.,
After diffusing this B into the wafer for 40 minutes in the N 2 atmosphere, the wafer is NH 4 OH: H 2 O 2 : H 2 O = 1: 1: 8
It was washed with No. 0 washing liquid (hereinafter referred to as SC-1). After that, HF 5% liquid is soaked for 1 minute in BSG of this wafer.
(Boron SilicateGlass) was removed, and then boron silicide removal oxidation was performed by pyrooxidation at 800 ° C. for 5 minutes. Further, the oxide film was removed by immersion in a HF 5% solution for 1 minute, and then the wafer was washed with SC-1 to produce a B diffusion wafer. The surface roughness of the diffusion surface, which is the bonding surface of this wafer, was measured with an LS-6000 (measurement device described above) at a detection voltage of 70
When measured at 0 V, it was 67 bits and was very coarse.
The bond wafer in this state is shown by a black square mark in FIG. 1B, and this was used as a bond wafer of Comparative Example 2. As a result of measuring the in-plane distribution of the sheet resistance of the diffusion surface of this wafer,
The average sheet resistance ρ S is as shown in FIG.
Was 12.35Ω / □.
【００１３】このウェーハの拡散面を、荷重１５０ｇ/c
m2、研磨速度０．０２μｍ／分で５分間、鏡面研磨を施
した（研磨の取り代は０．１μｍ）後、表面粗さを測定
したところ、２０bit であった。このボンドウェーハは
図１（ｂ）の×印で示され、これを実施例相当のボンド
ウェーハとした。また、このウェーハのシート抵抗の面
内分布を再度測定した結果を図２（ｂ）に示す。鏡面研
磨前と比べてほぼ同程度の面内分布及び平均シート抵抗
ρS を有することから、上述の鏡面研磨がウェーハへ与
える影響は小さいことがわかる。なお、図２（ａ）、
（ｂ）中の＋、−で示した領域は、それぞれシート抵抗
が平均シート抵抗ρS より大きい領域、小さい領域であ
ることを示している。A load of 150 g / c was applied to the diffusion surface of this wafer.
After performing mirror polishing for 5 minutes at m 2 and a polishing rate of 0.02 μm / min (the polishing allowance was 0.1 μm), the surface roughness was measured and found to be 20 bits. This bond wafer is shown by a cross mark in FIG. 1B, and this was used as a bond wafer corresponding to the example. Further, FIG. 2B shows the result of re-measurement of the in-plane distribution of the sheet resistance of this wafer. Since the in-plane distribution and the average sheet resistance ρ S are almost the same as those before the mirror polishing, it is understood that the above-mentioned mirror polishing has a small influence on the wafer. In addition, FIG.
Regions indicated by + and − in (b) indicate regions where the sheet resistance is larger than the average sheet resistance ρ S and smaller than the average sheet resistance ρ S , respectively.
【００１４】（比較例３）ボンドウェーハのＢ拡散工程
において、Ｂ拡散とボロンシリサイド除去酸化を一回の
熱処理で行う以外は、比較例２と同一の条件でＢ拡散ウ
ェーハを作製し、その表面粗さを測定したところ、４０
bit であった。これを比較例３のボンドウェーハとし、
図１（ｂ）の□印で示した。(Comparative Example 3) In the B diffusion step of a bond wafer, a B diffusion wafer was prepared under the same conditions as in Comparative Example 2 except that B diffusion and boron silicide removal oxidation were performed in a single heat treatment. When the roughness was measured, it was 40
It was a bit. This is a bond wafer of Comparative Example 3,
It is shown by a □ mark in FIG.
【００１５】直径１２５ｍｍ、厚さ６２５μｍのｐ型シ
リコンウェーハを用意し、１１００℃、３０分の条件で
パイロ酸化することによって０．５μｍ厚さの熱酸化膜
を形成したベースウェーハを作製した。このベースウェ
ーハと、前記の諸条件で作製した実施例、比較例１〜３
用のボンドウェーハについて結合熱処理の試験を行っ
た。 すなわち、このベースウェーハと上述の各種ボン
ドウェーハの鏡面側同士を室温にて重ね合わせて接合ウ
ェーハとし、この接合ウェーハを酸素雰囲気下で７００
℃、８００℃、９００℃の温度により各６０分の結合熱
処理を行った。各結合熱処理後の結合ウェーハの結合強
度を、ブレード法で測定した。ブレード法は、結合させ
た２枚のウェーハの間に刃を差し込み、２枚のウェーハ
が剥離した先端から刃の刃先までの距離により、結合強
度を求める方法である（W.P.Maszara,J.Appl.Phys.,64
(1988)4943 ）。その結果を図１（ａ）に示す。A p-type silicon wafer having a diameter of 125 mm and a thickness of 625 μm was prepared and pyrooxidized at 1100 ° C. for 30 minutes to prepare a base wafer on which a thermal oxide film having a thickness of 0.5 μm was formed. This base wafer, and Examples and Comparative Examples 1 to 3 produced under the above-mentioned conditions
A bond heat treatment test was performed on the bond wafers. That is, the mirror surface sides of the base wafer and the various bond wafers described above are superposed at room temperature to form a bonded wafer, and the bonded wafer is subjected to 700 ° C. in an oxygen atmosphere.
Bonding heat treatment was performed for 60 minutes at temperatures of 800 ° C., 800 ° C., and 900 ° C., respectively. The bond strength of the bonded wafer after each bonding heat treatment was measured by the blade method. The blade method is a method in which a blade is inserted between two bonded wafers and the bond strength is determined by the distance from the tip of the two wafers separated to the blade edge (WPMaszara, J.Appl.Phys ., 64
(1988) 4943). The result is shown in FIG.
【００１６】図１（ａ）において、●は比較例１として
の、不純物未拡散の鏡面シリコンウェーハ、×は実施
例、■は比較例２、□は比較例３の値である。図１
（ａ）より、表面粗さが小さいほど、ウェーハの結合強
度は向上したことがわかる。In FIG. 1 (a), ● is a specular silicon wafer with no impurity diffusion as Comparative Example 1, × is an Example, ■ is a Comparative Example 2, and □ is a Comparative Example 3. FIG.
From (a), it can be seen that the smaller the surface roughness, the higher the bonding strength of the wafer.
【００１７】[0017]
【発明の効果】本発明のＳＯＩウェーハ及びその製造方
法によれば、不純物拡散層を有するボンドウェーハと、
ベースウェーハとの強固な結合が達成でき、不純物高濃
度層のシート抵抗に影響を与えることがなく、ＳＯＩ層
の薄膜化における研削・研磨工程や、薄膜化後の半導体
デバイス作製工程での、結合剥離を低減化することがで
きる。これにより、不純物高濃度層を有するボンドウェ
ーハと、酸化膜を有するベースウェーハとからなる結合
ウェーハに対し、不純物によるエッチストップ法を適用
して極薄のＳＯＩウェーハの製造が可能となる。According to the SOI wafer and the manufacturing method thereof of the present invention, a bond wafer having an impurity diffusion layer,
A strong bond with the base wafer can be achieved, without affecting the sheet resistance of the high-concentration impurity layer, and it can be bonded in the grinding / polishing process for thinning the SOI layer and the semiconductor device manufacturing process after thinning. Peeling can be reduced. As a result, it becomes possible to manufacture an extremely thin SOI wafer by applying the impurity etch stop method to a bonded wafer composed of a bond wafer having a high impurity concentration layer and a base wafer having an oxide film.
【図１】本発明の実施例のウェーハ結合強度の、表面粗
さ・結合熱処理温度依存性を示す図である。 （ａ）ウェーハ結合強度の、結合熱処理温度依存性を示
す。 × ‥‥‥ 実施例 ● ‥‥‥ 比較例１ ■ ‥‥‥ 比較例２ □ ‥‥‥ 比較例３ （ｂ）（ａ）の各ボンドウェーハの表面粗さを示す。FIG. 1 is a diagram showing surface roughness / bonding heat treatment temperature dependence of wafer bonding strength in an example of the present invention. (A) Shows the bond heat treatment temperature dependence of the wafer bond strength. × …………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………。
【図２】本発明の実施例の拡散面の、鏡面研磨前後での
平均シート抵抗ρS 、標準偏差σ及びその面内分布の変
化を示す図で、（ａ）は鏡面研磨前、（ｂ）は鏡面研磨
後のものである。FIG. 2 is a diagram showing changes in average sheet resistance ρ S , standard deviation σ, and its in-plane distribution of a diffusing surface before and after mirror-polishing according to an embodiment of the present invention. ) Is after mirror polishing.
【図３】（Ａ）〜（Ｆ）は、高濃度層を有するボンドウ
ェーハと、酸化膜を有するベースウェーハとからなる結
合ウェーハについて、不純物によるエッチストップ法を
応用した極薄のＳＯＩウェーハの製造工程を説明する図
である。3 (A) to 3 (F) are bonded wafers having a high-concentration layer and a base wafer having an oxide film, which are ultra-thin SOI wafers to which an etch stop method by impurities is applied. It is a figure explaining a process.
【図４】LS-6000 とＡＦＭとによる面粗さ測定値の比較
を示す図である。FIG. 4 is a diagram showing a comparison of surface roughness measurement values by LS-6000 and AFM.
【図５】研磨時間によるヘイズレベルの変化を示す図で
ある。FIG. 5 is a diagram showing changes in haze level depending on polishing time.
Claims (3)
一のシリコン鏡面ウェーハの表面に酸化膜を形成し、第
二のシリコン鏡面ウェーハに不純物の高濃度層を形成し
た後、互いに接触させて接合し、これに加熱処理を施し
て強固に結合させてなるＳＯＩウェーハにおいて、不純
物の高濃度層を形成した前記第二のウェーハの接合すべ
き表面を研磨後に、接合が行われていることを特徴とす
るＳＯＩウェーハ。1. An oxide film is formed on the surface of a first silicon mirror surface wafer of the two silicon mirror surface wafers, and a high concentration layer of impurities is formed on the second silicon mirror surface wafer, and then contacted with each other. In an SOI wafer obtained by bonding and subjecting it to a strong bonding by heat treatment, the bonding is performed after polishing the surfaces to be bonded of the second wafer on which the high-concentration layer of impurities is formed. Characteristic SOI wafer.
一のシリコン鏡面ウェーハの表面に酸化膜を形成し、第
二のシリコン鏡面ウェーハに不純物の高濃度層を形成し
た後、互いに接触させて接合し、これに加熱処理を施し
て強固に結合させてなるＳＯＩウェーハを製造する方法
において、不純物の高濃度層を形成した前記第二のウェ
ーハの接合すべき表面の研磨後に、接合を行うことを特
徴とするＳＯＩウェーハの製造方法。2. Of two silicon mirror-finished wafers, an oxide film is formed on the surface of a first silicon mirror-finished wafer and a high-concentration layer of impurities is formed on the second silicon mirror-finished wafer, and then contacted with each other. In a method of manufacturing an SOI wafer in which the second wafer is bonded and then heat-treated to be strongly bonded, bonding is performed after polishing the surfaces to be bonded of the second wafer having a high-concentration layer of impurities. And a method for manufacturing an SOI wafer.
一のシリコン鏡面ウェーハの表面に酸化膜を形成し、第
二のシリコン鏡面ウェーハに不純物の高濃度層を形成し
た後、互いに接触させて接合し、これに加熱処理を施し
て強固に結合させた後、前記第二のシリコン鏡面ウェー
ハ側を薄膜化してＳＯＩウェーハを製造するに際し、不
純物の高濃度層を形成した前記第二のシリコン鏡面ウェ
ーハの接合すべき表面の研磨後に接合を行い、これに加
熱処理を行うことによって強固に結合させた後、前記第
二のシリコン鏡面ウェーハ側を、不純物の高濃度層によ
るエッチストップ法により薄膜化させることを特徴とす
るＳＯＩウェーハの製造方法。3. Of two silicon mirror-finished wafers, an oxide film is formed on the surface of a first silicon mirror-finished wafer, a high-concentration layer of impurities is formed on a second silicon mirror-finished wafer, and then contacted with each other. The second silicon mirror surface on which a high-concentration layer of impurities has been formed is used in manufacturing an SOI wafer by thinning the second silicon mirror surface wafer side after bonding and strongly bonding them by heat treatment. Bonding is performed after polishing the surfaces of the wafers to be bonded, and a heat treatment is performed to firmly bond them, and then the second silicon mirror surface wafer side is thinned by an etch stop method using a high-concentration impurity layer. A method of manufacturing an SOI wafer, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20822896A JP2930194B2 (en) | 1995-08-17 | 1996-08-07 | SOI wafer and method for manufacturing the same |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7-209451 | 1995-08-17 | ||
| JP20945195 | 1995-08-17 | ||
| JP20822896A JP2930194B2 (en) | 1995-08-17 | 1996-08-07 | SOI wafer and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09116125A true JPH09116125A (en) | 1997-05-02 |
| JP2930194B2 JP2930194B2 (en) | 1999-08-03 |
Family
ID=26516714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20822896A Expired - Fee Related JP2930194B2 (en) | 1995-08-17 | 1996-08-07 | SOI wafer and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2930194B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127244A (en) * | 1997-12-27 | 2000-10-03 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing semiconductor device |
| JP2008258304A (en) * | 2007-04-03 | 2008-10-23 | Sumco Corp | Method of manufacturing semiconductor substrate |
| US7867877B2 (en) | 2004-01-30 | 2011-01-11 | Sumco Corporation | Method for manufacturing SOI wafer |
| US7927957B2 (en) | 2008-09-12 | 2011-04-19 | Sumco Corporation | Method for producing bonded silicon wafer |
| US7955874B2 (en) | 2008-12-25 | 2011-06-07 | Sumco Corporation | Method of producing bonded silicon wafer |
-
1996
- 1996-08-07 JP JP20822896A patent/JP2930194B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127244A (en) * | 1997-12-27 | 2000-10-03 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing semiconductor device |
| US7867877B2 (en) | 2004-01-30 | 2011-01-11 | Sumco Corporation | Method for manufacturing SOI wafer |
| JP2008258304A (en) * | 2007-04-03 | 2008-10-23 | Sumco Corp | Method of manufacturing semiconductor substrate |
| US7855132B2 (en) | 2007-04-03 | 2010-12-21 | Sumco Corporation | Method of manufacturing bonded wafer |
| US7927957B2 (en) | 2008-09-12 | 2011-04-19 | Sumco Corporation | Method for producing bonded silicon wafer |
| US7955874B2 (en) | 2008-12-25 | 2011-06-07 | Sumco Corporation | Method of producing bonded silicon wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2930194B2 (en) | 1999-08-03 |
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