JPH0878467A - Semiconductor wafer, dicing method therefor and semiconductor device - Google Patents

Semiconductor wafer, dicing method therefor and semiconductor device

Info

Publication number
JPH0878467A
JPH0878467A JP6206988A JP20698894A JPH0878467A JP H0878467 A JPH0878467 A JP H0878467A JP 6206988 A JP6206988 A JP 6206988A JP 20698894 A JP20698894 A JP 20698894A JP H0878467 A JPH0878467 A JP H0878467A
Authority
JP
Japan
Prior art keywords
semiconductor
data area
cutting
chip
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6206988A
Other languages
Japanese (ja)
Inventor
Masahito Takita
雅人 瀧田
Junji Ogawa
淳二 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6206988A priority Critical patent/JPH0878467A/en
Publication of JPH0878467A publication Critical patent/JPH0878467A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)

Abstract

PURPOSE: To enhance the reliability of a semiconductor device built in an SCP by increasing the degree of freedom in the dicing dimension of a chip. CONSTITUTION: In a wafer 30, a data region 35 on which a required circuit is formed along with wire bonding pads 36 for external connection thereof is provided in the center of a larger number of chip regions 34 sectioned by section lines 32, 33. Interconnection pad groups 38 facing the wire bonding pads and arranged with interconnection pads 39 for external connection are formed on the outside in the data region 35. The wafer 30 is diced without traversing the data region 35 or the interconnection pad group 38 and a diced chip is packaged to produce a semiconductor device.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、分割寸法可変に半導体
チップを形成した半導体ウェーハと、そのウェーハの分
割方法と、その分割で得られた導体チップを使用する半
導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer having semiconductor chips formed with variable division dimensions, a method of dividing the wafer, and a semiconductor device using the conductor chips obtained by the division.

【０００２】近年、短期間に短手番で多機能半導体装置
や大容量半導体装置を製造するため、一つのパッケージ
に複数の半導体チップを実装した半導体装置、例えばＳ
ＣＰ(stacked chip package)が使用されるようになっ
た。In recent years, in order to manufacture a multifunctional semiconductor device and a large-capacity semiconductor device in a short turn in a short time, a semiconductor device having a plurality of semiconductor chips mounted in one package, for example, S
CP (stacked chip package) has come to be used.

【０００３】[0003]

【従来の技術】図13は、ＳＣＰに組み込んだ半導体装置
の構成例を示す断面図である。図13において半導体装置
１は、一対の半導体チップ２と３を背中合わせまたは向
かい合わせに配設し、半導体チップ２および３に設けた
所定のパッド（図示せず）と、半導体チップ２，３の側
方に配設したリード端子４とは、ボンディング・ワイヤ
５-1,5-2で接続し、半導体チップ２と３およびワイヤ５
-1,5-2（半導体チップ２，３とリード端子４との接続
部）は、パッケージ（樹脂モールド）６に封入する。2. Description of the Related Art FIG. 13 is a sectional view showing a structural example of a semiconductor device incorporated in an SCP. In FIG. 13, a semiconductor device 1 includes a pair of semiconductor chips 2 and 3 arranged back to back or facing each other, and a predetermined pad (not shown) provided on the semiconductor chips 2 and 3 and a side of the semiconductor chips 2 and 3. The lead terminals 4 arranged on one side are connected by bonding wires 5 -1 , 5 -2 , and the semiconductor chips 2 and 3 and the wires 5 are connected.
-1,5 -2 (the connection between the semiconductor chips 2 and 3 and the lead terminal 4) is enclosed in a package (resin mold) 6.

【０００４】このような半導体装置１等において、付加
機能の拡大等で機能の異なる複数個のチップを封入する
場合、チップサイズが異なる例えば半導体チップ２に対
し半導体チップ３が小さいと、チップ３に接続したボン
ディング・ワイヤ５-2は、チップ２に接続したボンディ
ング・ワイヤ５-1より長くなり、不要なインピーダンス
が発生するだけでなく、場合によってはチップ３のワイ
ヤ５-2がチップ２に接触したり、隣接するワイヤ５-2間
で接触する恐れがあった。In such a semiconductor device 1 or the like, when a plurality of chips having different functions are encapsulated due to expansion of additional functions, etc., if the semiconductor chip 3 is smaller than the semiconductor chip 2 having different chip sizes, the chip 3 becomes The connected bonding wire 5 -2 is longer than the bonding wire 5 -1 connected to the chip 2, not only generating unnecessary impedance, but also the wire 5 -2 of the chip 3 contacts the chip 2 in some cases. Or there is a risk of contact between adjacent wires 5-2 .

【０００５】そこで、前記問題点を解決するには、同一
パッケージに収容する複数個のチップサイズを揃える技
術が必要となる。図14は、同一パッケージに収容する複
数個のチップサイズを揃えるため、分割寸法可変とした
半導体チップの従来例の模式説明図である。Therefore, in order to solve the above-mentioned problems, a technique for aligning a plurality of chip sizes accommodated in the same package is required. FIG. 14 is a schematic explanatory diagram of a conventional example of a semiconductor chip having a variable division size in order to arrange a plurality of chip sizes to be accommodated in the same package.

【０００６】図14(a) において、特開平１−１１４０４
９号公報に開示されたチップ11は、所望の回路が形成さ
れている矩形のメイン領域 (回路セル) 12と、メイン領
域12の縁部に形成された複数個の第１のパッド13と、メ
イン領域12に隣接する複数個（４個）の配線領域14と、
配線領域14とメイン領域12とを仕切るスクライブ線15
と、配線領域14内に設けられ第１のパッド13と対向して
配置された複数個の第２のパッド16と、配線領域14内の
外側縁部に配置され第２のパッド16と配線17により接続
された複数個の第３のパッド18とを有し、図14(b) に示
す如くスクライブ線15によりメイン領域12と配線領域14
とを分離して使用するか、または、図14(c) に示す如く
対向する所定の第１のパッド13と第２のパッド16とを接
続して使用する。In FIG. 14 (a), Japanese Patent Laid-Open No. 1-11404
The chip 11 disclosed in Japanese Patent Publication No. 9 has a rectangular main region (circuit cell) 12 in which a desired circuit is formed, a plurality of first pads 13 formed at the edge of the main region 12, A plurality of (four) wiring areas 14 adjacent to the main area 12,
A scribe line 15 that separates the wiring area 14 from the main area 12
A plurality of second pads 16 provided in the wiring region 14 so as to face the first pads 13, and a second pad 16 and a wiring 17 arranged at the outer edge of the wiring region 14. 14B and a plurality of third pads 18 connected to each other by a scribe line 15 as shown in FIG. 14B.
Are used separately, or as shown in FIG. 14 (c), a predetermined first pad 13 and a second pad 16 which are opposed to each other are connected and used.

【０００７】図14(b) において、チップ11をそのまま使
用した半導体装置は、所定のパッド13とパッド16とをワ
イヤ21で接続し、所定のパッド18とリード端子22とをワ
イヤ５で接続し、チップ11とワイヤ５ (パッド18とリー
ド端子22との接続部) をパッケージに封入する。In FIG. 14 (b), the semiconductor device using the chip 11 as it is, the predetermined pad 13 and the pad 16 are connected by the wire 21, and the predetermined pad 18 and the lead terminal 22 are connected by the wire 5. The chip 11 and the wire 5 (the connecting portion between the pad 18 and the lead terminal 22) are enclosed in the package.

【０００８】図14(c) において、メイン領域12だけを使
用する半導体装置は、チップ11をスクライブ線15に沿っ
て分割（スクライブ）し、その分割によって得られたチ
ップ11-1の所定のパッド13を、ワイヤ５で所定のリード
端子22に接続し、チップ11-1とワイヤ５ (パッド13とリ
ード端子22との接続部) をパッケージに封入する。In FIG. 14 (c), the semiconductor device using only the main region 12 divides the chip 11 along the scribe line 15 (scribe), and obtains a predetermined pad of the chip 11 -1 obtained by the division. The wire 13 is connected to a predetermined lead terminal 22 with a wire 5, and the chip 11 -1 and the wire 5 (the connecting portion between the pad 13 and the lead terminal 22) are enclosed in a package.

【０００９】[0009]

【発明が解決しようとする課題】以上説明したように、
従来の半導体チップ11は、図14(b) に示す如くチップ11
をそのまま使用するかまたは、図14(c) に示す如くメイ
ン領域12の外縁部部でスクライブしたチップ11-1を使用
することになる。As described above,
The conventional semiconductor chip 11 is the chip 11 as shown in Fig. 14 (b).
Is used as it is, or the chip 11 -1 scribed at the outer edge of the main region 12 is used as shown in FIG. 14 (c).

【００１０】従って、図14(a) に破線24に示す如くチッ
プ11と11-1の中間寸法のチップが欲しいときは、破線24
に沿ってチップ11を分割する、即ち配線17を途中で切断
するようになる。Therefore, when a chip having an intermediate size between the chips 11 and 11 -1 is desired as shown by the broken line 24 in FIG.
The chip 11 is divided along the line, that is, the wiring 17 is cut in the middle.

【００１１】しかし、破線24に沿ってチップ11を分割し
たチップは、アルミニウム等にてなる配線17がチップ基
体 (シリコン基体) と全く同じに分割され難いため、図
15に示す如く、引き延ばされた配線17の切断端17-1が垂
れ下がってチップ基体にショートしたり、配線17の切り
粉17-2がチップ基体に被着することがあった。However, in the chip obtained by dividing the chip 11 along the broken line 24, it is difficult to divide the wiring 17 made of aluminum or the like into exactly the same as the chip base (silicon base).
As shown in FIG. 15, the cut end 17 -1 of the extended wiring 17 may hang down and short-circuit to the chip substrate, or the chips 17 -2 of the wiring 17 may adhere to the chip substrate.

【００１２】そのため、従来のチップ11はそのまま分割
しないまたはスクライブ線15で分割するか、の何れかの
方法で使用することになり、図14(a) に破線24に示す如
き寸法のチップが必要なときは、チップ11をそのまま使
用することになった。即ち、チップ11はサイズがデジタ
ル的にしか変化されず、設計当初予測できなかった大き
さのチップを得ることができなかった。Therefore, the conventional chip 11 is used by either not dividing it as it is or dividing it by the scribe line 15, and a chip having a size as shown by a broken line 24 in FIG. 14 (a) is required. In that case, I decided to use the chip 11 as it was. That is, the size of the chip 11 is changed only digitally, and it is impossible to obtain a chip whose size cannot be predicted at the time of design.

【００１３】[0013]

【課題を解決するための手段】本発明の半導体ウェーハ
は、区画線により区分された多数のチップ領域には、所
要回路および該回路の外部接続用ワイヤボンディングパ
ッドが形成されたデータ領域を中心部に設け、該ワイヤ
ボンディングパッドに対向し外部接続用中継パッドが整
列する中継パッド群が該データ領域の外側に形成されて
なる。In a semiconductor wafer of the present invention, in a large number of chip areas divided by comparting lines, a data area in which a required circuit and a wire bonding pad for external connection of the circuit are formed is a central portion. And a relay pad group facing the wire bonding pad and aligned with the relay pads for external connection are formed outside the data area.

【００１４】さらに、前記中継パッドがワイヤのダブ
ルボンディング可能な大きさであること、前記データ
領域の四方の前記中継パッド群形成領域の表面は、半導
体基板が表呈するまたは絶縁性カバー膜または酸化膜ま
たは該カバー膜と酸化膜の積層でおおわれてなること、
前記データ領域の四方にはそれぞれ複数の前記中継パ
ッド群が形成されてなること、前記データ領域の上下
方向および左右方向に形成した前記中継パッド群が、該
データ領域に対し対称位置または非対称位置に設けられ
たこと、前記データ領域と前記中継パッド群とに重複
しない位置にウェーハ切断用ガイドラインが形成してな
ること、前記ガイドラインが前記ウェーハに被着した
保護層の一部をエッチングしてなること、前記ガイド
ラインが前記ウェーハに被着した保護層の取り残しによ
って形成されてなること、である。Further, the relay pad has a size capable of double-bonding a wire, and the surfaces of the relay pad group formation regions on four sides of the data region are exposed by a semiconductor substrate or an insulating cover film or an oxide film. Or covered with a laminate of the cover film and the oxide film,
A plurality of relay pad groups are formed on each of the four sides of the data area, and the relay pad groups formed in the vertical direction and the horizontal direction of the data area are located symmetrically or asymmetrically with respect to the data area. Provided, a guideline for wafer cutting is formed at a position not overlapping the data area and the relay pad group, and the guideline is formed by etching a part of the protective layer deposited on the wafer. The guideline is formed by leaving a protective layer deposited on the wafer.

【００１５】本発明のウェーハ切断方法は、前記デー
タ領域に沿って切断すること、前記データ領域と前記
中継パッド群とを含むように切断すること、前記ガイ
ドラインに沿って切断すること、前記切断方法の組合
せでデータ領域の大きさが異なる一対の半導体チップを
同一寸法に切断すること、である。The wafer cutting method of the present invention includes cutting along the data area, cutting so as to include the data area and the relay pad group, cutting along the guideline, and the cutting method. A pair of semiconductor chips having different data area sizes are cut into the same size by the combination of.

【００１６】本発明の半導体装置は、前記方法で切断し
た半導体チップ、さらにデータ領域の大きさが異なるが
同一寸法に切断した一対の半導体チップを、一つのパッ
ケージに封入する。In the semiconductor device of the present invention, a semiconductor chip cut by the above method and a pair of semiconductor chips cut in the same size although the size of the data area is different are enclosed in one package.

【００１７】[0017]

【作用】上記手段の半導体ウェーハは、チップ領域の中
心部にデータ領域を設け、データ領域の周囲に中継用パ
ッドを配設した構成であり、半導体チップへの切断は、
必要に応じて中継用パッドを含むように、時には隣接す
るチップ領域内の中継用パッドを含むように設定するこ
とが可能となる。The semiconductor wafer of the above means has a structure in which the data area is provided in the center of the chip area and the relay pads are arranged around the data area.
It is possible to set the relay pads to be included as needed, and sometimes to include the relay pads in the adjacent chip areas.

【００１８】従って、半導体ウェーハを切断する半導体
チップの寸法は、中継用パッドを横切って切断しないこ
とが必要になるが、必要に応じて広範囲に設定可能にな
る。最小がデータ領域の外縁に沿った切断であり、従っ
て、前記半導体ウェーハを切断して得られる半導体チッ
プの最小寸法は、データ領域の寸法であり、チップ領域
を越えない最大寸法はチップ領域の区画線に囲まれた寸
法となる。そして、その最小寸法と最大寸法との間で
は、中継用パッドを横切ないことが必要になるが、図14
を用いて説明した従来の半導体チップより大幅に自由度
が増すことになる。Therefore, the dimensions of the semiconductor chip for cutting the semiconductor wafer need not be cut across the relay pads, but can be set in a wide range as needed. The minimum is the cutting along the outer edge of the data area, and therefore the minimum size of the semiconductor chip obtained by cutting the semiconductor wafer is the size of the data area, and the maximum size that does not exceed the chip area is the division of the chip area. The dimensions are surrounded by the line. It is necessary that the relay pad is not crossed between the minimum dimension and the maximum dimension.
The degree of freedom is significantly increased as compared with the conventional semiconductor chip described by using.

【００１９】そのため、本発明になるウェーハから本発
明方法で切断した半導体チップ、特にデータ領域の大き
さが異なる一対の半導体チップを封入した半導体装置
は、一対の半導体チップを同一寸法にすることが可能で
あり、従来技術においてボンディングワイヤによる前記
障害をなくすことができる。Therefore, in a semiconductor device in which a semiconductor chip cut from a wafer according to the present invention by the method according to the present invention, in particular, a pair of semiconductor chips having different data area sizes is enclosed, the pair of semiconductor chips may have the same size. This is possible, and it is possible to eliminate the obstacle caused by the bonding wire in the conventional technique.

【００２０】[0020]

【実施例】図１は本発明の第１の実施例のウェーハの説
明図、図２は図１のパッド群形成領域の断面図である。1 is an explanatory view of a wafer according to a first embodiment of the present invention, and FIG. 2 is a sectional view of a pad group forming region in FIG.

【００２１】図１(a) において、ウェーハ30は半導体基
板 (シリコン基板)31 の縦方向および横方向に複数本の
区画線32,33 を設け、区画線32,33 は、ウェーハ31を多
数のチップ領域34に区分する。In FIG. 1A, a wafer 30 is provided with a plurality of partition lines 32 and 33 in a vertical direction and a horizontal direction of a semiconductor substrate (silicon substrate) 31, and the partition lines 32 and 33 include a large number of wafers 31. The chip area 34 is divided.

【００２２】チップ領域34は拡大して図１(b) に示す如
く、中央部に角形のデータ領域35、即ち所望の回路と該
回路を外部接続するための複数のパッド36が形成された
データ領域35を設け、データ領域35の周囲のロ字形領域
（パッド群形成領域）37には、データ領域35の四辺に対
向する中継用パッド群38を設ける。The chip area 34 is enlarged and, as shown in FIG. 1B, a rectangular data area 35, that is, data in which a desired circuit and a plurality of pads 36 for externally connecting the circuit are formed in the central portion. An area 35 is provided, and a relay pad group 38 facing the four sides of the data area 35 is provided in a square-shaped area (pad group formation area) 37 around the data area 35.

【００２３】パッド群38は拡大して図１(c) に示す如
く、ワイヤのダブルボンディング可能な、例えば 150μ
m × 300μm の複数のパッド39が、データ領域35内のパ
ッド36に対向し形成される。As shown in FIG. 1 (c), the pad group 38 is enlarged to allow double bonding of wires, for example, 150 μm.
A plurality of m × 300 μm pads 39 are formed facing the pads 36 in the data area 35.

【００２４】図１のパッド群38形成領域37は図２(a) 〜
(d) に示す如く、半導体基板31の表面が露呈するまた
は、基板31の表面を保護するため薄い酸化膜40を形成す
るまたは、基体31の表面に防湿用カバー膜41を形成する
または、基体31の表面に酸化膜40とカバー膜41を積層し
た状態である。The pad group 38 forming region 37 of FIG. 1 is shown in FIG.
As shown in (d), the surface of the semiconductor substrate 31 is exposed, a thin oxide film 40 is formed to protect the surface of the substrate 31, a moisture-proof cover film 41 is formed on the surface of the base 31, or the base is formed. An oxide film 40 and a cover film 41 are laminated on the surface of 31.

【００２５】このようなパッド群形成領域37において、
一般に酸化シリコン(SiO2)にてなる酸化膜40，燐珪酸ガ
ラス(PSG) にてなるカバー膜41，酸化膜40とカバー膜41
の積層膜は非粘性であり、チップ領域34の切断に際し基
板31と同様な被切断性である。従って、チップ領域34に
おいて領域37内での切断は、パッド群38を避けるだけ
で、自由に位置設定できる。In such a pad group forming region 37,
An oxide film 40 generally made of silicon oxide (SiO 2 ), a cover film 41 made of phosphosilicate glass (PSG), an oxide film 40 and a cover film 41
The laminated film is non-viscous, and has the same cutting property as the substrate 31 when the chip region 34 is cut. Therefore, in the chip area 34, the cutting in the area 37 can be freely set by only avoiding the pad group 38.

【００２６】さらに、酸化膜40またはカバー膜41または
酸化膜40とカバー膜41の積層膜は電気的絶縁性を有す
る。そのため、ボンディングワイヤ43,45(図３参照）が
それらに接触しても、基体31と電気的に接続する恐れが
ない。Further, the oxide film 40 or the cover film 41 or the laminated film of the oxide film 40 and the cover film 41 has an electrical insulating property. Therefore, even if the bonding wires 43 and 45 (see FIG. 3) come into contact with them, there is no possibility of being electrically connected to the base 31.

【００２７】図３は図１のウェーハから得たチップを収
納した半導体装置の断面図であり、図３(a) はパッド群
38を含まないようにウェーハ30を切断したチップ50を収
容した半導体装置、図３(b) はパッド群38を含むように
ウェーハ30を切断したチップ51を収容した半導体装置で
ある。FIG. 3 is a sectional view of a semiconductor device containing a chip obtained from the wafer of FIG. 1, and FIG. 3 (a) is a pad group.
A semiconductor device containing a chip 50 obtained by cutting the wafer 30 so as not to include the wafer 38 is shown in FIG. 3B. A semiconductor device having a chip 51 obtained by cutting the wafer 30 so as to include the pad group 38 is shown therein.

【００２８】図３(a) において、パッド群38を含まない
ように、即ちデータ領域35の輪郭に沿ってまたはデータ
領域35とパッド群38との間でウェーハ30を切断したチッ
プ50を収納した半導体装置42は、データ領域35内のパッ
ド36とリード端子22とをワイヤ43で接続し、チップ50と
ワイヤ43 (チップ50およびチップ50とリード端子22との
接続部) を樹脂パッケージ６に封入する。In FIG. 3A, a chip 50 obtained by cutting the wafer 30 is housed so as not to include the pad group 38, that is, along the contour of the data area 35 or between the data area 35 and the pad group 38. In the semiconductor device 42, the pad 36 in the data area 35 and the lead terminal 22 are connected by the wire 43, and the chip 50 and the wire 43 (the connection between the chip 50 and the chip 50 and the lead terminal 22) are enclosed in the resin package 6. To do.

【００２９】図３(b) において、データ領域35の四方に
パッド群38を含むように、即ちパッド群38と分割ガイド
ライン32,33 との間でウェーハ30を切断したチップ51を
収容した半導体装置44は、データ領域内パッド36と中継
パッド39とをワイヤ45で接続し、中継パッド39とリード
端子22とをワイヤ43で接続し、チップ51とワイヤ45およ
び43 (チップ51およびチップ51と端子22との接続部) を
樹脂パッケージ６に封入する。In FIG. 3 (b), a semiconductor device containing a chip 51 obtained by cutting the wafer 30 between the pad group 38 and the dividing guide lines 32, 33 so as to include the pad group 38 on all sides of the data area 35. In the reference numeral 44, the pad 36 in the data area and the relay pad 39 are connected by the wire 45, the relay pad 39 and the lead terminal 22 are connected by the wire 43, and the chip 51 and the wires 45 and 43 (chip 51 and chip 51 and the terminal 22) is sealed in the resin package 6.

【００３０】図４は図１のウェーハを切断する代表例の
説明図、図５はワイヤ接続方法の説明図である。図４
(a) において、半導体装置製造のためウェーハ30を切断
し半導体チップを切り出す方法には、 区画線32,33 に沿って切り出す、 データ領域35の輪郭を含む線に沿って切り出す、 チップ領域34の外側かつ隣接する四方のチップ領域34
のパッド群38を含まないように、例えば図中の破線を含
む線に沿って切り出す、 チップ領域34の外側かつ隣接する四方のチップ領域34
の隣接側パッド群38を含むように、例えば図中の一点鎖
線を含む線に沿って切り出す、 所要のチップ領域34を囲む８個のチップ領域34のデー
タ領域35とその外側のパッド群38を含むように、例えば
図中の二点鎖線を含む線に沿って切り出す、 データ領域35の三方のパッド群38を含むように、例え
ば図中の三点鎖線を含む線に沿って切り出す、 等がある。FIG. 4 is an explanatory view of a typical example of cutting the wafer of FIG. 1, and FIG. 5 is an explanatory view of a wire connecting method. FIG.
In (a), the method of cutting the wafer 30 and cutting the semiconductor chip to manufacture the semiconductor device includes cutting along the dividing lines 32 and 33, cutting along the line including the contour of the data area 35, and cutting the chip area 34. Outside and adjacent four-sided chip area 34
The pad group 38 of is cut out along a line including a broken line in the drawing so as not to include the pad group 38 of
To include the adjacent pad group 38 of, for example, cut out along a line including a dashed line in the figure, So as to include, for example, cut out along a line including a two-dot chain line in the figure, so as to include a pad group 38 on three sides of the data area 35, for example, cut out along a line including a three-dot chain line in the figure is there.

【００３１】前記の方法またはの方法で切り出した
チップ34-2は、図４(b) に示す如く、データ領域内パッ
ドとチップ内中継パッドとをワイヤ45で接続し、該中継
パッドとリード端子22とをワイヤ43で接続するようにな
る。[0031] The chip 34 -2 cut out by the method or methods, as shown in FIG. 4 (b), a data area in the pad and the chip relay pads connected by wires 45, the relay pad and the lead terminals 22 and the wire 43 are connected.

【００３２】前記の方法で切り出したチップ34-3は、
図４(c) に示す如く、データ領域内パッドとデータ領域
内側の中継パッドとをワイヤ45で接続し、チップ内の内
側と外側の中継パッド間をワイヤ46で接続し、チップ内
の外側の中継パッド39とリード端子22とをワイヤ43で接
続するようになる。The chip 34 -3 cut out by the above method is
As shown in FIG. 4 (c), the pads in the data area and the relay pads inside the data area are connected by wires 45, and the relay pads inside and outside the chip are connected by wires 46, and The relay pad 39 and the lead terminal 22 are connected by the wire 43.

【００３３】そして、接続用ワイヤ43,45,46は、図５
(a),(c) の平面図に示す如くそれぞれが独立したワイヤ
であるまたは、図５(b) の平面図に示す如く、一端がデ
ータ領域内パッド36に接続し他端がリード端子22に接続
する１本のワイヤの中間部を、中継パッド39に接合す
る。従って、図５(a),(c) の中継パッド39はダブルボン
ディング可能な大きさが必要であるのに対し、図５(b)
の中継パッド39はシングルボンディング可能な大きさで
よい。The connecting wires 43, 45 and 46 are shown in FIG.
As shown in the plan views of (a) and (c), each is an independent wire, or as shown in the plan view of FIG. 5 (b), one end is connected to the data area pad 36 and the other end is the lead terminal 22. The intermediate portion of one wire connected to is connected to the relay pad 39. Therefore, the relay pad 39 of FIGS. 5 (a) and 5 (c) needs to have a size capable of double bonding, while FIG.
The relay pad 39 may be of a size that allows single bonding.

【００３４】図６は本発明の第２の実施例のウェーハに
おけるチップ領域の説明図、図７は本発明の第３の実施
例のウェーハにおけるチップ領域の説明図、図８は本発
明の第４の実施例のウェーハにおけるチップ領域の説明
図、図９は本発明の第５の実施例のウェーハにおけるチ
ップ領域の説明図、図１０は本発明の第６の実施例のウ
ェーハにおけるチップ領域の説明図である。FIG. 6 is an explanatory view of a chip area in the wafer of the second embodiment of the present invention, FIG. 7 is an explanatory view of a chip area in the wafer of the third embodiment of the present invention, and FIG. 4 is an explanatory view of a chip area in a wafer of a fourth embodiment, FIG. 9 is an explanatory view of a chip area in a wafer of a fifth embodiment of the present invention, and FIG. 10 is a chip area in a wafer of a sixth embodiment of the present invention. FIG.

【００３５】図６において、区画線32,33 に区分された
チップ領域34-1は、中央に角形のデータ領域35、即ち所
望の回路と該回路を外部接続するための複数のパッド36
(図１(b) 参照) が形成されたデータ領域35を設け、デ
ータ領域35の周囲のロ字形領域（パッド群形成領域）37
には、データ領域35の四辺に対向しそれぞれ３列の中継
用パッド群38を設ける。In FIG. 6, a chip area 34 -1 divided into partition lines 32 and 33 has a rectangular data area 35 in the center, that is, a desired circuit and a plurality of pads 36 for externally connecting the circuit.
(See FIG. 1B) is provided with a data area 35, and a square-shaped area (pad group formation area) 37 around the data area 35 is provided.
Is provided with relay pad groups 38 in three rows, each facing the four sides of the data area 35.

【００３６】図７において、区画線32,33 に区分された
チップ領域34-2は、中央に角形のデータ領域35、即ち所
望の回路と該回路を外部接続するための複数のパッド36
(図１(b) 参照) が形成されたデータ領域35を設け、デ
ータ領域35の周囲のロ字形領域（パッド群形成領域）37
には、データ領域35の四辺に対向する中継用パッド群3
8、データ領域35とパッド群38との間を横切る切断用ガ
イドライン32-1と33-1、パッド群38と分割ガイドライン
32,33 との間を横切る切断用ガイドライン32-2と33-2を
形成する。In FIG. 7, a chip area 34 -2 divided into partition lines 32 and 33 has a rectangular data area 35 in the center, that is, a desired circuit and a plurality of pads 36 for externally connecting the circuit.
(See FIG. 1B) is provided with a data area 35, and a square-shaped area (pad group formation area) 37 around the data area 35 is provided.
The relay pad group 3 facing the four sides of the data area 35.
8, cutting guidelines 32 -1 and 33 -1 , crossing between data area 35 and pad group 38, pad group 38 and dividing guide line
Form cutting guidelines 32 -2 and 33 -2 across 32,33.

【００３７】図８において、区画線32,33(図７参照）に
区分されたチップ領域34-3は、中央に角形のデータ領域
35、即ち所望の回路と該回路を外部接続するための複数
のパッド36 (図１(b) 参照) が形成されたデータ領域35
を設け、データ領域35の周囲のロ字形領域（パッド群形
成領域）37には、データ領域35の上下方向の２辺に平行
しそれぞれ２本の中継用パッド群38と、データ領域35の
左右方向の２辺に平行しそれぞれ３本の中継用パッド群
38を設ける。In FIG. 8, the chip area 34 -3 divided into the dividing lines 32 and 33 (see FIG. 7) is a rectangular data area in the center.
35, that is, a data area 35 in which a desired circuit and a plurality of pads 36 (see FIG. 1 (b)) for externally connecting the circuit are formed.
In the square-shaped area (pad group formation area) 37 around the data area 35, two relay pad groups 38 parallel to the two vertical sides of the data area 35 and left and right sides of the data area 35 are provided. 3 relay pad groups each parallel to the two sides of the direction
38 is provided.

【００３８】図９において、区画線32,33(図７参照）に
区分されたチップ領域34-4は、中央に角形のデータ領域
35、即ち所望の回路と該回路を外部接続するための複数
のパッド36 (図１(b) 参照) が形成されたデータ領域35
を設け、データ領域35の周囲のロ字形領域（パッド群形
成領域）37には、データ領域35の上下方向の２辺に平行
しそれぞれ２本の中継用パッド群38と、データ領域35の
左辺に平行する３本の中継用パッド群38と、データ領域
35の右辺に平行する４本の中継用パッド群38と、上下方
向に３本の切断用ガイドライン51と、左右方向に７本の
切断用ガイドライン52を設ける。In FIG. 9, a chip area 34 -4 sectioned by the dividing lines 32 and 33 (see FIG. 7) is a rectangular data area in the center.
35, that is, a data area 35 in which a desired circuit and a plurality of pads 36 (see FIG. 1 (b)) for externally connecting the circuit are formed.
In the square-shaped area (pad group forming area) 37 around the data area 35, two relay pad groups 38 each parallel to the two vertical sides of the data area 35 and the left side of the data area 35 are provided. Group of three relay pads 38 parallel to and data area
A group of four relay pads 38 parallel to the right side of 35, three cutting guide lines 51 in the vertical direction, and seven cutting guide lines 52 in the horizontal direction are provided.

【００３９】ただし、データ領域35の上方向に形成した
中継用パッド群38と、データ領域35の下方向に形成した
中継用パッド群38とは、その位置がデータ領域35に対し
非対称であり、かつ、データ領域35の左方向に形成した
中継用パッド群38とデータ領域35の右方向に形成した中
継用パッド群38とは、その位置がデータ領域35に対し非
対称であり、図中に一点鎖線で示すガイドライン51と52
は、データ領域35および中継用パッド群38から離し、隣
接する一対のパッド群38の間またはデータ領域35とパッ
ド群38との間を仕切るように設ける。However, the positions of the relay pad group 38 formed in the upper direction of the data area 35 and the relay pad group 38 formed in the lower direction of the data area 35 are asymmetric with respect to the data area 35, The positions of the relay pad group 38 formed to the left of the data area 35 and the relay pad group 38 formed to the right of the data area 35 are asymmetric with respect to the data area 35. Guidelines 51 and 52, shown in dashed lines
Is provided so as to be separated from the data area 35 and the relay pad group 38 and to partition between a pair of adjacent pad groups 38 or between the data area 35 and the pad group 38.

【００４０】このように中継用パッド群38を左右方向・
上下方向に非対称としたチップ領域34-4は、中継用パッ
ド群38が左右方向・上下方向に対称なものに比べ切断の
自由度が優れる、即ち中継用パッド群38に架かることな
く切断できる寸法設定の自由度が増すという特徴があ
る。In this way, the relay pad group 38
The chip area 34 -4 that is asymmetric in the vertical direction has a higher degree of freedom in cutting than the relay pad group 38 that is symmetrical in the left-right direction and the vertical direction, that is, a dimension that can be cut without straddling the relay pad group 38. The feature is that the degree of freedom in setting increases.

【００４１】図10において、区画線32,33 に区分された
チップ領域34-5は、中央に角形のデータ領域35、即ち所
望の回路と該回路を外部接続するための複数のパッド36
(図１(b) 参照) が形成されたデータ領域35を設け、デ
ータ領域35の周囲のロ字形領域（パッド群形成領域）37
には、データ領域35の四辺に対向しそれぞれ３列の中継
用パッド群38と、データ領域35の四隅が対向するコーナ
部分かつ上下方向・左右方向に延在する中継用パッド群
38の延長線の交差部に中継用パッド39-1を形成する。In FIG. 10, a chip area 34 -5 divided into partition lines 32, 33 has a rectangular data area 35 in the center, that is, a desired circuit and a plurality of pads 36 for externally connecting the circuit.
(See FIG. 1B) is provided with a data area 35, and a square-shaped area (pad group formation area) 37 around the data area 35 is provided.
, Three rows of relay pad groups 38 facing the four sides of the data area 35, and four corners of the data area 35, the relay pad groups extending in the vertical and horizontal directions at the opposite corners.
A relay pad 39 -1 is formed at the intersection of the extension lines of 38.

【００４２】領域37の各コーナ部分にそれぞれ複数個
(図は合計36個) ずつ形成した中継用パッド39-1は、ダ
ブルボンディング可能な大きさであり、データ領域内パ
ッド36を外部接続する際の中継地として適宜利用する、
例えばパッド36→一番内側のパッド群38のパッド39→そ
のパッド39に一番近いパッド39-1→他のパッド39-1→さ
らに他のパッド39-1→リード端子22 (図３参照）という
ように利用する。A plurality of parts are provided at each corner of the area 37.
(Figure total of 36) by the relay pad 39 -1 formed is double bondable sized appropriately utilizing data area in the pad 36 as a relay destination when an external connection,
For example, the pad 36 → the pad 39 of the innermost pad group 38 → the pad 39 -1 closest to the pad 39 → another pad 39 -1 → yet another pad 39 -1 → lead terminal 22 (see FIG. 3) And so on.

【００４３】図11は本発明の実施例になる半導体装置の
説明図であり、(a) は本発明になる一対の半導体チップ
をＳＣＰに組み込んだ半導体装置の縦断図、(b) は重ね
た一対の半導体チップの上側のものを示す横断図、(c)
は重ねた一対の半導体チップの下側のものを示す横断図
である。FIG. 11 is an explanatory view of a semiconductor device according to an embodiment of the present invention. (A) is a longitudinal sectional view of a semiconductor device in which a pair of semiconductor chips according to the present invention is incorporated in SCP, and (b) is a stack. Transverse view showing the upper side of the pair of semiconductor chips, (c)
[Fig. 3] is a cross-sectional view showing the lower side of a pair of stacked semiconductor chips.

【００４４】以上説明した実施例におけるチップ領域34
-1, 34-2, 34-3, 34-4, 34-5は、図４を用いて説明した
切り出し方法〜でウェーハから切断できるが，チッ
プ領域34-2と34-4は、ガイドライン32-1, 32-2, 33-1,
33-2または51,52 を切り出し時の目安として利用できて
便利である。The chip area 34 in the embodiment described above
-1, 34 -2, 34 -3, 34 -4, 34 -5, which can be cut from the wafer by cutting out the method ~ described with reference to FIG. 4, the chip area 34 -2 and 34 -4, guidelines 32 -1 , 32 -2 , 33 -1,,
It is convenient to use 33 -2 or 51,52 as a guide when cutting out.

【００４５】図11において、61は半導体装置、62,63 は
重ね合わせた一対の半導体チップ、22はリード端子、43
-1はリード端子22と半導体チップ62を接続するワイヤ、
43-2はリード端子22と半導体チップ63を接続するワイ
ヤ、６は半導体チップ62,63 およびワイヤ43-1と43-2を
封入した樹脂モールドである。In FIG. 11, 61 is a semiconductor device, 62 and 63 are a pair of stacked semiconductor chips, 22 is a lead terminal, and 43 is a lead terminal.
-1 is a wire connecting the lead terminal 22 and the semiconductor chip 62,
43 -2 wire connecting the lead terminals 22 and the semiconductor chip 63, 6 is a resin mold encapsulating the semiconductor chip 62, 63 and the wires 43 -1 and 43 -2.

【００４６】半導体チップ62は半導体チップ63の外形寸
法に合わせてウェーハを切断し形成したものであり、半
導体チップ62と63の外形寸法は同一である。ただし、半
導体チップ62のデータ領域35 (図１参照）は、半導体チ
ップ63のデータ領域35 (図１参照）より狭く、そのた
め、ワイヤ43-1はワイヤ43-2より長くなっている。The semiconductor chip 62 is formed by cutting a wafer according to the outer dimensions of the semiconductor chip 63, and the outer dimensions of the semiconductor chips 62 and 63 are the same. However, the data area 35 (see FIG. 1) of the semiconductor chip 62 is narrower than the data area 35 (see FIG. 1) of the semiconductor chip 63, so that the wire 43 -1 is longer than the wire 43 -2 .

【００４７】図12はウェーハ切断用ガイドラインの形成
例の説明図である。図12(a) において、データ領域35は
シリコン酸化層71, 各種の所要薄膜72〜75を積層し、最
上層にはカバー膜76を被着してなり、データ領域35の外
縁部には、データ領域35に沿ってウェーハを切断するた
めのガイド77を形成するための積層部78が、データ領域
35のパターン形成工程を利用し形成されている。FIG. 12 is an explanatory diagram of an example of forming a wafer cutting guideline. In FIG. 12 (a), the data area 35 is formed by laminating a silicon oxide layer 71 and various required thin films 72 to 75, and covering the uppermost layer with a cover film 76. The stack 78 for forming the guide 77 for cutting the wafer along the data area 35 is
It is formed by using 35 pattern forming steps.

【００４８】側面がカバー膜76に被覆された中継パッド
39の上面には導体層79が露呈し、中継パッド39と積層部
78との間の切断可能領域80には、カバー膜76形成のため
被着したカバー層の一部を取り残して形成したガイドラ
イン51(52)が形成されている。Relay pad whose side surface is covered with the cover film 76
The conductor layer 79 is exposed on the upper surface of the 39, and the relay pad 39 and the laminated portion are exposed.
A guide line 51 (52) formed by leaving a part of the cover layer deposited for forming the cover film 76 is formed in a severable region 80 between the guide film 51 and 78.

【００４９】図12(b) において、データ領域35はシリコ
ン酸化層71, 各種の所要薄膜72〜75を積層し、最上層に
はカバー膜76を被着してなり、データ領域35の外縁部に
は、データ領域35に沿ってウェーハを切断するためのガ
イド77を形成するための積層部78が、データ領域35のパ
ターン形成工程を利用し形成されている。In FIG. 12B, the data area 35 is formed by laminating a silicon oxide layer 71 and various required thin films 72 to 75, and covering the uppermost layer with a cover film 76. A laminated portion 78 for forming a guide 77 for cutting the wafer along the data area 35 is formed by using the pattern forming process of the data area 35.

【００５０】側面がカバー膜76に被覆された中継パッド
39の上面には導体層79が露呈し、中継パッド39と積層部
78との間の切断可能領域80には、カバー膜76形成のため
被着したカバー層の一部をエッチングし形成したガイド
ライン51(52)が形成されている。A relay pad whose side surface is covered with a cover film 76.
The conductor layer 79 is exposed on the upper surface of the 39, and the relay pad 39 and the laminated portion are exposed.
A guide line 51 (52) is formed in a severable region 80 between the guide line 78 and 78, which is formed by etching a part of the cover layer deposited to form the cover film 76.

【００５１】[0051]

【発明の効果】以上説明したように本発明によれば、半
導体ウェーハから所要チップを取り出す切断の自由度が
拡大し、従来のものより所望のサイズに近い大きさに切
り出すことができる。As described above, according to the present invention, the degree of freedom in cutting out a required chip from a semiconductor wafer is increased, and it is possible to cut out into a size closer to a desired size than the conventional one.

【００５２】従って、本発明によってパターン形成し切
断した一対の半導体チップを、ＳＣＰに組み込んだ半導
体装置は、パッド間およびパッドとリード端子との接続
用ワイヤによる従来の障害を皆無にする。Therefore, the semiconductor device in which the pair of semiconductor chips patterned and cut according to the present invention are incorporated in the SCP eliminates the conventional troubles due to the connecting wires between the pads and between the pads and the lead terminals.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の第１の実施例のウェーハの説明図FIG. 1 is an explanatory diagram of a wafer according to a first embodiment of the present invention.

【図２】 図１のパッド群形成領域の断面図FIG. 2 is a cross-sectional view of the pad group formation region of FIG.

【図３】 図１のウェーハから切り出したチップを封入
した半導体装置FIG. 3 is a semiconductor device in which a chip cut out from the wafer of FIG. 1 is enclosed.

【図４】 図１のウェーハの切断例の説明図FIG. 4 is an explanatory diagram of an example of cutting the wafer in FIG.

【図５】 ワイヤ接続方法の説明図FIG. 5 is an explanatory diagram of a wire connection method.

【図６】 本発明の第２の実施例のウェーハにおけるチ
ップ領域の説明図FIG. 6 is an explanatory diagram of a chip area on a wafer according to a second embodiment of the present invention.

【図７】 本発明の第３の実施例のウェーハにおけるチ
ップ領域の説明図FIG. 7 is an explanatory diagram of a chip area on a wafer according to a third embodiment of the present invention.

【図８】 本発明の第４の実施例のウェーハにおけるチ
ップ領域の説明図FIG. 8 is an explanatory diagram of a chip area on a wafer according to a fourth embodiment of the present invention.

【図９】 本発明の第５の実施例のウェーハにおけるチ
ップ領域の説明図FIG. 9 is an explanatory diagram of a chip area on a wafer according to a fifth embodiment of the present invention.

【図１０】 本発明の第６の実施例のウェーハにおける
チップ領域の説明図FIG. 10 is an explanatory diagram of a chip area on a wafer according to a sixth embodiment of the present invention.

【図１１】 本発明の実施例になる半導体装置の説明図FIG. 11 is an explanatory diagram of a semiconductor device according to an embodiment of the present invention.

【図１２】 ウェーハ切断用ガイドラインの形成例の説
明図FIG. 12 is an explanatory view of an example of forming a wafer cutting guideline.

【図１３】 ＳＣＰに組み込んだ半導体装置の構成例を
示す断面図FIG. 13 is a sectional view showing a configuration example of a semiconductor device incorporated in the SCP.

【図１４】 切り出しサイズ可変とした半導体チップの
従来例の模式説明図FIG. 14 is a schematic explanatory view of a conventional example of a semiconductor chip having a variable cutout size.

【図１５】 図１４の半導体チップにおける問題点の説
明図FIG. 15 is an explanatory diagram of problems in the semiconductor chip of FIG.

【符号の説明】[Explanation of symbols]

６ パッケージ（樹脂モールド） 22 リード端子 30 ウェーハ 32,33 チップ領域を区分する区画線 32-1, 32-2, 33-1, 33-2,51,52 チップ領域内切断用ガ
イドライン 34, 34-1, 34-2, 34-3, 34-4, 34-5 チップ領域 35 データ領域 36 データ領域内のワイヤボンディングパッド 38 中継パッド群 39, 39-1 中継パッド 40 酸化膜 41 カバー膜 42,44,61 半導体装置 43, 45,46,43-1, 43-2 ボンディングワイヤ 50-1, 50-2,62,63 半導体チップ6 Package (resin mold) 22 Lead terminal 30 wafers 32 and 33 partition lines 32 -1 for distinguishing chip area, 32 -2, 33 -1, 33 -2, 51, 52 chip region for cutting guidelines 34, 34 - 1 , 34 -2 , 34 -3 , 34 -4 , 34 -5 Chip area 35 Data area 36 Wire bonding pad in data area 38 Relay pad group 39, 39 -1 Relay pad 40 Oxide film 41 Cover film 42,44 , 61 Semiconductor device 43, 45,46,43 -1 , 43 -2 Bonding wire 50 -1 , 50 -2 , 62,63 Semiconductor chip

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/822 Ｈ０１Ｌ 27/04 Ａ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical display location H01L 21/822 H01L 27/04 A

Claims (19)

【特許請求の範囲】[Claims] 【請求項１】 区画線により区分された多数のチップ領
域には、所要回路および該回路の外部接続用ワイヤボン
ディングパッドが形成されたデータ領域を中心部に設
け、該ワイヤボンディングパッドに対向し外部接続用中
継パッドが整列する中継パッド群が該データ領域の外側
に形成されてなること、 を特徴とする半導体ウェーハ。1. A plurality of chip areas divided by partition lines are provided with a data area, in which a required circuit and a wire bonding pad for external connection of the circuit are formed, at a central portion, and the data area is opposed to the wire bonding pad. A semiconductor wafer, wherein a relay pad group in which the connection relay pads are aligned is formed outside the data area. 【請求項２】 請求項１記載の半導体ウェーハにおい
て、前記中継パッドがワイヤのダブルボンディング可能
な大きさであること、 を特徴とする半導体ウェーハ。2. The semiconductor wafer according to claim 1, wherein the relay pad has a size capable of double-bonding a wire. 【請求項３】 請求項１記載の半導体ウェーハにおい
て、前記データ領域の四方の前記中継パッド群形成領域
の表面が、絶縁性カバー膜または酸化膜または該カバー
膜と酸化膜の積層で覆われてなること、 を特徴とする半導体ウェーハ。3. The semiconductor wafer according to claim 1, wherein the surfaces of the relay pad group formation regions on four sides of the data region are covered with an insulating cover film, an oxide film, or a stack of the cover film and an oxide film. Being a semiconductor wafer. 【請求項４】 請求項１記載の半導体ウェーハにおい
て、前記データ領域の四方にはそれぞれ複数の前記中継
パッド群が該データ領域から離れる方向に並列に形成さ
れてなること、 を特徴とする半導体ウェーハ。4. The semiconductor wafer according to claim 1, wherein a plurality of relay pad groups are formed in parallel on each of four sides of the data region in a direction away from the data region. . 【請求項５】 請求項１記載の半導体ウェーハにおい
て、前記データ領域の上下方向および左右方向に形成し
た前記中継パッド群が、該データ領域に対し対称位置に
設けられたこと、 を特徴とする半導体ウェーハ。5. The semiconductor wafer according to claim 1, wherein the relay pad groups formed in the vertical and horizontal directions of the data area are provided at symmetrical positions with respect to the data area. Wafer. 【請求項６】 請求項１記載の半導体ウェーハにおい
て、前記データ領域の上下方向および左右方向に形成し
た前記中継パッド群が、該データ領域に対し非対称位置
に設けられたこと、 を特徴とする半導体ウェーハ。6. The semiconductor wafer according to claim 1, wherein the relay pad group formed in the vertical direction and the horizontal direction of the data area is provided in an asymmetrical position with respect to the data area. Wafer. 【請求項７】 請求項１記載の半導体ウェーハにおい
て、前記データ領域および前記中継パッド群が重複しな
い位置にウェーハ切断用ガイドラインが形成されてなる
こと、 を特徴とする半導体ウェーハ。7. The semiconductor wafer according to claim 1, wherein a guide line for wafer cutting is formed at a position where the data area and the relay pad group do not overlap each other. 【請求項８】 請求項７記載の半導体ウェーハにおい
て、前記ガイドラインが前記ウェーハに被着した保護層
のエッチングにより形成されてなること、 を特徴とする半導体ウェーハ。8. The semiconductor wafer according to claim 7, wherein the guideline is formed by etching a protective layer deposited on the wafer. 【請求項９】 請求項７記載の半導体ウェーハにおい
て、前記ガイドラインが前記ウェーハに被着した保護層
の取り残しによって形成されてなること、 を特徴とする半導体ウェーハ。9. The semiconductor wafer according to claim 7, wherein the guideline is formed by leaving a protective layer deposited on the wafer. 【請求項１０】 前記データ領域の外縁に沿って請求項
１記載の半導体ウェーハを切断すること、 を特徴とする半導体ウェーハの切断方法。10. The method for cutting a semiconductor wafer according to claim 1, wherein the semiconductor wafer according to claim 1 is cut along an outer edge of the data area. 【請求項１１】 前記データ領域と前記中継パッド群と
を含むように請求項１記載の半導体ウェーハを切断する
こと、 を特徴とする半導体ウェーハの切断方法。11. The method for cutting a semiconductor wafer according to claim 1, wherein the semiconductor wafer is cut so as to include the data area and the relay pad group. 【請求項１２】 前記ガイドラインに沿って請求項７記
載の半導体ウェーハを切断すること、 を特徴とする半導体ウェーハの切断方法。12. A method of cutting a semiconductor wafer, comprising cutting the semiconductor wafer according to claim 7 along the guideline. 【請求項１３】 前記データ領域の大きさが異なる一対
の請求項１記載の半導体ウェーハに対し、データ領域の
大きい一方のウェーハを請求項１０の方法で切断した第
１の半導体チップの寸法に合わせて、データ領域の小さ
い他方のウェーハを請求項１１または１２の方法で切断
すること、 を特徴とする半導体ウェーハの切断方法。13. A semiconductor wafer according to claim 1, wherein the data areas have different sizes, and one of the wafers having a larger data area is adjusted to the size of the first semiconductor chip cut by the method of claim 10. And then cutting the other wafer having a small data area by the method according to claim 11 or 12. 【請求項１４】 前記データ領域の大きさが異なる一対
の請求項１記載の半導体ウェーハに対し、データ領域の
大きい一方のウェーハを請求項１１の方法で切断した第
１の半導体チップの寸法に合わせて、データ領域の小さ
い他方のウェーハを請求項１２の方法で切断すること、 を特徴とする半導体ウェーハの切断方法。14. The semiconductor wafer according to claim 1, wherein the data areas have different sizes, and one of the wafers having a larger data area is adjusted to the size of the first semiconductor chip cut by the method of claim 11. And then cutting the other wafer having a smaller data area by the method of claim 12. 【請求項１５】 前記データ領域の大きさが異なる一対
の請求項１記載の半導体ウェーハに対し、切断寸法が揃
うように該一対の半導体ウェーハを請求項１１の方法で
切断すること、 を特徴とする半導体ウェーハの切断方法。15. The pair of semiconductor wafers according to claim 1, wherein the data areas have different sizes, and the pair of semiconductor wafers are cut by the method according to claim 11 so that the cutting dimensions are the same. Method for cutting semiconductor wafers. 【請求項１６】 前記データ領域の大きさが異なる一対
の請求項１記載の半導体ウェーハに対し、切断寸法が揃
うように該一対の半導体ウェーハを請求項１２の方法で
切断すること、 を特徴とする半導体ウェーハの切断方法。16. The pair of semiconductor wafers according to claim 1, wherein the data areas have different sizes, and the pair of semiconductor wafers are cut by the method according to claim 12 so that the cutting dimensions are aligned. Method for cutting semiconductor wafers. 【請求項１７】 前記データ領域の大きさが異なる一対
の請求項１記載の半導体ウェーハに対し、切断寸法が揃
うように該半導体ウェーハの一方を請求項１１の方法で
切断し他方を請求項１２の方法で切断すること、 を特徴とする半導体ウェーハの切断方法。17. A pair of semiconductor wafers according to claim 1, wherein the data areas have different sizes, and one of the semiconductor wafers is cut by the method according to claim 11 and the other is cut so that the cutting dimensions are aligned. A method for cutting a semiconductor wafer, which comprises: 【請求項１８】 請求項１１または１２記載の方法で半
導体ウェーハを切断し形成した半導体チップの前記ワイ
ヤボンディングパッドと前記中継用パッドおよび該中継
用パッドとリード端子とをワイヤで接続し、該半導体チ
ップおよび該ワイヤによる接続部を、パッケージに封入
したこと、 を特徴とする半導体装置。18. A semiconductor chip formed by cutting the semiconductor wafer by the method according to claim 11, wherein the wire bonding pad and the relay pad, and the relay pad and a lead terminal are connected by a wire, and the semiconductor A semiconductor device, characterized in that a chip and a connecting portion by the wire are enclosed in a package. 【請求項１９】 請求項１３または１４または１５また
は１６または１７記載の方法で半導体ウェーハを切断し
た一対の半導体チップを重ねてパッケージに封入したこ
と、 を特徴とする半導体装置。19. A semiconductor device comprising: a pair of semiconductor chips obtained by cutting a semiconductor wafer by the method according to claim 13 or 14 or 15 or 16 or 17 and superposing the semiconductor chips in a package.
JP6206988A 1994-08-31 1994-08-31 Semiconductor wafer, dicing method therefor and semiconductor device Withdrawn JPH0878467A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6206988A JPH0878467A (en) 1994-08-31 1994-08-31 Semiconductor wafer, dicing method therefor and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6206988A JPH0878467A (en) 1994-08-31 1994-08-31 Semiconductor wafer, dicing method therefor and semiconductor device

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JPH0878467A true JPH0878467A (en) 1996-03-22

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115977B2 (en) * 2000-09-28 2006-10-03 Oki Electric Industry Co., Ltd. Multi-chip package type semiconductor device
US7608925B2 (en) 2005-07-20 2009-10-27 Fujitsu Microelectronics Limited Relay board with bonding pads connected by wirings
WO2010119762A1 (en) * 2009-04-15 2010-10-21 オリンパスメディカルシステムズ株式会社 Semiconductor device and method for manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115977B2 (en) * 2000-09-28 2006-10-03 Oki Electric Industry Co., Ltd. Multi-chip package type semiconductor device
US8053278B2 (en) 2000-09-28 2011-11-08 Oki Semiconductor Co., Ltd. Multi-chip package type semiconductor device
US7608925B2 (en) 2005-07-20 2009-10-27 Fujitsu Microelectronics Limited Relay board with bonding pads connected by wirings
WO2010119762A1 (en) * 2009-04-15 2010-10-21 オリンパスメディカルシステムズ株式会社 Semiconductor device and method for manufacturing semiconductor device

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