JPH0868618A - System and method for manufacture of semiconductor device - Google Patents
System and method for manufacture of semiconductor deviceInfo
- Publication number
- JPH0868618A JPH0868618A JP7179793A JP17979395A JPH0868618A JP H0868618 A JPH0868618 A JP H0868618A JP 7179793 A JP7179793 A JP 7179793A JP 17979395 A JP17979395 A JP 17979395A JP H0868618 A JPH0868618 A JP H0868618A
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- Japan
- Prior art keywords
- defect
- semiconductor device
- substrate
- image
- image signal
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＬＳＩウェハを複数の
工程で処理することにより半導体装置を製造する半導体
装置の製造システム及び製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing system and method for manufacturing a semiconductor device by processing an LSI wafer in a plurality of steps.
【０００２】[0002]
【従来の技術】従来の半導体装置の製造システムにおい
ては、ＬＳＩウエハの回路パターンの異物、変色欠陥、
形状欠陥等の欠陥を外観から検出する外観欠陥検査装置
は、半導体の製造ラインから切り離されたいわゆるオフ
ラインで用いられていた。このようにして用いられてい
た外観検査装置としては、例えば、信学技報ＶＯＬ．8
7,No.132（1987）第３１頁から第３８頁に記載されたも
のが知られている。即ち図２３において、ランプ２で照
明したウェハ１上の回路パターンを対物レンズ３を介し
てイメージセンサ４で拡大検出し、回路パターンの濃淡
画像を得る。欠陥判定回路６において、検出した濃淡画
像を画像メモリ５に記憶してある一つ前のチップ７ａ
（隣接チップ）の画像と比較し、欠陥判定を行う。検出
した画像は、同時に画像メモリ５に格納し（記憶画
像）、次のチップ７ｂの比較検査に用いる。2. Description of the Related Art In a conventional semiconductor device manufacturing system, a foreign material on a circuit pattern of an LSI wafer, a discoloration defect,
An appearance defect inspection apparatus for detecting a defect such as a shape defect from the appearance has been used in a so-called off-line separated from a semiconductor manufacturing line. Examples of the appearance inspection device used in this manner include, for example, SIJ Technical Report VOL. 8
7, No. 132 (1987), pages 31 to 38 are known. That is, in FIG. 23, the circuit pattern on the wafer 1 illuminated by the lamp 2 is enlarged and detected by the image sensor 4 through the objective lens 3 to obtain a grayscale image of the circuit pattern. In the defect determination circuit 6, the detected grayscale image is stored in the image memory 5 and the previous chip 7a is stored.
Defect determination is performed by comparing with the image of (adjacent chip). The detected image is simultaneously stored in the image memory 5 (stored image) and used for the next comparative inspection of the chip 7b.
【０００３】図２４に欠陥判定の１例を示す。位置合せ
回路６ａにおいて、検出画像と記憶画像を位置合せを
し、差画像検出回路６ｂにより位置合せされた検出画像
と記憶画像の差画像を検出する。これを２値化回路６ｃ
により２値化することにより、欠陥を検出する。上記構
成により検出画像に存在する欠け８ｄが検出される。FIG. 24 shows an example of defect determination. The registration circuit 6a aligns the detected image with the stored image, and the difference image detection circuit 6b detects the difference image between the detected image and the stored image. This is a binarization circuit 6c
The defect is detected by binarizing with. With the above configuration, the defect 8d existing in the detected image is detected.
【０００４】また、この種の装置として関連するものに
例えばエス・ピー・アイ・イー，オプティカル マイク
ロリソグラフィＶＩ（1987年）第248頁から第255頁（Ｓ
ＰＩＥ Ｖｏｌ．772 Ｏptical Ｍicrolithography
ＶＩ（1987）ｐｐ248−255）等が挙げられる。Related to this type of apparatus, for example, SPII, Optical Microlithography VI (1987), pages 248 to 255 (S
PIE Vol. 772 Optical Microlithography
VI (1987) pp248-255) and the like.
【０００５】[0005]
【発明が解決しようとする課題】上記従来技術は、対応
するパターンの不一致を欠陥として検出するものであ
り、従って検出した欠陥を他の観察手段、例えば光学顕
微鏡やＳＥＭにより観察しなければ、形状欠陥、変色、
異物といった欠陥の種類を識別することができず、欠陥
の発生源となるウエハ処理装置を細かく管理することが
できないという課題があった。The above-mentioned prior art is to detect the mismatch of the corresponding patterns as a defect. Therefore, if the detected defect is not observed by other observation means such as an optical microscope or SEM, the shape of Defects, discoloration,
There is a problem that the type of defect such as a foreign substance cannot be identified and the wafer processing apparatus that is the source of the defect cannot be managed in detail.
【０００６】本発明の目的は、ＬＳＩウェハの製造工程
において、ウエハ上に発生する欠陥を致命的な欠陥と致
命的でない欠陥とに識別することにより、各処理装置の
状態を的確に把握することができる半導体装置の製造シ
ステム及び製造方法を提供することにある。An object of the present invention is to accurately grasp the state of each processing apparatus by discriminating defects occurring on the wafer into fatal defects and non-fatal defects in the LSI wafer manufacturing process. A semiconductor device manufacturing system and manufacturing method are provided.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明では、被処理基板を複数の工程で処理するこ
とにより半導体装置を製造する半導体装置の製造システ
ムにおいて、複数の工程の内の所定の工程の間に設けら
れて被処理基板上の欠陥の発生状態を検出する欠陥検出
手段と、この欠陥検出手段により得られる被処理基板上
の欠陥の情報に基づいて工程における欠陥の種類及び発
生位置を特定する欠陥判定手段とを備えるようにした。In order to achieve the above object, the present invention provides a semiconductor device manufacturing system for manufacturing a semiconductor device by processing a substrate to be processed in a plurality of steps. Defect detection means provided between the predetermined steps for detecting the occurrence state of defects on the substrate to be processed, and the type of defects in the steps based on the information on the defects on the substrate to be processed obtained by the defect detection means. And defect determining means for specifying the occurrence position.
【０００８】[0008]
【作用】ＬＳＩウェハの被検査パターンについて、異
物、変色欠陥、形状欠陥等の欠陥を検出し、このウエハ
を追跡して各処理装置毎に検査及び欠陥分類を行ない、
欠陥の座標（ウエハ上での欠陥の発生位置）をチェック
することにより欠陥が各処理装置を経てどのように発生
するかを調べ、また、欠陥を致命的なものと致命的でな
いものとに識別して欠陥の致命性を判定することにより
各処理装置の状態を的確に把握できる。With respect to the pattern to be inspected of the LSI wafer, defects such as foreign matter, discoloration defect, and shape defect are detected, and the wafer is traced to inspect and classify each processing device.
By checking the coordinates of the defect (the position where the defect occurs on the wafer), it is possible to check how the defect occurs through each processing device, and also to identify the defect as fatal and non-fatal. Then, the state of each processing apparatus can be accurately grasped by determining the fatality of the defect.
【０００９】[0009]
【実施例】以下、本発明による半導体製造システムに用
いる外観検査装置の一実施例を、図１を用いて説明す
る。Ｘｅランプ１２で照明したウェハ１上の回路パター
ンを対物レンズ３を介してＴＶカメラ１３で拡大検出す
る。ＴＶカメラの出力はＡ／Ｄ変換器１４によりディジ
タル信号に変換される。光電変換器としては、ＴＶカメ
ラ、リニアイメージセンサ等いかなるものでも使用可能
であるが、リニアイメージセンサの場合は、センサの自
己走査及びそれと直角方向に移動するｘｙテーブルによ
りウェハの２次元パターンを検出する。検出した濃淡画
像は、画像メモリ１５ａに記憶されている一つ前のチッ
プの画像と比較され、欠陥判定が行われる。即ち、図２
に示すように、ウェハ上のチップ７内部の位置７ｄの回
路パターンを検出し、これを画像メモリ１５ａに記憶し
た隣のチップの対応する位置７ｃの回路パターンと比較
することにより、欠陥を検出する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a visual inspection apparatus used in a semiconductor manufacturing system according to the present invention will be described below with reference to FIG. The circuit pattern on the wafer 1 illuminated by the Xe lamp 12 is enlarged and detected by the TV camera 13 via the objective lens 3. The output of the TV camera is converted into a digital signal by the A / D converter 14. As the photoelectric converter, any device such as a TV camera or a linear image sensor can be used. In the case of the linear image sensor, the two-dimensional pattern of the wafer is detected by the self-scanning of the sensor and the xy table moving in the direction perpendicular to the sensor. To do. The detected grayscale image is compared with the image of the previous chip stored in the image memory 15a, and defect determination is performed. That is, FIG.
As shown in FIG. 5, a defect is detected by detecting the circuit pattern of the position 7d inside the chip 7 on the wafer and comparing it with the circuit pattern of the corresponding position 7c of the adjacent chip stored in the image memory 15a. .
【００１０】まず、図１の位置合せ回路１６で、図３に
図示するような検出画像（ａ）、記憶画像（ｂ）を位置
合せし（図３（ｃ））、図１の差画像検出回路１７によ
り位置合せされた検出画像と記憶画像の差画像を検出す
る（図３の差画像（ｄ））。この差画像（ｄ）を図１の
２値化回路１８により２値化することにより、図３の２
値画像（ｅ）を得る。これにより、検出画像（ａ）に存
在するパターンの断線８ｂを欠陥として検出する。位置
７ｄの回路パターンを検出して得た画像は、新たに画像
メモリ１５ａに記憶され、次のチップの位置７ｅの検査
に用いられる。First, the alignment circuit 16 of FIG. 1 aligns the detected image (a) and the stored image (b) as shown in FIG. 3 (FIG. 3 (c)), and detects the difference image of FIG. The difference image between the detected image and the stored image aligned by the circuit 17 is detected (difference image (d) in FIG. 3). This difference image (d) is binarized by the binarization circuit 18 of FIG.
Obtain the value image (e). Thereby, the disconnection 8b of the pattern existing in the detected image (a) is detected as a defect. The image obtained by detecting the circuit pattern at the position 7d is newly stored in the image memory 15a and used for the inspection at the position 7e of the next chip.
【００１１】図２において、欠陥が７ｄの位置にある場
合、７ｃと７ｄの比較においても、７ｄと７ｅの比較に
おいても、欠陥が検出されるので、それぞれの２チップ
比較結果を照合すれば、どのチップに欠陥があったかを
特定することができる。図１のＣＰＵ３１により、この
照合が行われる。In FIG. 2, when the defect is at the position of 7d, the defect is detected both in the comparison between 7c and 7d and in the comparison between 7d and 7e. Therefore, by comparing the two-chip comparison results, It is possible to identify which chip has a defect. This collation is performed by the CPU 31 of FIG.
【００１２】２値化回路１８からの信号により、位置７
ｄに欠陥があると判定された場合、ウェハを上下に移動
するＺ制御回路１９によりウェハを移動し、各Ｚ位置で
欠陥部７ｄの画像を検出して、画像を画像メモリ１５ａ
に記憶する。ウェハのｘｙ方向の移動はｘｙ制御回路２
０により行い、欠陥部に対応する良品部例えば位置７ｃ
にウェハを移動し、欠陥部７ｄと同様に各Ｚ位置で良品
部の画像を検出して、画像を画像メモリ１５ｂに記憶す
る。位置合せ回路２１ａでは画像メモリ１５ａに記憶さ
れたＺ＝Ｚ1での欠陥部の画像と画像メモリ１５ｂに記
憶されたＺ＝Ｚ1での良品部の画像を位置合せする。差
画像検出回路２２ａでは、位置合せされた画像の差画像
を検出し、最大値検出回路２３ａにより差画像の欠陥部
の濃淡値が検出される。The signal from the binarization circuit 18 causes the position 7
If it is determined that there is a defect in d, the wafer is moved by the Z control circuit 19 that moves the wafer up and down, the image of the defective portion 7d is detected at each Z position, and the image is stored in the image memory 15a.
To memorize. The xy control circuit 2 moves the wafer in the xy directions.
0, and the non-defective part corresponding to the defective part, for example, position 7c
The wafer is moved to, the image of the non-defective part is detected at each Z position as in the defective portion 7d, and the image is stored in the image memory 15b. Aligning images of non-defective portion in the alignment circuit 21a Z = Z 1 stored in the image and the image memory 15b of the defect in the Z = Z 1 stored in the image memory 15a in. The difference image detection circuit 22a detects the difference image of the aligned images, and the maximum value detection circuit 23a detects the gray value of the defective portion of the difference image.
【００１３】図４に、この様子を示す。欠陥部の画像
（ａ）と良品部の画像（ｂ）は、位置合せされ、差画像
（ｃ）が得られる。最大値検出回路２３ａにより、差画
像（ｃ）における濃淡の最大値が検出される。欠陥８ｂ
は、良品部との濃淡差が大きいので、上記最大値検出回
路２３ａにより、欠陥８ｂの、良品部との濃淡差を検出
することができる。This state is shown in FIG. The image of the defective portion (a) and the image of the non-defective portion (b) are aligned, and a difference image (c) is obtained. The maximum value detection circuit 23a detects the maximum value of the light and shade in the difference image (c). Defect 8b
Has a large shade difference from the non-defective part, the maximum value detection circuit 23a can detect the shade difference of the defect 8b from the non-defective part.
【００１４】同様に、画像メモリ１５ａ，１５ｂに記憶
された各Ｚ2〜Ｚｎ位置での欠陥部と良品部の画像を位
置合せ回路２１ｂ…２１ｎで位置合せし、差画像検出回
路２２ｂ…２２ｎで差画像を検出し、最大値検出回路２
３ｂ…２３ｎで差画像の欠陥部の濃淡値が検出される。
画像メモリ１５ａ，１５ｂには、例えば１０２４×１０
２４画素の濃淡画像を、それぞれｎ枚分記憶する。Similarly, the images of the defective portion and the non-defective portion at the respective Z 2 to Zn positions stored in the image memories 15a and 15b are aligned by the alignment circuits 21b ... 21n, and the difference image detection circuits 22b ... 22n. Maximum value detection circuit 2 that detects the difference image
The gray value of the defective portion of the difference image is detected at 3b ... 23n.
The image memories 15a and 15b have, for example, 1024 × 10
The grayscale image of 24 pixels is stored for each n sheets.
【００１５】なお、画像メモリ１５ａは、上記多重焦点
画像記憶用以外に、通常の欠陥判定用に、濃淡画像１枚
分を記憶できる容量をもつ。これにより、後述する、欠
陥判定と欠陥分類を交互に行うシーケンスを実現するこ
とが可能になる。The image memory 15a has a capacity for storing one gray-scale image for ordinary defect determination, in addition to the above-described multi-focus image storage. This makes it possible to realize a sequence, which will be described later, for alternately performing defect determination and defect classification.
【００１６】また、Ｚ＝Ｚ0での欠陥部の画像と良品部
の画像を位置合せ回路２４で位置合せし、１次微分回路
２５ａでそれぞれの画像の１次微分をとり、これらの差
画像を差画像検出回路２６ａでとった後最大値検出回路
２７ａで差画像の欠陥部の濃淡値を検出する。同様に、
２次微分回路２５ｂで欠陥部の画像と良品部の画像の２
次微分をとり、差画像検出回路２６ｂでこれらの差画像
を検出、最大値検出回路２７ｂで差画像の濃淡値を検出
する。Further, the image of the defective portion and the image of the non-defective portion at Z = Z 0 are aligned by the aligning circuit 24, the primary differential circuit 25a takes the primary differential of each image, and the difference image between them is obtained. After being taken by the difference image detecting circuit 26a, the maximum value detecting circuit 27a detects the gray value of the defective portion of the difference image. Similarly,
The image of the defective portion and the image of the non-defective portion are 2
Next differential is taken, the difference image detection circuit 26b detects these difference images, and the maximum value detection circuit 27b detects the grayscale value of the difference image.
【００１７】これらの検出値を全て欠陥分類回路３０に
入力する。欠陥分類回路３０では、図１５及び図１７に
基づいて図５に示すように欠陥の種類の判別を行う。こ
れらはソフトウェアにより実現される。All of these detected values are input to the defect classification circuit 30. The defect classification circuit 30 determines the defect type as shown in FIG. 5 based on FIGS. 15 and 17. These are realized by software.
【００１８】次に、上記外観検査装置の動作を説明す
る。Next, the operation of the appearance inspection apparatus will be described.
【００１９】対物レンズ３は、そのＮＡが例えば０．８
〜０．９５といった大きな値をもつものとし、解像度は
高く、焦点深度は浅いものを選ぶ。欠陥が検出される
と、この焦点深度の浅い対物レンズを利用して、ウェハ
を上下に例えば０．２μｍきざみで移動させ、ある平面
内にだけ焦点の合った画像を検出する。±０．６μｍの
範囲で画像を検出すると、７組の画像が検出される。The objective lens 3 has an NA of 0.8, for example.
It is assumed to have a large value such as .about.0.95, the resolution is high, and the depth of focus is shallow. When a defect is detected, the wafer having a shallow depth of focus is used to move the wafer up and down in steps of, for example, 0.2 μm, and an image focused only in a certain plane is detected. When an image is detected within a range of ± 0.6 μm, 7 sets of images are detected.
【００２０】欠陥部と良品部の画像の位置合せは、位置
合せ回路１６，２１ａ〜２１ｎ，２４で行われるが、こ
れは例えば信学技報ＶｏＬ、87，Ｎｏ．132（1987）第
３１頁から第３８頁に記載されている方法で実現でき
る。位置合せされた７組の画像の差画像を検出した後、
その濃淡値を検出すると、欠陥が異物の場合は図１６に
示すように合焦面Ｚ0より上側のＺ1，Ｚ2でも比較的大
きな濃淡値をもち、従って欠陥分類回路３０において例
えば図５に示すフローに従って、容易に異物かどうかの
判定ができる。The alignment of the images of the defective portion and the non-defective portion is performed by the alignment circuits 16, 21a to 21n, 24. This is described in, for example, Technical Report VoL, 87, No. 132 (1987) page 31 to page 38. After detecting the difference image of the aligned 7 sets of images,
When the density value is detected, if the defect is a foreign matter, Z 1 and Z 2 above the focusing surface Z 0 also have relatively large density values as shown in FIG. It is possible to easily determine whether or not it is a foreign matter according to the flow shown in FIG.
【００２１】画像の微分は、微分回路２５で行われる
が、例えば２次微分は図６に示すように、４種のエッジ
オペレータ〔１ −２ １〕を画像に施し、それらの最
大値を検出することにより実現できる。The differentiation of the image is carried out by the differentiating circuit 25. For example, for the second order differentiation, as shown in FIG. 6, four kinds of edge operators [1-21] are applied to the image and their maximum values are detected. It can be realized by doing.
【００２２】図７に、２次微分回路２５ｂの具体構成を
示す。図７（ａ）において、位置合せ回路２４からの、
例えば８ｂｉｔのディジタル画像信号を３段のシフトレ
ジスタ２５０で受け、初段及び第３段の出力は加算器２
５１に、第２段の出力はゲイン２の増幅器２５２にそれ
ぞれ供給される。加算器２５１の出力及び増幅器２５２
の出力は、減算器２５３に加えられる。シフトレジスタ
２５０、加算器２５１、増幅器２５２及び減算器２５３
で、“１，−２，１”なるオペレータが構成されてい
る。FIG. 7 shows a specific configuration of the second-order differentiating circuit 25b. In FIG. 7A, from the alignment circuit 24,
For example, an 8-bit digital image signal is received by the shift register 250 of three stages, and the outputs of the first stage and the third stage are the adder 2
51, the output of the second stage is supplied to the gain 252 amplifier 252, respectively. Output of adder 251 and amplifier 252
The output of is added to the subtractor 253. Shift register 250, adder 251, amplifier 252 and subtractor 253
, An operator "1, -2, 1" is configured.
【００２３】図７（ｂ）は、縦、横、斜めの８方向で微
分するための回路で、位置合せ回路２４の出力を３×３
切出し回路２５４に加え、縦、横、斜めの３画素を選択
して４つのオペレータＯＰ１〜ＯＰ４に加え、画像信号
を微分する。各オペレータは、図７（ａ）に図示したも
のと同一でよい。４つのオペレータ出力は、最大値検出
回路２５５に加えられ、これらのうちから最大値が検出
される。FIG. 7B is a circuit for differentiating in eight directions of vertical, horizontal, and diagonal, and the output of the alignment circuit 24 is 3 × 3.
In addition to the cutout circuit 254, vertical, horizontal, and diagonal three pixels are selected and added to the four operators OP1 to OP4 to differentiate the image signal. Each operator may be the same as that shown in FIG. The four operator outputs are applied to the maximum value detection circuit 255, and the maximum value is detected from among these.
【００２４】微分した後、差画像を検出すると、その濃
淡値は図１７に示すような波形となり、欠陥が変色の場
合は濃淡値が小さくなるので、欠陥分類回路３０により
図５に示すフローに従って容易に変色かどうかの判定が
できる。When the difference image is detected after differentiation, the grayscale value has a waveform as shown in FIG. 17, and the grayscale value becomes small when the defect is discolored. Therefore, the defect classification circuit 30 follows the flow shown in FIG. It is possible to easily determine whether the color changes.
【００２５】図１８に、処理のフローを示す。横軸は時
間を示している。同図において画像検出、欠陥判定を繰
返し行い、検査が行われる。画像検出は、図１に示すＴ
Ｖカメラ１３，Ａ／Ｄ変換器１４、画像メモリ１５ａに
より行い、欠陥判定は、位置合せ回路１６、差画像検出
回路１７、２値化回路１８、及び欠陥位置の特定を行う
ＣＰＵ３１により行われる。欠陥が検出された場合、上
記検査を中断し、欠陥部及び対応する良品部の多重焦点
画像を検出する。この画像検出はＴＶカメラ、Ａ／Ｄ変
換器１４、画像メモリ１５ａ，１５ｂを用いて行われ
る。次に、これらの画像の差画像、最大値検出を行う。
これらは、位置合せ回路２１ａ，…，２１ｎ，２４、差
画像検出回路２２ａ，…，２２ｎ，２６ａ，２６ｂ、微
分回路２５ａ，２５ｂ、最大値検出回路２３ａ，…，２
３ｎ，２７ａ，２７ｂにより実現される。各Ｚ位置での
最大値及び微分画像の差画像の最大値がすべて検出され
ると、欠陥分類が行われ、欠陥分類回路３０により異
物、変色、形状欠陥に分類される。そして、再び画像検
出、欠陥判定か、欠陥が検出されるまで繰返し行われ
る。FIG. 18 shows a processing flow. The horizontal axis represents time. In the figure, the image detection and the defect determination are repeated to perform the inspection. Image detection is performed by the T shown in FIG.
The V camera 13, the A / D converter 14, and the image memory 15a perform the defect determination, and the defect determination is performed by the alignment circuit 16, the difference image detection circuit 17, the binarization circuit 18, and the CPU 31 that identifies the defect position. When a defect is detected, the inspection is interrupted and a multi-focus image of the defective part and the corresponding non-defective part is detected. This image detection is performed using the TV camera, the A / D converter 14, and the image memories 15a and 15b. Next, the difference image of these images and maximum value detection are performed.
, 21n, 24, difference image detecting circuits 22a, ..., 22n, 26a, 26b, differentiating circuits 25a, 25b, maximum value detecting circuits 23a ,.
It is realized by 3n, 27a and 27b. When the maximum value at each Z position and the maximum value of the differential image of the differential image are all detected, the defect classification is performed, and the defect classification circuit 30 classifies the foreign matter, the discoloration, and the shape defect. Then, image detection and defect determination are performed again, or the process is repeated until a defect is detected.
【００２６】このようにウェハ上の被検査対象パターン
上に存在する欠陥を図２２に示す。即ち、検出対象欠陥
は、回路パターンのふくれ８ａ、断線８ｂ、ショート８
ｃ、欠け８ｄなどの形状欠陥８、変色欠陥９及び異物１
０である。The defects existing on the pattern to be inspected on the wafer in this way are shown in FIG. That is, the defects to be detected are the swell 8a of the circuit pattern, the disconnection 8b, and the short 8
c, shape defect 8 such as chip 8d, discoloration defect 9 and foreign matter 1
0.
【００２７】本実施例において用いる外観検査装置で
は、欠陥を検出しては分類するという検査シーケンスを
説明したが、図１９に示すように例えば１枚のウェハに
ついて欠陥を全て検出して、欠陥の位置座標をＣＰＵ３
１にすべて記憶しておき、これに基づいて検査後順次欠
陥を呼び出して欠陥分類を行っても良い。In the appearance inspection apparatus used in this embodiment, the inspection sequence in which defects are detected and classified has been described. However, as shown in FIG. 19, for example, all defects of one wafer are detected and the defects are detected. CPU3 for position coordinates
All may be stored in No. 1 and defects may be sequentially called after the inspection based on this to perform defect classification.
【００２８】また、欠陥検出と欠陥分類を図２１に示す
ように別の光学系で行い、欠陥検出は低倍で高速に、欠
陥分類は高倍で正確に行うことも可能である。また、照
明はいかなる構成のものであっても適用可能である。It is also possible to perform defect detection and defect classification by another optical system as shown in FIG. 21, and to perform defect detection at low speed and high speed, and defect classification at high speed and accurately. Further, the illumination can be applied to any structure.
【００２９】図８に、本発明による半導体製造システム
に用いる外観検査装置における多重焦点画像検出の別の
実施例を示す。Ｚ制御回路１９によりウェハ１を上下移
動する代わりに、複数のＴＶカメラ１３ａ，１３ｂ…を
用意し、これを少しずつ光路上離して設置することによ
り、合焦面がＺ3，…，Ｚ-3…の複数の画像を同時に得
ることも可能である。FIG. 8 shows another embodiment of multi-focus image detection in the visual inspection apparatus used in the semiconductor manufacturing system according to the present invention. The wafer 1 by the Z control circuit 19 instead of up and down movement, a plurality of TV cameras 13a, 13b ... was prepared, by placing this apart optical path gradually focusing plane Z 3, ..., Z - It is also possible to obtain multiple images of 3 ... at the same time.
【００３０】図９に、上記した図８の多重焦点画像検出
の別の実施例を用いた外観検査装置の全体構成を示す。
同図において、合焦点の画像は、カメラ１３ａによって
得られ、Ａ／Ｄ変換器１４ａを経た後、欠陥判定に用い
るべく、画像メモリ１５ａ、及び位置合せ回路１６に入
力される。欠陥分類時は、カメラ１３ａ〜１３ｎによっ
て得られる全ての画像が、画像メモリ１５ａ，１５ｂに
同時に入力される。従って、画像メモリは、ｎ枚の画像
を同時にｗｒｉｔｅ可能であるものとする。ただし、ｒ
ｅａｄは画像を１枚ずつ読み出せれば良い。FIG. 9 shows the entire structure of an appearance inspection apparatus using another embodiment of the multi-focus image detection shown in FIG.
In the figure, an in-focus image is obtained by the camera 13a, passed through the A / D converter 14a, and then input to the image memory 15a and the alignment circuit 16 for use in defect determination. At the time of defect classification, all the images obtained by the cameras 13a to 13n are simultaneously input to the image memories 15a and 15b. Therefore, the image memory can write n images at the same time. Where r
The ead may read the images one by one.
【００３１】変色については別の構成により判別するこ
ともでき、図１では変色を判別するため画像を微分した
が、画像認識論（コロナ社）１７頁、１８頁に記載され
ているように、画像をフーリエ変換し、これにフィルタ
をかけた後逆フーリエ変換することにより、回路パター
ンのエッジを強調することもできる。これを用いて、欠
陥部と良品部の差画像を検出し、濃淡値の大小により変
色欠陥を判別することが可能である。Discoloration can be discriminated by another structure. In FIG. 1, the image is differentiated in order to discriminate the discoloration. However, as described on pages 17 and 18 of Image Recognition Theory (Corona Corp.) It is also possible to emphasize the edge of the circuit pattern by performing a Fourier transform on the signal, applying a filter to this, and then performing an inverse Fourier transform. By using this, it is possible to detect the difference image between the defective portion and the non-defective portion, and discriminate the discolored defect based on the magnitude of the gray value.
【００３２】また、光学的手段により変色欠陥を判別す
ることも可能である。図１０において、暗視野照明系と
してランプ３２、コンデンサレンズ３３、暗視野照明用
波長選定のための狭帯域フィルタ３４（波長λ1）、リ
ング状開口スリット３５、リング状ミラー３６、放物凹
面鏡３７、また明視野照明系としてランプ３８、コンデ
ンサレンズ３９、波長選定フィルタ４０（波長λ2）、
円形開口スリット４１、ハーフミラー４２、対物レンズ
４３、波長分離ミラー４４、及び暗視野検出用ＴＶカメ
ラ４５、明視野像検出用ＴＶカメラ４６により構成され
た画像検出系において、暗視野照明はフィルタ３４によ
り波長λ1に限定され、放物凹面鏡３７によりパターン
上に周囲斜め方向から照明される。明視野照明はフィル
タ４０により波長λ2に限定され、上方から照明され
る。欠陥部の暗視野画像と良品部の暗視野画像を検出
し、これを図１１に図示する位置合せ回路２４ａで位置
合せし、差画像検出回路２６ａで差画像を検出する。It is also possible to discriminate the discoloration defect by optical means. In FIG. 10, a lamp 32 as a dark field illumination system, a condenser lens 33, a narrow band filter 34 (wavelength λ 1 ) for selecting a wavelength for dark field illumination, a ring opening slit 35, a ring mirror 36, a parabolic concave mirror 37. , A lamp 38 as a bright field illumination system, a condenser lens 39, a wavelength selection filter 40 (wavelength λ 2 ),
In the image detection system including the circular aperture slit 41, the half mirror 42, the objective lens 43, the wavelength separation mirror 44, the dark field detection TV camera 45, and the bright field image detection TV camera 46, the dark field illumination is the filter 34. Is limited to the wavelength λ 1 and the parabolic concave mirror 37 illuminates the pattern obliquely from the periphery. The bright field illumination is limited to the wavelength λ 2 by the filter 40 and is illuminated from above. The dark field image of the defective portion and the dark field image of the non-defective portion are detected, the alignment circuit 24a shown in FIG. 11 aligns them, and the difference image detection circuit 26a detects the difference image.
【００３３】同様に、欠陥部の明視野画像と良品部の明
視野画像を検出し、これを位置合せ回路２４ｂで位置合
せし、差画像検出回路２６ｂで差画像を検出する。最大
値検出回路２７ａ，２７ｂでこれらの差画像の濃淡値を
検出すると、図１２に示すように、欠陥が変色の場合は
形状欠陥、異物に比べ、暗視野照明時の濃淡値が小さく
なり、欠陥分類回路３０において容易に変色が判別でき
る。なお、同図において、位置合せ回路１６、差画像検
出回路１７、２値化回路１８は通常の欠陥判定用のもの
である。Similarly, the bright field image of the defective portion and the bright field image of the non-defective portion are detected, the positions are aligned by the alignment circuit 24b, and the difference image is detected by the difference image detection circuit 26b. When the maximum-value detection circuits 27a and 27b detect the grayscale values of these difference images, as shown in FIG. 12, when the defect is discolored, the grayscale value at the time of dark-field illumination becomes smaller than that of the shape defect and the foreign matter. Discoloration can be easily identified in the defect classification circuit 30. In the figure, the alignment circuit 16, the difference image detection circuit 17, and the binarization circuit 18 are for normal defect determination.
【００３４】また、別の実施例として、上記暗視野画像
の検出の代りに図１３に示す構成要素を用いてもよい。As another embodiment, the components shown in FIG. 13 may be used instead of the detection of the dark field image.
【００３５】図１３において、Ｓ偏光レーザ４７ａ，４
７ｂにより、Ｓ偏光レーザ光をウェハ１上に角度ψで照
射する。ψは約１度である。ここで照射レーザ光とウェ
ハ法線のなす面に、垂直に振動する偏光をＳ偏光、平行
に振動する偏光をＰ偏光と呼ぶ。このとき、ウェハ上の
回路パターンのうち低段差のものは、その散乱光は偏光
方向が変化せず、実線で示すＳ偏光のまま対物レンズ４
８のほうに進むが、異物或いは高段差の回路パターンに
当ったレーザ光は偏光方向が変化するため、点線で示す
Ｐ偏光成分を多く含んでいる。そこで、対物レンズ４８
の後方にＳ偏光を遮断する偏光板４９を設け、これを通
過した光を光電素子５０で検出することにより、異物及
び高段差の回路パターンエッジからの散乱光を検出す
る。この散乱光信号をＡ／Ｄ変換回路１４によりディジ
タル信号に変換する。検出した信号を、画像メモリ１５
ａに記憶されている一つ前のチップの信号と比較する。
即ち、位置合せ回路２４ａでこれらの信号を位置合せ
し、差信号検出回路２６ａで差信号を検出する。高段差
の回路パターンエッジからの散乱光信号は２つの信号に
共通に含まれるので、差信号には異物からの散乱光信号
だけが含まれる。この差信号を２値化回路２７ａにより
２値化することにより異物が検出でき、欠陥分類を行う
ことができる。In FIG. 13, S-polarized lasers 47a, 4
7b, the S-polarized laser light is irradiated onto the wafer 1 at an angle ψ. ψ is about 1 degree. Here, polarized light that vibrates perpendicularly to the plane formed by the irradiation laser beam and the wafer normal is called S-polarized light, and polarized light that vibrates in parallel is called P-polarized light. At this time, in the circuit pattern on the wafer having a low step, the polarization direction of the scattered light does not change, and the objective lens 4 remains as S-polarized light shown by the solid line.
8, the laser light impinging on a foreign substance or a circuit pattern with a high step changes the polarization direction, and thus contains a large amount of P-polarized light component indicated by the dotted line. Therefore, the objective lens 48
A polarizing plate 49 that blocks S-polarized light is provided in the rear of, and the light passing through the polarizing plate 49 is detected by the photoelectric device 50 to detect the scattered light from the foreign matter and the circuit pattern edge of the high step. This scattered light signal is converted into a digital signal by the A / D conversion circuit 14. The detected signal is transferred to the image memory 15
Compare with the signal of the previous chip stored in a.
That is, the alignment circuit 24a aligns these signals, and the difference signal detection circuit 26a detects the difference signal. Since the scattered light signal from the circuit pattern edge with a high step is included in the two signals in common, the difference signal includes only the scattered light signal from the foreign matter. By binarizing this difference signal by the binarizing circuit 27a, foreign matter can be detected and defect classification can be performed.
【００３６】次に、上記した本発明による外観検査装置
を用いた半導体装置の製造システムについて、図１４を
用いて説明する。Next, a semiconductor device manufacturing system using the above-described appearance inspection apparatus according to the present invention will be described with reference to FIG.
【００３７】ウェハ上の回路パターンは複数の装置Ａ，
Ｂ，…Ｅにより順次形成される。本構成をもつ外観検査
装置により、ウェハを追跡し、各装置毎に検査及び欠陥
分類を行う。欠陥の座標をチェックすることにより、欠
陥が各装置を経てどのように発生するかが調べられる。
例えば、装置Ｂによる処理を経たウェハを検査し、検出
した欠陥は、前装置Ａからの持込み欠陥と装置Ｂ内で発
生した欠陥からなり、装置Ａによる処理を経た時に検査
して得た欠陥データと照合すれば、装置Ｂ内で発生した
欠陥か前装置からの持込み欠陥かどうかがわかる。ここ
で、前装置Ａからの持込み欠陥のうち、異物については
装置Ｂで形状欠陥或いは変色を引き起こさないものもあ
り、致命的な異物の付着したパターンは必ず次以降の装
置で形状欠陥或いは変色となるが、致命的でない異物の
付着したパターンは以降の装置を経ても形状欠陥等にな
らず、良品である。従って、本構成をもつ外観検査装置
により異物と分類された欠陥について、その座標を記憶
しておき、そのウェハが次の装置を経た後に、再度欠陥
検出、分類を行うことにより、異物の致命性を判定する
ことが可能になる。これにより、製造装置の状態をより
的確に把握することが可能になる。The circuit pattern on the wafer is composed of a plurality of devices A,
B, ... E are sequentially formed. The wafer is traced by the appearance inspection device having this configuration, and inspection and defect classification are performed for each device. By checking the coordinates of the defect, it is possible to see how the defect occurs through each device.
For example, the defect detected by inspecting the wafer processed by the device B is composed of a carry-in defect from the previous device A and a defect generated in the device B, and the defect data obtained by the inspection when the process by the device A is performed. By comparing with, it is possible to know whether it is a defect occurring in the device B or a defect brought in from the previous device. Here, among the defects brought in from the previous device A, some foreign substances do not cause a shape defect or discoloration in the device B, and a pattern in which a fatal foreign substance is attached always causes a shape defect or discoloration in the next and subsequent devices. However, the pattern in which the non-fatal foreign matter is attached does not cause a shape defect or the like even after passing through the subsequent device, and is a good product. Therefore, the coordinates of the defects classified as foreign matter by the appearance inspection apparatus having this configuration are stored, and the defect is detected and classified again after the wafer has passed through the next apparatus. Can be determined. This makes it possible to more accurately grasp the state of the manufacturing apparatus.
【００３８】図２０に、上記した本発明による半導体製
造システムにおいて、外観検査装置により異物の致命性
判定を行う構成を示す。同図において、欠陥判定部４０
により欠陥を検出し、その座標を欠陥属性記憶部４２に
より記憶する。検出した欠陥部について、欠陥分類部４
１により欠陥を異物とそれ以外の種類に分類し、欠陥属
性記憶部４２にその座標と対で記憶する。次に、次工程
を経た上記と同一ウェハを検査し、同様に欠陥判定、欠
陥分類を行い、欠陥座標、種類を欠陥属性記憶部４２に
記憶する。前工程で異物と判定された欠陥について、致
命性判定部４３において、その座標を調べ、次工程で形
状欠陥、変色と分類された欠陥を致命性と判定する。FIG. 20 shows the structure of the above-described semiconductor manufacturing system according to the present invention, in which the lethality of foreign matter is judged by the appearance inspection apparatus. In the figure, the defect determination unit 40
The defect is detected by, and the coordinates thereof are stored in the defect attribute storage unit 42. Defect classification section 4 for the detected defect section
Defects are classified into foreign matter and other types by 1 and stored in the defect attribute storage unit 42 as a pair with their coordinates. Next, the same wafer as the above which has undergone the next step is inspected, defect determination and defect classification are performed in the same manner, and the defect coordinates and type are stored in the defect attribute storage unit 42. The coordinates of the defects determined to be foreign matter in the previous process are examined by the fatality determination unit 43, and defects classified as shape defects and discoloration in the next process are determined to be fatal.
【００３９】以上、本発明の半導体製造システムに用い
る外観検査装置のいくつかの実施例を説明したが、対象
とするウェハの画像を検出し、位置合せすることによ
り、欠陥判定、欠陥分類を行っている。従って、ウェハ
上の回路パターン密度が小さい場所では、位置合せする
２枚の画像の隅に一方でパターンが入り、他方に入らな
いケースが生じ、画像の位置合せが正確にできない場合
がある。そこで、パターンのないエリアについて、ダミ
ーパターンを作り込み、検出した画像に必ずパターンが
入るようにして位置合せできるようにする。ダミーパタ
ーンはいかなる形状であってもよい。このようにして、
ウェハを検査、欠陥分類することにより、プロセス・設
備の歩留り管理に大きく寄与することができる。Although some embodiments of the appearance inspection apparatus used in the semiconductor manufacturing system of the present invention have been described above, defect determination and defect classification are performed by detecting and aligning an image of a target wafer. ing. Therefore, in a place where the circuit pattern density on the wafer is low, there may be a case where a pattern enters one of the corners of the two images to be aligned and the other does not enter, and the images may not be accurately aligned. Therefore, a dummy pattern is created in an area having no pattern so that the detected image always includes the pattern so that the position can be adjusted. The dummy pattern may have any shape. In this way,
By inspecting wafers and classifying defects, it is possible to greatly contribute to yield management of processes and equipment.
【００４０】上記実施例ではウェハについて説明した
が、ＴＦＴや薄膜磁気ヘッド等の半導体製品等について
も適用可能である。In the above embodiment, the wafer is explained, but it can be applied to semiconductor products such as TFT and thin film magnetic head.
【００４１】[0041]
【発明の効果】以上説明したように、本発明によれば外
観検査装置において検出した欠陥を自動で分類し、検出
した異物の致命性を判定できるので、プロセス・設備の
歩留り管理に大きく寄与することができ、ＬＳＩの生産
を高い歩留りで安定に維持することが可能になる。As described above, according to the present invention, the defects detected by the appearance inspection apparatus can be automatically classified and the lethality of the detected foreign matter can be judged, which greatly contributes to the yield management of the process / equipment. Therefore, it becomes possible to stably maintain the LSI production with a high yield.
【００４２】[0042]
【図１】本発明による半導体製造システムに用いる被検
査対象パターンの欠陥検出装置の一実施例を示す全体構
成図。FIG. 1 is an overall configuration diagram showing an embodiment of a defect detection apparatus for a pattern to be inspected used in a semiconductor manufacturing system according to the present invention.
【図２】図１に示す装置において隣接するウェハ上のチ
ップ内部の位置の回路パターンを比較する状態を示す
図。FIG. 2 is a diagram showing a state in which circuit patterns at positions inside chips on adjacent wafers are compared in the apparatus shown in FIG.
【図３】図１に示す装置において得られる検出画像、記
憶画像、位置合せ画像、差画像及び２値画像を示す図。FIG. 3 is a diagram showing a detected image, a stored image, an alignment image, a difference image, and a binary image obtained by the device shown in FIG.
【図４】図１に示す装置においてＺ＝Ｚ1での欠陥部の
画像、良品部の画像、これら位置合せされた差画像及び
該差画像の濃淡波形を示す図。FIG. 4 is a diagram showing an image of a defective portion at Z = Z 1 in the apparatus shown in FIG. 1, an image of a non-defective portion, a difference image aligned with these, and a grayscale waveform of the difference image.
【図５】図１に示す欠陥分類回路により欠陥の種類の判
別を行うフローを示す図。5 is a diagram showing a flow for determining the type of defect by the defect classification circuit shown in FIG.
【図６】図１に示す微分回路によって行なわれる画像微
分を示す図。FIG. 6 is a diagram showing image differentiation performed by the differentiating circuit shown in FIG. 1.
【図７】図１に示す２次微分回路の具体的構成を示す
図。7 is a diagram showing a specific configuration of the secondary differentiating circuit shown in FIG.
【図８】図１とは異なる多重焦点画像検出の一実施例を
示す図。FIG. 8 is a diagram showing an embodiment of multi-focus image detection different from FIG.
【図９】図８に示す多重焦点画像検出を適用した本発明
による半導体製造システムに用いる被検査対象パターン
の欠陥検出装置の全体構成を示す図。9 is a diagram showing an overall configuration of a defect detection apparatus for a pattern to be inspected used in a semiconductor manufacturing system according to the present invention to which the multi-focus image detection shown in FIG. 8 is applied.
【図１０】図１と異なり、光学的手段により変色欠陥を
判別する一実施例を示す図。FIG. 10 is a diagram showing an embodiment for discriminating a discoloration defect by optical means, which is different from FIG.
【図１１】図１０に示す一実施例を適用した全体構成を
示す図。FIG. 11 is a diagram showing an overall configuration to which the embodiment shown in FIG. 10 is applied.
【図１２】各種欠陥における明視野照明及び暗視野照明
と差画像の濃淡値との関係を示した図。FIG. 12 is a diagram showing the relationship between bright-field illumination and dark-field illumination and the grayscale value of the difference image for various defects.
【図１３】図１０に示す暗視野画像検出とは異なる他の
一実施例を示した概略構成図。13 is a schematic configuration diagram showing another embodiment different from the dark field image detection shown in FIG.
【図１４】本発明による半導体製造システムを示す図。FIG. 14 is a diagram showing a semiconductor manufacturing system according to the present invention.
【図１５】被検査対象パターンに対する合焦点位置関係
を示した図。FIG. 15 is a diagram showing the in-focus position relationship with respect to the pattern to be inspected.
【図１６】各種欠陥における合焦点面のＺ位置と差画像
の濃淡値との関係を示す図。FIG. 16 is a diagram showing the relationship between the Z position of the in-focus plane and the grayscale value of the difference image for various defects.
【図１７】各種欠陥における微分の次数と差画像の濃淡
値との関係を示す図。FIG. 17 is a diagram showing the relationship between the order of differentiation and the grayscale value of the difference image for various defects.
【図１８】図１に示す装置における処理の一実施例を示
すフロー図。FIG. 18 is a flowchart showing one embodiment of processing in the apparatus shown in FIG.
【図１９】図１８と異なる処理の一実施例を示すフロー
図。FIG. 19 is a flowchart showing one embodiment of processing different from FIG.
【図２０】外観検査装置を用いて異物の致命性判定を行
う装置の具体的構成を示す図。FIG. 20 is a diagram showing a specific configuration of an apparatus for determining the lethality of a foreign substance using an appearance inspection apparatus.
【図２１】欠陥検出と欠陥分類とを別の光学系で行う一
実施例を示した概略構成図。FIG. 21 is a schematic configuration diagram showing an example in which defect detection and defect classification are performed by different optical systems.
【図２２】被検査対象パターンに存在する各種の欠陥を
示した図。FIG. 22 is a view showing various defects existing in the pattern to be inspected.
【図２３】従来技術の被検査対象パターンの欠陥検出装
置の一例を示した図。FIG. 23 is a diagram showing an example of a conventional defect detection apparatus for a pattern to be inspected.
【図２４】従来技術の被検査対象パターンの欠陥検出装
置の他の一例を示した図。FIG. 24 is a diagram showing another example of a conventional defect detection apparatus for a pattern to be inspected.
１…ウェハ、 １３…ＴＶカメラ、 １５…画像メモリ、 １６，２１，２４…位置合せ回路、 １７，２２，２６…差画像検出回路、 ２３，２７…最大値検出回路、 ２５…微分回路、 ３０…欠陥分類回路。 1 ... Wafer, 13 ... TV camera, 15 ... Image memory, 16, 21, 24 ... Alignment circuit, 17, 22, 26 ... Difference image detection circuit, 23, 27 ... Maximum value detection circuit, 25 ... Differentiation circuit, 30 … Defect classification circuit.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｇ０６Ｔ 1/00 Ｈ０１Ｌ 21/66 Ｊ 7514−4Ｍ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical display location G06T 1/00 H01L 21/66 J 7514-4M
Claims (16)
より半導体装置を製造する半導体装置の製造システムに
おいて、前記複数の工程の内の所定の工程の間に設けら
れて前記被処理基板上の欠陥の発生状態を検出する欠陥
検出手段と、該欠陥検出手段により得られる前記被処理
基板上の欠陥の情報に基づいて前記工程における前記欠
陥の種類及び発生位置を特定する欠陥判定手段とを備え
たことを特徴とする半導体装置の製造システム。1. A semiconductor device manufacturing system for manufacturing a semiconductor device by processing a substrate to be processed in a plurality of steps, wherein the substrate is provided between predetermined steps of the plurality of steps. Defect detecting means for detecting the occurrence state of the defect, and defect determining means for specifying the type and occurrence position of the defect in the process based on the information of the defect on the substrate to be processed obtained by the defect detecting means. A semiconductor device manufacturing system, comprising:
点画像信号に基づいて検出することを特徴とする請求項
１記載の半導体装置の製造システム。2. The semiconductor device manufacturing system according to claim 1, wherein the defect is detected based on a multi-focus image signal of the surface of the substrate to be inspected.
画像信号と暗視野画像信号とに基づいて検出することを
特徴とする請求項１記載の半導体装置の製造システム。3. The semiconductor device manufacturing system according to claim 1, wherein the defect is detected based on a bright field image signal and a dark field image signal of the surface of the substrate to be inspected.
欠陥のうち何れか少なくとも一つを含むことを特徴とす
る請求項２乃至３の何れかに記載の半導体装置の製造シ
ステム。4. The semiconductor device manufacturing system according to claim 2, wherein the defects include at least one of a foreign substance defect, a discoloration defect, and a shape defect.
パターン信号とを比較して得られる差画像信号に基づい
て異物欠陥を検出する異物欠陥検出部と、前記画像信号
の微分信号と前記基準パターン信号の微分信号とを比較
して得られる差画像信号に基づいて変色欠陥を検出する
変色欠陥検出部と、前記被検査対象パターン上の欠陥の
うち前記異物欠陥及び前記変色欠陥に相当しない欠陥を
形状欠陥として検出する形状欠陥検出部とを備えたこと
を特徴とする請求項４に記載の半導体装置の製造システ
ム。5. The foreign matter defect detecting section for detecting a foreign matter defect based on a difference image signal obtained by comparing the image signal with the reference pattern signal, a differential signal of the image signal and the inspection means. A discoloration defect detection unit that detects a discoloration defect based on a difference image signal obtained by comparing a differential signal of a reference pattern signal, and does not correspond to the foreign matter defect and the discoloration defect among defects on the pattern to be inspected. 5. The semiconductor device manufacturing system according to claim 4, further comprising a shape defect detection unit that detects a defect as a shape defect.
より半導体装置を製造する半導体装置の製造システムに
おいて、前記被処理基板を処理する前記複数の工程のう
ちの所定の工程の前後で前記被処理基板上の欠陥を検出
する検出手段と、該検出手段からの出力信号に基づいて
前記欠陥の発生状態を比較して前記欠陥の発生工程を特
定する判定手段とを備えたことを特徴とする半導体装置
の製造システム。6. In a semiconductor device manufacturing system for manufacturing a semiconductor device by processing a substrate to be processed in a plurality of steps, before and after a predetermined step among the plurality of steps to process the substrate to be processed. A detection means for detecting a defect on the substrate to be processed; and a determination means for comparing the generation state of the defect on the basis of an output signal from the detection means to identify the defect generation step. Semiconductor device manufacturing system.
基板表面の多重焦点画像信号に基づいて検出することを
特徴とする請求項６記載の半導体装置の製造システム。7. The semiconductor device manufacturing system according to claim 6, wherein said detection means detects said defect based on a multi-focus image signal of the surface of said substrate to be inspected.
基板表面の明視野画像信号と暗視野画像信号とに基づい
て検出することを特徴とする請求項６記載の半導体装置
の製造システム。8. The system for manufacturing a semiconductor device according to claim 6, wherein the detecting means detects the defect based on a bright field image signal and a dark field image signal of the surface of the substrate to be inspected. .
欠陥のうち何れか少なくとも一つであることを特徴とす
る請求項６乃至８記載の半導体装置の製造システム。9. The semiconductor device manufacturing system according to claim 6, wherein the defect is at least one of a foreign substance defect, a discoloration defect, and a shape defect.
により半導体装置を製造する半導体装置の製造方法にお
いて、前記複数の工程の内の所定の工程の間に設けられ
て前記被処理基板上の欠陥の発生状態を検出する欠陥検
出工程を備え、前記欠陥検出工程により得られる前記被
処理基板上の欠陥の発生状態を監視することにより、前
記欠陥が前記複数の工程を経てどのように発生するかを
調べながら前記半導体装置を製造することを特徴とする
半導体装置の欠陥検査方法。10. A semiconductor device manufacturing method for manufacturing a semiconductor device by processing a substrate to be processed in a plurality of steps, which is provided between predetermined steps of the plurality of steps and is provided on the substrate to be processed. The defect generation step of detecting the defect generation state, and by monitoring the defect generation state on the substrate to be processed obtained by the defect detection step, how the defect occurs through the plurality of steps. A method for inspecting a defect of a semiconductor device, which comprises manufacturing the semiconductor device while checking whether or not to perform the defect inspection.
焦点画像信号に基づいて検出することを特徴とする請求
項１０記載の半導体装置の欠陥検査方法。11. The defect inspection method for a semiconductor device according to claim 10, wherein the defect is detected based on a multi-focus image signal of the surface of the substrate to be inspected.
野画像信号と暗視野画像信号とに基づいて検出すること
を特徴とする請求項１０記載の半導体装置の欠陥検査方
法。12. The defect inspection method for a semiconductor device according to claim 10, wherein the defect is detected based on a bright field image signal and a dark field image signal of the surface of the substrate to be inspected.
状欠陥のうち何れか少なくとも一つを含むことを特徴と
する請求項１０記載の半導体装置の欠陥検査方法。13. The defect inspection method for a semiconductor device according to claim 10, wherein the defects include at least one of a foreign substance defect, a discoloration defect, and a shape defect.
により半導体装置を製造する半導体装置の製造方法にお
いて、前記被処理基板を処理する前記複数の工程のうち
の所定の工程の前後で前記被処理基板上の異物欠陥、変
色欠陥又は形状欠陥のうち何れか少なくとも一つを検査
して、前記異物欠陥、変色欠陥又は形状欠陥の発生状態
を比較することにより、前記異物欠陥、変色欠陥又は形
状欠陥の発生工程を特定することを特徴とする半導体装
置の欠陥検査方法。14. A semiconductor device manufacturing method for manufacturing a semiconductor device by processing a substrate to be processed in a plurality of steps, wherein before and after a predetermined step among the plurality of steps of processing the substrate to be processed. By inspecting at least one of a foreign matter defect, a discoloration defect or a shape defect on the substrate to be processed, and comparing the occurrence states of the foreign matter defect, the discoloration defect or the shape defect, the foreign matter defect, the discoloration defect or A method for inspecting a defect of a semiconductor device, characterized in that a step of generating a shape defect is specified.
を、前記被検査基板表面の多重焦点画像信号に基づいて
検出することを特徴とする請求項１４記載の半導体装置
の欠陥検査方法。15. The defect inspection method for a semiconductor device according to claim 14, wherein said foreign matter defect, discoloration defect or shape defect is detected based on a multi-focus image signal of the surface of said substrate to be inspected.
を、前記被検査基板表面の明視野画像信号と暗視野画像
信号とに基づいて検出することを特徴とする請求項１４
記載の半導体装置の欠陥検査方法。16. The foreign matter defect, the discoloration defect or the shape defect is detected based on a bright field image signal and a dark field image signal of the surface of the substrate to be inspected.
A defect inspection method for a semiconductor device as described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7179793A JP2822937B2 (en) | 1995-07-17 | 1995-07-17 | Semiconductor device manufacturing system and defect inspection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7179793A JP2822937B2 (en) | 1995-07-17 | 1995-07-17 | Semiconductor device manufacturing system and defect inspection method |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63323276A Division JPH02170279A (en) | 1988-12-23 | 1988-12-23 | Method and device for detecting defect of pattern to be checked |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10007222A Division JP3047881B2 (en) | 1998-01-19 | 1998-01-19 | Semiconductor device manufacturing system and semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0868618A true JPH0868618A (en) | 1996-03-12 |
| JP2822937B2 JP2822937B2 (en) | 1998-11-11 |
Family
ID=16071999
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7179793A Expired - Lifetime JP2822937B2 (en) | 1995-07-17 | 1995-07-17 | Semiconductor device manufacturing system and defect inspection method |
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| Country | Link |
|---|---|
| JP (1) | JP2822937B2 (en) |
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| US5995219A (en) * | 1997-03-05 | 1999-11-30 | Kabushiki Kaisha Toshiba | Pattern defect inspection apparatus |
| JP2004101214A (en) * | 2002-09-05 | 2004-04-02 | Dainippon Screen Mfg Co Ltd | Pattern inspection apparatus, yield management system, pattern inspection method, substrate manufacturing method, and program |
| JP2004260193A (en) * | 2004-03-10 | 2004-09-16 | Hitachi Ltd | Method and apparatus for testing circuit pattern |
| JP2005098970A (en) * | 2003-08-25 | 2005-04-14 | Hitachi Kokusai Electric Inc | Method and apparatus for identifying foreign matter |
| JP2007078466A (en) * | 2005-09-13 | 2007-03-29 | Tokyo Seimitsu Co Ltd | Visual inspection device and method therefor |
| JP2007183283A (en) * | 2007-01-24 | 2007-07-19 | Renesas Technology Corp | Foreign matter inspection method and device |
| JP2019015742A (en) * | 2007-08-31 | 2019-01-31 | ケーエルエー−テンカー・コーポレーションＫｌａ−Ｔｅｎｃｏｒ Ｃｏｒｐｏｒａｔｉｏｎ | Systems for simultaneously inspecting specimen with two distinct channels |
| JP2020514721A (en) * | 2017-01-10 | 2020-05-21 | ケーエルエー コーポレイション | System and method for training and applying defect classifiers in wafers with deeply stacked layers |
| CN114092476A (en) * | 2022-01-19 | 2022-02-25 | 阿里云计算有限公司 | Impurity detection method, system, device, equipment, storage medium and software product |
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| JP2001004347A (en) | 1999-06-22 | 2001-01-12 | Mitsubishi Electric Corp | Defect inspecting device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5995219A (en) * | 1997-03-05 | 1999-11-30 | Kabushiki Kaisha Toshiba | Pattern defect inspection apparatus |
| JP2004101214A (en) * | 2002-09-05 | 2004-04-02 | Dainippon Screen Mfg Co Ltd | Pattern inspection apparatus, yield management system, pattern inspection method, substrate manufacturing method, and program |
| JP2005098970A (en) * | 2003-08-25 | 2005-04-14 | Hitachi Kokusai Electric Inc | Method and apparatus for identifying foreign matter |
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| JP2007078466A (en) * | 2005-09-13 | 2007-03-29 | Tokyo Seimitsu Co Ltd | Visual inspection device and method therefor |
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| JP2007183283A (en) * | 2007-01-24 | 2007-07-19 | Renesas Technology Corp | Foreign matter inspection method and device |
| JP2019015742A (en) * | 2007-08-31 | 2019-01-31 | ケーエルエー−テンカー・コーポレーションＫｌａ−Ｔｅｎｃｏｒ Ｃｏｒｐｏｒａｔｉｏｎ | Systems for simultaneously inspecting specimen with two distinct channels |
| JP2020514721A (en) * | 2017-01-10 | 2020-05-21 | ケーエルエー コーポレイション | System and method for training and applying defect classifiers in wafers with deeply stacked layers |
| CN114092476A (en) * | 2022-01-19 | 2022-02-25 | 阿里云计算有限公司 | Impurity detection method, system, device, equipment, storage medium and software product |
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| Publication number | Publication date |
|---|---|
| JP2822937B2 (en) | 1998-11-11 |
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