JPH0864913A - Semiconductor light emitting element and its manufacture - Google Patents
Semiconductor light emitting element and its manufactureInfo
- Publication number
- JPH0864913A JPH0864913A JP20248094A JP20248094A JPH0864913A JP H0864913 A JPH0864913 A JP H0864913A JP 20248094 A JP20248094 A JP 20248094A JP 20248094 A JP20248094 A JP 20248094A JP H0864913 A JPH0864913 A JP H0864913A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- light emitting
- semiconductor light
- insulating film
- emitting device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体発光素子およびそ
の製法に関する。さらに詳しくは、青色発光に好適なチ
ッ化ガリウム系化合物半導体を用いた半導体発光素子お
よびその製法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device and its manufacturing method. More specifically, it relates to a semiconductor light emitting device using a gallium nitride based compound semiconductor suitable for blue light emission and a method for manufacturing the same.
【０００２】ここにチッ化ガリウム系化合物半導体と
は、III 族元素のＧａとＶ族元素のＮとの化合物または
III 族元素のＧａの一部がＡｌ、Ｉｎなど他のIII 族元
素と置換したものおよび／またはＶ族元素のＮの一部が
Ｐ、Ａｓなど他のＶ族元素と置換した化合物からなる半
導体をいう。Here, a gallium nitride compound semiconductor is a compound of a group III element Ga and a group V element N or
A semiconductor made of a compound in which a part of Ga of the group III element is replaced with another group III element such as Al and In and / or a part of N of the group V element is replaced with another group V element such as P and As. Say.
【０００３】また、半導体発光素子とは、ｐｎ接合また
はｐｉｎなどダブルヘテロ接合を有する発光ダイオード
（以下、ＬＥＤという）、スーパルミネッセントダイオ
ード（ＳＬＤ）または半導体レーザダイオード（ＬＤ）
などの光を発生する半導体素子をいう。A semiconductor light emitting device is a light emitting diode (hereinafter referred to as LED) having a double heterojunction such as a pn junction or a pin, a super luminescent diode (SLD) or a semiconductor laser diode (LD).
A semiconductor element that emits light.
【０００４】[0004]
【従来の技術】従来青色のＬＥＤは赤色や緑色に比べて
輝度が小さく実用化に難点があったが、近年チッ化ガリ
ウム系化合物半導体を用い、Ｍｇをドーパントした低抵
抗のｐ型半導体層がえられたことにより、輝度が向上し
脚光をあびている。2. Description of the Related Art Conventionally, blue LEDs have a lower brightness than red and green and are difficult to put into practical use. In recent years, however, gallium nitride compound semiconductors have been used, and a low resistance p-type semiconductor layer doped with Mg has been formed. As a result, the brightness is improved and it is in the limelight.
【０００５】従来のチッ化ガリウム系のＬＥＤは、たと
えば図４に示されるような構造になっている。このＬＥ
Ｄを製造するには、まずサファイア（Ａｌ2 Ｏ3 単結
晶）基板２１に４００〜７００℃の低温で有機金属化合
物気相成長法（以下、ＭＯＣＶＤ法という）によりキャ
リアガスＨ2 とともに有機金属化合物ガスであるトリメ
チルガリウム（以下、ＴＭＧという）およびアンモニア
（ＮＨ3 ）を供給し、ＧａＮからなる低温バッファ層２
２を０．０１〜０．２μｍ程度形成し、ついで７００〜
１２００℃の高温で同じガスを供給し同じ組成のｎ型の
ＧａＮからなる高温バッファ層２３を２〜５μｍ程度形
成する。A conventional gallium nitride based LED has a structure as shown in FIG. 4, for example. This LE
In order to manufacture D, first, a sapphire (Al 2 O 3 single crystal) substrate 21 is formed at a low temperature of 400 to 700 ° C. by a metal organic compound vapor phase growth method (hereinafter referred to as MOCVD method) together with a carrier gas H 2 and an organic metal compound. A low temperature buffer layer 2 made of GaN by supplying trimethylgallium (hereinafter referred to as TMG) and ammonia (NH 3 ) which are gases
2 is formed in the range of 0.01 to 0.2 μm, and then 700 to
The same gas is supplied at a high temperature of 1200 ° C. to form the high temperature buffer layer 23 made of n-type GaN having the same composition in a thickness of about 2 to 5 μm.
【０００６】ついで前述のガスにさらにトリメチルアル
ミニウム（以下、ＴＭＡという）のガスを供給してｎ型
のＡｌx Ｇａ1-x Ｎ（０＜ｘ＜１）からなるｎ型クラッ
ド層２４を０．１〜０．３μｍ程度形成し、ダブルヘテ
ロ接合形成のためのｎ型クラッド層を形成する。これら
のｎ型層を形成するには、チッ化ガリウム系化合物半導
体のばあい、ｎ型不純物をドープしなくてもｎ型になる
という性質を利用することもできるし、ＳｉＨ4 などの
原料ガスを同時に導入することもできる。Then, a gas of trimethylaluminum (hereinafter referred to as TMA) is further supplied to the above-mentioned gas to form an n-type clad layer 24 of n-type Al x Ga 1 -x N (0 <x <1). The thickness is about 1 to 0.3 μm, and an n-type clad layer for forming a double heterojunction is formed. To form these n-type layers, in the case of gallium nitride-based compound semiconductors, the property of becoming n-type without doping with n-type impurities can be used, or a source gas such as SiH 4 can be used. Can be introduced at the same time.
【０００７】つぎに、クラッド層の組成よりＡｌの量を
減らしＩｎの量を多くしてバンドギャップエネルギーが
クラッド層のそれより小さくなる材料、たとえばＧａy
Ｉｎ1-y Ｎ（０＜ｙ≦１）からなる活性層２５を形成す
る。Next, a material having a bandgap energy smaller than that of the cladding layer, for example, Ga y , is produced by reducing the Al content and increasing the In content relative to the composition of the cladding layer.
An active layer 25 made of In 1-y N (0 <y ≦ 1) is formed.
【０００８】ついで、ｎ型クラッド層の形成と同じ原料
ガスにさらにｐ型不純物としてのＭｇまたはＺｎのため
のビスシクロペンタジエニルマグネシウム（以下、Ｃｐ
2 Ｍｇという）またはジメチル亜鉛（以下、ＤＭＺｎと
いう）の有機金属化合物ガスを加えて反応管に導入し、
ｐ型Ａｌx Ｇａ1-x Ｎからなるｐ型クラッド層２６を形
成する。Then, biscyclopentadienyl magnesium (hereinafter, Cp) for Mg or Zn as a p-type impurity is added to the same source gas as that for forming the n-type clad layer.
2 Mg) or dimethylzinc (hereinafter referred to as DMZn) organometallic compound gas is added and introduced into the reaction tube,
A p - type clad layer 26 made of p - type Al x Ga 1-x N is formed.
【０００９】さらにキャップ層２７とするため、前述と
同様のガスを供給してｐ型のＧａＮ層を気相成長させ
る。Further, in order to form the cap layer 27, the same gas as described above is supplied to vapor-deposit the p-type GaN layer.
【００１０】そののち、ＳｉＯ2 などの保護膜を半導体
の成長層表面全面に設け、４００〜８００℃、２０〜６
０分間程度のアニールを行い、ｐ型層であるキャップ層
２７およびｐ型クラッド層２６の活性化を図る。ついで
保護膜を除去したのちｎ型の電極を形成するため、レジ
ストを塗布しパターニングして、図４に示されるよう
に、成長した各半導体層の一部を塩素ガス雰囲気でのド
ライエッチングを行ってｎ型ＧａＮからなる高温バッフ
ァ層２３を露出させる。ついでＡｕ、Ａｌなどの金属膜
をスパッタリングなどにより形成して両電極２８、２９
を形成し、ダイシングすることによりＬＥＤチップを形
成している。After that, a protective film such as SiO 2 is provided on the entire surface of the semiconductor growth layer, and the temperature is 400 to 800 ° C. and 20 to 6 ° C.
Annealing is performed for about 0 minutes to activate the p-type cap layer 27 and the p-type cladding layer 26. Then, after removing the protective film, in order to form an n-type electrode, a resist is applied and patterned, and as shown in FIG. 4, a part of each grown semiconductor layer is dry-etched in a chlorine gas atmosphere. To expose the high temperature buffer layer 23 made of n-type GaN. Then, a metal film of Au, Al or the like is formed by sputtering or the like to form both electrodes 28, 29.
Then, the LED chip is formed by dicing.
【００１１】[0011]
【発明が解決しようとする課題】従来のチッ化ガリウム
系化合物半導体を用いた半導体発光素子はサファイア基
板を用いるものである。サファイア基板は高温に耐える
ことができ、比較的種々の結晶面に合わせることができ
るため有利に用いられているが、サファイア基板とチッ
化ガリウム系化合物半導体結晶との格子定数はそれぞれ
４．７５８Åと３．１８９Åで相当異なり、さらに熱膨
脹係数も異なるため、図５のＡに示されるように、サフ
ァイア基板と接するバッファ層に転位や結晶欠陥が発生
し、その結晶欠陥が動作層であるチッ化ガリウム系化合
物半導体単結晶層にも進展し動作領域が狭くなるととも
に、半導体層の光学的品質も低下するという問題があ
る。A conventional semiconductor light emitting device using a gallium nitride based compound semiconductor uses a sapphire substrate. The sapphire substrate can withstand high temperatures and can be adjusted to relatively various crystal planes, so it is advantageously used. However, the lattice constants of the sapphire substrate and the gallium nitride-based compound semiconductor crystal are 4.758Å, respectively. 3.189Å, and the coefficient of thermal expansion is also different. Therefore, as shown in A of FIG. 5, dislocations and crystal defects occur in the buffer layer in contact with the sapphire substrate, and the crystal defects are gallium nitride nitride which is the operation layer. There is a problem in that the compound compound semiconductor single crystal layer also develops and the operating region becomes narrow, and the optical quality of the semiconductor layer also deteriorates.
【００１２】さらに、サファイア基板を劈開することは
できず、前述の構造では劈開により半導体発光素子チッ
プを製造することができないため、半導体レーザのよう
に端面が精度のよい平行な２つの鏡面を必要とするデバ
イスには不向きであるという問題がある。また、サファ
イア基板の加工性にも問題があり、デバイス作製上の基
板の取扱いが困難である。Further, since the sapphire substrate cannot be cleaved, and the semiconductor light emitting device chip cannot be manufactured by the cleaving in the above-described structure, it is necessary to have two mirror surfaces whose end faces are highly accurate and parallel to each other like a semiconductor laser. There is a problem that the device is not suitable for. Further, there is a problem in the workability of the sapphire substrate, and it is difficult to handle the substrate when manufacturing a device.
【００１３】本発明はこのような問題を解決し、格子定
数の不整合や熱膨張係数の相違に基づく結晶欠陥や転位
の発生が極力抑えられた半導体発光素子およびその製法
を提供することを目的とする。It is an object of the present invention to solve such problems and to provide a semiconductor light emitting device in which the occurrence of crystal defects and dislocations due to the mismatch of lattice constants and the difference in thermal expansion coefficient is suppressed as much as possible, and a manufacturing method thereof. And
【００１４】本発明のさらに他の目的は半導体発光素子
ごとに、劈開によって容易にチップを分離できるなど加
工が容易に行える層構造を有する半導体発光素子および
その製法を提供することを目的とする。Yet another object of the present invention is to provide a semiconductor light emitting device having a layer structure for each semiconductor light emitting device, which can be easily processed by cleaving chips, and a method for manufacturing the same.
【００１５】[0015]
【課題を解決するための手段】本発明の半導体発光素子
は、単結晶シリコン基板、該単結晶シリコン基板上に形
成された絶縁膜および該絶縁膜上に積層されたチッ化ガ
リウム系化合物半導体層を構成要素とする。A semiconductor light emitting device of the present invention comprises a single crystal silicon substrate, an insulating film formed on the single crystal silicon substrate, and a gallium nitride-based compound semiconductor layer laminated on the insulating film. Is a component.
【００１６】前記単結晶シリコン基板が（１１１）面を
主面とした基板であることにより、チッ化ガリウム系化
合物半導体層と界面での格子整合性がよい絶縁膜がえら
れるため好ましい。It is preferable that the single crystal silicon substrate is a substrate having a (111) plane as a main surface because an insulating film having a good lattice matching at the interface with the gallium nitride based compound semiconductor layer can be obtained.
【００１７】前記絶縁膜がチッ化シリコンであるか酸化
アルミニウムであることが半導体発光素子が、膜質のよ
いチッ化ガリウム系化合物半導体層から構成されるもの
となるために好ましい。It is preferable that the insulating film is made of silicon nitride or aluminum oxide because the semiconductor light emitting device is composed of a gallium nitride compound semiconductor layer having good film quality.
【００１８】前記チッ化ガリウム系化合物半導体層が、
ｐ型層およびｎ型層を含む複数の層であり、かつ、発光
のための活性層を有することにより、発光素子を実現す
るための構造として好ましい。The gallium nitride based compound semiconductor layer is
Having a plurality of layers including a p-type layer and an n-type layer and having an active layer for light emission is preferable as a structure for realizing a light emitting element.
【００１９】前記チッ化ガリウム系化合物半導体層が、
バッファ層、下部クラッド層、活性層、上部クラッド
層、キャップ層からなることが、発光素子を実現するた
めの構造として好ましい。The gallium nitride based compound semiconductor layer is
It is preferable that the structure includes a buffer layer, a lower clad layer, an active layer, an upper clad layer, and a cap layer for realizing a light emitting device.
【００２０】前記バッファ層がｎ型ＧａＮ、前記下部ク
ラッド層がｎ型Ａｌx Ｇａ1-x Ｎ（０＜ｘ＜１）、前記
活性層がＧａy Ｉｎ1-y Ｎ（０＜ｙ≦１）、前記上部ク
ラッド層がｐ型Ａｌx Ｇａ1-x Ｎ（０＜ｘ＜１）、前記
キャップ層がｐ型ＧａＮであると、ダブルヘテロ構造を
有する発光素子を実現するために好ましい。The buffer layer is n-type GaN, the lower cladding layer is n-type Al x Ga 1-x N (0 <x <1), and the active layer is Ga y In 1-y N (0 <y ≦ 1). ), The upper clad layer is p-type Al x Ga 1-x N (0 <x <1), and the cap layer is p-type GaN, which is preferable for realizing a light emitting device having a double hetero structure.
【００２１】本発明の半導体発光素子の製法は、単結晶
シリコン基板上に絶縁膜を形成する工程、前記絶縁膜上
にチッ化ガリウム系化合物半導体層を成膜してバッファ
層とする工程、前記バッファ層上にチッ化ガリウム系化
合物半導体からなる下部クラッド層、活性層、上部クラ
ッド層およびキャップ層を順次積層する工程、前記単結
晶シリコン基板に垂直にエッチングして、前記バッファ
層を露出させる工程、前記キャップ層および前記エッチ
ングにより露出したバッファ層上に電極を形成する工
程、およびダイシングまたは劈開によって素子ごとのチ
ップを分離する工程、を有する。The method of manufacturing a semiconductor light emitting device of the present invention comprises the steps of forming an insulating film on a single crystal silicon substrate, forming a gallium nitride based compound semiconductor layer on the insulating film to form a buffer layer, A step of sequentially stacking a lower clad layer, an active layer, an upper clad layer and a cap layer made of a gallium nitride based compound semiconductor on the buffer layer, and a step of vertically etching the single crystal silicon substrate to expose the buffer layer A step of forming an electrode on the buffer layer exposed by the cap layer and the etching, and a step of separating a chip for each element by dicing or cleavage.
【００２２】前記単結晶シリコン基板が（１１１）面を
主面とする基板であることが、チッ化ガリウム系化合物
半導体とより近い格子定数を有する絶縁膜を形成する上
で好ましい。It is preferable that the single crystal silicon substrate is a substrate having a (111) plane as a main surface in order to form an insulating film having a lattice constant closer to that of a gallium nitride based compound semiconductor.
【００２３】前記絶縁膜を形成する工程が、前記単結晶
シリコン基板の表面酸化膜を除去したのち、チッ素雰囲
気中で熱処理する工程であると、形成されるチッ化シリ
コン膜が、チッ化ガリウム系化合物半導体と共通の原子
を有して整合が行われやすくなるため好ましい。If the step of forming the insulating film is a step of removing the surface oxide film of the single crystal silicon substrate and then performing a heat treatment in a nitrogen atmosphere, the formed silicon nitride film is gallium nitride nitride. It is preferable that the atoms have a common atom with the system compound semiconductor, which facilitates matching.
【００２４】前記絶縁膜を形成する工程が、酸化アルミ
ニウムを成膜する工程であると、それに続いてチッ化ガ
ウリム系半導体層を成膜するときの膜質の特性に変化を
つけ易くなり、半導体発光素子の設計が容易になるため
好ましい。If the step of forming the insulating film is the step of forming aluminum oxide, it becomes easy to change the characteristics of the film quality when the gauride nitride semiconductor layer is subsequently formed, and semiconductor light emission is achieved. It is preferable because the device can be easily designed.
【００２５】[0025]
【作用】本発明によれば、単結晶シリコン基板上にチッ
化シリコンや酸化アルミニウムなどの絶縁膜を堆積させ
たのち、チッ化ガリウム系化合物半導体層からなるバッ
ファ層を介してその上に動作層のチッ化ガリウム系化合
物半導体単結晶層を成長しているため、格子定数や熱膨
張係数は非常に近くなり、格子欠陥や転位は発生しにく
い。According to the present invention, after an insulating film such as silicon nitride or aluminum oxide is deposited on a single crystal silicon substrate, an operating layer is formed on the insulating film via a buffer layer made of a gallium nitride based compound semiconductor layer. Since the gallium nitride-based compound semiconductor single crystal layer is grown, the lattice constant and the thermal expansion coefficient are very close to each other, and lattice defects and dislocations are less likely to occur.
【００２６】ここで、半導体単結晶基板上に堆積させた
絶縁膜とチッ化ガリウム系化合物半導体層とのあいだの
格子不整合に基因して発生した結晶欠陥が、動作層とす
るチッ化ガリウム系化合物半導体単結晶層へ広がって転
位や欠陥とならないように、バッファ層が設けられてい
るが、このバッファ層は、低温バッファ層および高温バ
ッファ層の二重構造となっていてより効率よく格子の不
整合を吸収するものとされてもよい。Here, a crystal defect generated due to a lattice mismatch between the insulating film deposited on the semiconductor single crystal substrate and the gallium nitride based compound semiconductor layer is a gallium nitride based compound serving as an operating layer. A buffer layer is provided so that it does not spread to the compound semiconductor single crystal layer to form dislocations or defects. This buffer layer has a double structure of a low temperature buffer layer and a high temperature buffer layer, so that the lattice can be efficiently formed. The mismatch may be absorbed.
【００２７】さらに、バッファ層とクラッド層の１μｍ
以上に厚く形成される層の半導体単結晶層の組成を同じ
にすることにより、きれいな劈開面がえられ、鏡面もえ
られるものとなる。Further, the buffer layer and the clad layer have a thickness of 1 μm.
By making the composition of the semiconductor single crystal layer of the layer formed thicker as above, a clean cleavage surface and a mirror surface can be obtained.
【００２８】[0028]
【実施例】つぎに図面を参照しながら本発明の半導体発
光素子を製法に従って説明する。図１〜２は本発明の製
法の一実施例により製造された半導体レーザチップの工
程断面説明図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor light emitting device of the present invention will be described according to a manufacturing method with reference to the drawings. 1 to 2 are process cross-sectional explanatory views of a semiconductor laser chip manufactured by an embodiment of the manufacturing method of the present invention.
【００２９】図１〜２を参照しながら本発明の製法の一
実施例である半導体レーザを製法に従って説明する。A semiconductor laser which is an embodiment of the manufacturing method of the present invention will be described according to the manufacturing method with reference to FIGS.
【００３０】まず主面が（１１１）面である単結晶シリ
コン基板１を用意して表面酸化膜を除去し、図１（ａ）
に示されるように、チッ素雰囲気中で５００〜９００℃
で熱処理を行って表面シリコンをチッ化し１〜５ｎｍ程
度の、たとえばＳｉ3 Ｎ4 からなる絶縁膜２を形成す
る。これに続いて図１（ｂ）のように従来技術で説明し
たのと同様に、有機金属ガスおよび不純物ガスを導入し
てＭＯＣＶＤ法による成膜を行う。絶縁膜２上にｎ型Ｇ
ａＮからなる低温バッファ層３を０．０１〜０．２μｍ
程度、７００〜１２００℃でｎ型ＧａＮからなる高温バ
ッファ層４を２〜５μｍ程度、ｎ型Ａｌx Ｇａ1-x Ｎ
（０＜ｘ＜１）からなる下部クラッド層５を０．１〜
０．３μｍ程度、クラッド層よりもバンドギャップエネ
ルギーが小さくなる材料、たとえばノンドープのＧａy
Ｉｎ1-y Ｎ（０＜ｙ≦１）からなる活性層６を０．０５
〜０．１μｍ程度、ｐ型Ａｌx Ｇａ1-x Ｎからなる上部
クラッド層７を０．１〜０．３μｍ程度、ｐ型ＧａＮか
らなるキャップ層８を０．３〜２μｍ程度それぞれ連続
して成長させる。First, a single crystal silicon substrate 1 whose main surface is a (111) plane is prepared and the surface oxide film is removed.
As shown in, 500 to 900 ° C. in a nitrogen atmosphere
Is heat-treated to nitride the surface silicon to form an insulating film 2 of about 1 to 5 nm made of, for example, Si 3 N 4 . Subsequently, as shown in FIG. 1B, as described in the conventional technique, an organic metal gas and an impurity gas are introduced to form a film by the MOCVD method. N-type G on the insulating film 2
The low temperature buffer layer 3 made of aN has a thickness of 0.01 to 0.2 μm.
The high temperature buffer layer 4 made of n-type GaN at 700 to 1200 ° C. for about 2 to 5 μm and n type Al x Ga 1-x N
The lower cladding layer 5 composed of (0 <x <1) is
A material whose bandgap energy is smaller than that of the cladding layer by about 0.3 μm, for example, non-doped Ga y
The active layer 6 made of In 1-y N (0 <y ≦ 1) is 0.05
About ~0.1μm, 0.1~0.3μm about the upper cladding layer 7 made of p-type Al x Ga 1-x N, and the cap layer 8 made of p-type GaN continuously respectively about 0.3~2μm Grow.
【００３１】つぎに図１（ｃ）に示されるように、積層
された半導体層の表面に、たとえばレジスト膜１１を
０．３〜３μｍの厚さに塗布形成し、半導体層のエッチ
ングされる部分が開口するようにパターニングする。こ
のパターニングは、開口部１２の側壁が基板１の表面、
すなわち積層された半導体層の表面に対して実質的に垂
直となるように行われる。Next, as shown in FIG. 1C, for example, a resist film 11 having a thickness of 0.3 to 3 μm is formed by coating on the surface of the laminated semiconductor layers, and the portion of the semiconductor layer to be etched is etched. Is patterned so as to open. In this patterning, the side wall of the opening 12 is the surface of the substrate 1,
That is, it is performed so as to be substantially perpendicular to the surface of the stacked semiconductor layers.
【００３２】そののち、たとえばＣｌ2 ガス雰囲気の下
で反応性イオンエッチングを行い、図２（ｄ）に示され
るるように、活性層６を貫通してｎ型のクラッド層５ま
たは高温バッファ層４が露出するまでエッチングする。
このエッチングにより半導体発光素子の側面が形成され
るが、このとき、活性層を露呈する発光面および光導波
路を介してそれに向き合う端面がＧａy Ｉｎ1-y Ｎ膜の
（０００１）面であるようにあらかじめ設計されてい
る。したがって、これらの端面は、滑らかで質の高い鏡
面となる。続いて、表面にＡｕ、Ａｌなどからなる金属
膜を成膜してパターニングすることにより、ｐ側電極９
およびｎ側電極１０をそれぞれキャップ層８およびエッ
チングにより露出した高温バッファ層４上に形成する
（図２（ｅ）参照）。このままこれに続いてダイシング
を行って図３に示されるのと同様のＬＥＤチップを形成
してもよいが、ｐ側電極９をマスクとしてキャップ層８
および上部クラッド層７の一部をＣｌ2 ガス雰囲気の下
での反応性イオンエッチングによりエッチングしてメサ
形状としてから、基板１をシリコン基板とその上のエピ
膜とで滑らかな結晶面が出る方向に劈開すると、発光面
が滑らかで質の高い鏡面のｐ側電極９の４〜１０μｍの
帯状の形状にストライプが形成された半導体レーザのチ
ップがえられる（図２（ｆ）参照）。After that, reactive ion etching is performed in, for example, a Cl 2 gas atmosphere, and as shown in FIG. 2D, the n-type cladding layer 5 or the high temperature buffer layer is penetrated through the active layer 6. Etch until 4 is exposed.
The side surface of the semiconductor light emitting device is formed by this etching. At this time, the end surface facing the light emitting surface exposing the active layer and the optical waveguide is the (0001) surface of the Ga y In 1 -y N film. Pre-designed. Therefore, these end surfaces are smooth and high quality mirror surfaces. Subsequently, a metal film made of Au, Al, or the like is formed on the surface and patterned to form the p-side electrode 9
And the n-side electrode 10 are formed on the cap layer 8 and the high temperature buffer layer 4 exposed by etching, respectively (see FIG. 2E). Although this may be followed by dicing to form an LED chip similar to that shown in FIG. 3, the p-side electrode 9 is used as a mask to form the cap layer 8.
And a part of the upper clad layer 7 is etched by reactive ion etching in a Cl 2 gas atmosphere to form a mesa shape, and then the substrate 1 has a direction in which a smooth crystal plane appears between the silicon substrate and the epi film thereon. When cleaved, a semiconductor laser chip is obtained in which stripes are formed in a strip shape of 4 to 10 μm of the p-side electrode 9 having a smooth and light-emitting surface with high quality (see FIG. 2F).
【００３３】この実施例では、チッ化ガリウム系化合物
半導体層を成膜するための絶縁膜がチッ化シリコン（た
とえばＳｉ3 Ｎ4 ）であり、シリコン基板表面をチッ素
雰囲気中で熱処理するだけの簡単な工程で形成され、ま
た、チッ化ガリウム系化合物半導体層とチッ素原子を共
通して有するため、これらの界面で整合を取りやすく、
歪みを小さく押さえることができる。In this embodiment, the insulating film for forming the gallium nitride based compound semiconductor layer is silicon nitride (for example, Si 3 N 4 ), and the surface of the silicon substrate is simply heat-treated in a nitrogen atmosphere. It is formed by a simple process, and since it has a nitrogen atom in common with the gallium nitride-based compound semiconductor layer, it is easy to match at these interfaces,
Distortion can be kept small.
【００３４】一方、本発明の製法の他の実施例では、前
述の実施例と同様に、まず、主面が（１１１）面である
単結晶シリコン基板を用意して、スパッタ法、蒸着法な
どによって０．０１〜０．１μｍ程度の酸化アルミニウ
ムＡｌ2 Ｏ3 などの絶縁膜２を形成する。以下前述の実
施例と同様にして、バッファ層、クラッド層、活性層と
なるチッ化ガリウム系化合物半導体層をＭＯＣＶＤ法に
よってそれぞれ積層し、図２（ｆ）もしくは図３に示さ
れるような半導体発光素子をうる。On the other hand, in another embodiment of the manufacturing method of the present invention, as in the above-mentioned embodiments, first, a single crystal silicon substrate having a (111) main surface is prepared, and the sputtering method, vapor deposition method, etc. are prepared. Then, the insulating film 2 of aluminum oxide Al 2 O 3 or the like having a thickness of about 0.01 to 0.1 μm is formed. Thereafter, in the same manner as in the above-mentioned embodiment, the buffer layer, the cladding layer, and the gallium nitride-based compound semiconductor layer serving as the active layer are laminated by the MOCVD method, and the semiconductor light emission as shown in FIG. Get the element.
【００３５】この実施例のように、単結晶シリコン基板
上に、酸化アルミニウムを介在させて成膜されたチッ化
ガリウム系化合物半導体層は、その膜質が安定するの
で、それぞれの層の特性に幅をもたせることができ、発
光素子の設計が容易になる。The gallium nitride-based compound semiconductor layer formed on a single crystal silicon substrate with aluminum oxide interposed therebetween as in this example has stable film quality, and thus the characteristics of each layer are wide. Can be provided, which facilitates the design of the light emitting element.
【００３６】いずれの実施例においても、本発明によれ
ば、活性層６の両側発光端面は共に基板１の表面に対し
て実質的に垂直になっており、活性層６の上下はバンド
ギャップエネルギーが大きいクラッド層で挟まれ、両端
面が鏡面で囲まれた共振器となり、発振効率のすぐれた
半導体レーザがえられるとともに、活性層６から出射さ
れるレーザビームは基板表面と平行に進み、レーザビー
ムと集光レンズとの光軸合わせも容易にすることができ
る。In each of the embodiments, according to the present invention, both light emitting end faces of the active layer 6 are substantially perpendicular to the surface of the substrate 1, and the upper and lower sides of the active layer 6 have band gap energy. Are sandwiched between large clad layers, and both end faces are surrounded by mirror surfaces to form a resonator, which makes it possible to obtain a semiconductor laser with excellent oscillation efficiency, and the laser beam emitted from the active layer 6 advances in parallel with the substrate surface. It is also possible to easily align the optical axes of the beam and the condenser lens.
【００３７】前記各実施例ではメサエッチングすること
により電流の注入領域をストライプ形状にする半導体レ
ーザの例で説明したが、たとえばクラッド層内にストラ
イプ溝の形成された反対導電型の電流ブロッキング層を
設ける構造や埋込み構造の半導体レーザでも本発明によ
り基板表面に垂直な端面を形成でき、チッ化ガリウム系
化合物半導体層を用いた青色の半導体レーザをうること
ができる。また、チッ化ガリウム系の半導体材料も前述
の組成に限定されず、一般にＡｌp Ｇａq Ｉｎ1-p-q Ｎ
（０≦ｐ＜１、０＜ｑ≦１、０＜ｐ＋ｑ≦１）からなり
活性層のバンドギャップエネルギーがクラッド層のバン
ドギャップエネルギーより小さくなるようにｐ、ｑを選
定すればよい。また前記Ａｌp Ｇａq Ｉｎ1-p-q ＮのＮ
の一部または全部をＡｓおよび／またはＰなどで置換し
た材料でも同様に本発明を適用できる。さらにレーザダ
イオードに限らず、ＬＥＤでも上部から発光させない
で、側面から発光するＬＥＤにおいては、本発明により
垂直な端面から発光させることができ、発光方向を一定
方向に揃えることができ、ダブルヘテロ接合に限らず、
ｐｎ接合でも同様に本発明を適用できる。In each of the above-described embodiments, description has been made on the example of the semiconductor laser in which the current injection region is formed into a stripe shape by mesa etching. However, for example, a current blocking layer of the opposite conductivity type in which a stripe groove is formed in the cladding layer is used. According to the present invention, an end face perpendicular to the substrate surface can be formed even with a semiconductor laser having a structure to be provided or a buried structure, and a blue semiconductor laser using a gallium nitride based compound semiconductor layer can be obtained. Further, the gallium nitride based semiconductor material is not limited to the above-mentioned composition, and is generally Al p Ga q In 1 -pq N 2.
(0 ≦ p <1, 0 <q ≦ 1, 0 <p + q ≦ 1) and p and q may be selected so that the bandgap energy of the active layer is smaller than the bandgap energy of the cladding layer. In addition, the N of Al p Ga q In 1-pq N is
The present invention can be similarly applied to a material in which a part or all of is replaced with As and / or P or the like. Further, not only the laser diode, but also the LED, which does not emit light from the upper side but emits light from the side surface, can emit light from a vertical end face according to the present invention, and the light emitting direction can be aligned in a certain direction. Not only
The present invention can be similarly applied to a pn junction.
【００３８】さらに端面をエッチングによって形成する
ことにかえて、劈開によって行ってもよい。このばあい
は、ｎ側電極１０を形成するためにエッチングを行った
のと直交する方向に劈開し、その端面が発光面を含むよ
うにしておくと品質の高い鏡面に挟まれた光共振器の作
製が可能となる。Further, instead of forming the end face by etching, cleavage may be performed. In this case, it is possible to manufacture an optical resonator sandwiched between high-quality mirror surfaces by cleaving in a direction orthogonal to the etching performed to form the n-side electrode 10 so that its end surface includes the light emitting surface. Is possible.
【００３９】[0039]
【発明の効果】本発明によれば、基板として単結晶基板
を用い、薄い絶縁膜を介してチッ化ガリウム系化合物半
導体層を成膜するので、従来のように、サファイア基板
に直接チッ化ガリウム系化合物半導体層を成膜するばあ
いに比べて界面での歪みが小さくなる。また、基板その
ものが安価に手に入り、加工性に優れているので、デバ
イス化が容易である。According to the present invention, a single crystal substrate is used as a substrate and a gallium nitride compound semiconductor layer is formed through a thin insulating film. Therefore, as in the conventional case, the gallium nitride compound semiconductor layer is directly formed on the sapphire substrate. The strain at the interface becomes smaller than when the system compound semiconductor layer is formed. In addition, the substrate itself can be obtained at low cost and has excellent workability, so that it can be easily made into a device.
【００４０】さらにクラッド層などの厚いチッ化ガリウ
ム系化合物半導体層と単結晶シリコン基板が構成の大半
を占めるので、チップを分離するに際して劈開すること
もでき、発光端面を鏡面とすることもできる。その結
果、青色の半導体レーザも容易にうることができる。Further, since a thick gallium nitride compound semiconductor layer such as a clad layer and the single crystal silicon substrate occupy most of the constitution, it can be cleaved when the chips are separated, and the light emitting end surface can be made a mirror surface. As a result, a blue semiconductor laser can be easily obtained.
【図１】本発明の半導体発光素子の一実施例を製造工程
（前半）に従って示す図である。FIG. 1 is a diagram showing an embodiment of a semiconductor light emitting device of the present invention according to a manufacturing process (first half).
【図２】本発明の半導体発光素子の一実施例を製造工程
（後半）に従って示す図である。FIG. 2 is a diagram showing an embodiment of a semiconductor light emitting device of the present invention according to a manufacturing process (second half).
【図３】本発明の他の実施例であるＬＥＤの断面説明図
である。FIG. 3 is a cross-sectional explanatory view of an LED which is another embodiment of the present invention.
【図４】従来のＧａＮ系ＬＥＤの断面説明図である。FIG. 4 is a cross-sectional explanatory view of a conventional GaN-based LED.
【図５】従来のサファイヤ基板上に形成されたバッファ
層に発生する転位の状況を説明する図である。FIG. 5 is a diagram illustrating a situation of dislocations generated in a buffer layer formed on a conventional sapphire substrate.
１ 単結晶シリコン基板 ２ 絶縁膜 ３ 低温バッファ層 ４ 高温バッファ層 ５ ｎ型クラッド層 ６ 活性層 ７ ｐ型クラッド層 DESCRIPTION OF SYMBOLS 1 Single crystal silicon substrate 2 Insulating film 3 Low temperature buffer layer 4 High temperature buffer layer 5 n-type clad layer 6 Active layer 7 p-type clad layer
Claims (11)
基板上に形成された絶縁膜および該絶縁膜上に積層され
たチッ化ガリウム系化合物半導体層を構成要素とする半
導体発光素子。1. A semiconductor light emitting device comprising a single crystal silicon substrate, an insulating film formed on the single crystal silicon substrate, and a gallium nitride-based compound semiconductor layer laminated on the insulating film.
を主面とした基板である請求項１記載の半導体発光素
子。2. The semiconductor light emitting device according to claim 1, wherein the single crystal silicon substrate is a substrate having a (111) plane as a main surface.
項１または２記載の半導体発光素子。3. The semiconductor light emitting device according to claim 1, wherein the insulating film is silicon nitride.
求項１または２記載の半導体発光素子。4. The semiconductor light emitting device according to claim 1, wherein the insulating film is aluminum oxide.
が、ｐ型層およびｎ型層を含む複数の層であり、かつ、
発光のための活性層を有する請求項１、２、３または４
記載の半導体発光素子。5. The gallium nitride-based compound semiconductor layer is a plurality of layers including a p-type layer and an n-type layer, and
5. An active layer for light emission, claim 1, 2, 3 or 4.
The semiconductor light-emitting device as described above.
が、バッファ層、下部クラッド層、活性層、上部クラッ
ド層、キャップ層からなる請求項１、２、３、４または
５記載の半導体発光素子。6. The semiconductor light emitting device according to claim 1, wherein the gallium nitride compound semiconductor layer comprises a buffer layer, a lower clad layer, an active layer, an upper clad layer, and a cap layer.
クラッド層がｎ型Ａｌx Ｇａ1-x Ｎ（０＜ｘ＜１）、前
記活性層がＧａy Ｉｎ1-y Ｎ（０＜ｙ≦１）、前記上部
クラッド層がｐ型Ａｌx Ｇａ1-x Ｎ（０＜ｘ＜１）、前
記キャップ層がｐ型ＧａＮである請求項６記載の半導体
発光素子。7. The buffer layer is n-type GaN, the lower cladding layer is n-type Al x Ga 1-x N (0 <x <1), and the active layer is Ga y In 1-y N (0 <y. ≦ 1), the upper cladding layer is p-type Al x Ga 1 -x N (0 <x <1), and the cap layer is p-type GaN.
る工程、前記絶縁膜上にチッ化ガリウム系化合物半導体
層を成膜してバッファ層とする工程、前記バッファ層上
にチッ化ガリウム系化合物半導体からなる下部クラッド
層、活性層、上部クラッド層およびキャップ層を順次積
層する工程、前記単結晶シリコン基板に垂直にエッチン
グして、前記バッファ層を露出させる工程、前記キャッ
プ層および前記エッチングにより露出したバッファ層上
に電極を形成する工程、およびダイシングまたは劈開に
よってチップに分離する工程、からなる半導体発光素子
の製法。8. A step of forming an insulating film on a single crystal silicon substrate, a step of forming a gallium nitride based compound semiconductor layer on the insulating film to form a buffer layer, and a gallium nitride based on the buffer layer. A step of sequentially laminating a lower clad layer, an active layer, an upper clad layer and a cap layer made of a compound semiconductor; a step of vertically etching the single crystal silicon substrate to expose the buffer layer; A method of manufacturing a semiconductor light emitting device, which comprises a step of forming an electrode on an exposed buffer layer, and a step of separating into chips by dicing or cleavage.
を主面とする基板である請求項８記載の半導体発光素子
の製法。9. The method for manufacturing a semiconductor light emitting device according to claim 8, wherein the single crystal silicon substrate is a substrate whose main surface is a (111) plane.
結晶シリコン基板の表面酸化膜を除去したのち、チッ素
雰囲気中で熱処理してチッ化シリコン膜を形成する工程
である請求項８または９記載の半導体発光素子の製法。10. The step of forming the insulating film is a step of removing a surface oxide film of the single crystal silicon substrate and then performing a heat treatment in a nitrogen atmosphere to form a silicon nitride film. 9. The method for manufacturing a semiconductor light emitting device described in 9.
ルミニウムを成膜する工程である請求項８または９記載
の半導体発光素子の製法。11. The method for manufacturing a semiconductor light emitting element according to claim 8, wherein the step of forming the insulating film is a step of forming aluminum oxide.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20248094A JPH0864913A (en) | 1994-08-26 | 1994-08-26 | Semiconductor light emitting element and its manufacture |
| US08/517,121 US5838029A (en) | 1994-08-22 | 1995-08-21 | GaN-type light emitting device formed on a silicon substrate |
| US09/149,435 US6087681A (en) | 1994-08-08 | 1998-09-08 | GaN semiconductor light emitting device having a group III-V substrate |
| US09/569,300 US6376866B1 (en) | 1994-08-22 | 2000-05-11 | GaN semiconductor light emitting device having a group II-VI substrate |
| US10/127,810 US6680492B2 (en) | 1994-08-22 | 2002-04-23 | Semiconductor light emitting device and method for producing the same |
| US10/690,624 US7071015B2 (en) | 1994-08-22 | 2003-10-23 | Semiconductor light emitting device and method for producing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20248094A JPH0864913A (en) | 1994-08-26 | 1994-08-26 | Semiconductor light emitting element and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0864913A true JPH0864913A (en) | 1996-03-08 |
Family
ID=16458216
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20248094A Pending JPH0864913A (en) | 1994-08-08 | 1994-08-26 | Semiconductor light emitting element and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0864913A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000016378A2 (en) * | 1998-09-15 | 2000-03-23 | National University Of Singapore | Method of fabricating group-iii nitride-based semiconductor device |
| JP2008034834A (en) * | 2006-07-25 | 2008-02-14 | Samsung Electro Mech Co Ltd | Growing method of nitride single crystal on silicon substrate, nitride-semiconductor light-emitting element using the same and manufacturing method of the same |
| JP2008504715A (en) | 2004-06-28 | 2008-02-14 | ニトロネックス コーポレイション | Gallium nitride materials and methods |
| JP2009152627A (en) * | 1998-01-16 | 2009-07-09 | Mitsubishi Materials Corp | Method of manufacturing substrate with nitride semiconductor layer |
| JP2013033887A (en) * | 2011-08-03 | 2013-02-14 | Covalent Materials Corp | Nitride semiconductor substrate manufacturing method |
| WO2013145404A1 (en) * | 2012-03-28 | 2013-10-03 | 株式会社豊田中央研究所 | Laminated substate of silicon single crystal and group iii nitride single crystal with off angle |
| JP2014522126A (en) * | 2011-08-08 | 2014-08-28 | イルジン エルイーディー カンパニー リミテッド | Nitride semiconductor light emitting device having excellent leakage current blocking effect and method for manufacturing the same |
| WO2023037838A1 (en) * | 2021-09-09 | 2023-03-16 | 信越半導体株式会社 | Method for manufacturing nitride semiconductor substrate |
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1994
- 1994-08-26 JP JP20248094A patent/JPH0864913A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009152627A (en) * | 1998-01-16 | 2009-07-09 | Mitsubishi Materials Corp | Method of manufacturing substrate with nitride semiconductor layer |
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| JP2008504715A (en) | 2004-06-28 | 2008-02-14 | ニトロネックス コーポレイション | Gallium nitride materials and methods |
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