JPH0845988A - Connection method for circuit - Google Patents

Connection method for circuit

Info

Publication number
JPH0845988A
JPH0845988A JP7219300A JP21930095A JPH0845988A JP H0845988 A JPH0845988 A JP H0845988A JP 7219300 A JP7219300 A JP 7219300A JP 21930095 A JP21930095 A JP 21930095A JP H0845988 A JPH0845988 A JP H0845988A
Authority
JP
Japan
Prior art keywords
adhesive
light
chip
liquid crystal
crystal panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7219300A
Other languages
Japanese (ja)
Inventor
Katsuma Endo
甲午 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP7219300A priority Critical patent/JPH0845988A/en
Publication of JPH0845988A publication Critical patent/JPH0845988A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To enhance reliability at the joint of circuits formed while facing each other by irradiating a transparent circuit boards with a light through a lens from the rear side hardening an adhesive while shifting the focus of the lens and jointing the circuits facing each other while conducting. CONSTITUTION:An IC chip 1 is mounted on a liquid crystal panel 2 which is then irradiated, from the rear side with a light 5 having high intensity. Consequently, an adhesive 4 sandwiched between the IC chip 1 and the liquid crystal panel 2 is hardened thus jointing the IC chip 1 and the liquid crystal panel 2 basically. In other words, the light 5 is projected from the rear surface of the IC chip 1 through a lens 7. Since the light 5 is focused on a plane located above the surface of the IC chip 1, the adhesive layer 4 on the rear surface of the IC chip 1 is not focused but irradiated with the light 5 over a wider range. Consequently, the adhesive is hardened uniformly over the entire area on the rear surface of the IC chip 1 thus realizing a highly reliable joint.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明はポケットテレビ、壁
掛けテレビ、プロジェクションテレビ、ラップトップパ
ソコン、ゲーム機、等に用いられる液晶パネルやその他
の回路部品の実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a liquid crystal panel and other circuit components used in pocket televisions, wall televisions, projection televisions, laptop personal computers, game consoles and the like.

【０００２】[0002]

【従来の技術】従来よりポケットテレビなど液晶パネル
を組み込むためには小型、高密度実装の液晶パネルを構
成する必要がある。その対策の一例として液晶パネルを
構成しているガラス基板上にＩＣチップを直接搭載する
方法が提案されている。2. Description of the Related Art Conventionally, in order to incorporate a liquid crystal panel such as a pocket television, it is necessary to construct a small-sized, high-density mounted liquid crystal panel. As an example of such measures, there has been proposed a method of directly mounting an IC chip on a glass substrate forming a liquid crystal panel.

【０００３】以下図面を参照しながら、従来の液晶パネ
ルについて説明する。図５、６は従来の液晶パネルの一
例を示すものである。図５は相対峙して形成された接続
用回路すなわちＩＣチップと液晶パネルガラスの電極パ
ターンの間に絶縁性接着剤あるいは絶縁性接着剤中に導
電性微粒子を分散させた接着剤を狭持して上記相対峙す
る接続用回路を位置合わせする工程、図６は液晶パネル
ガラスの裏面から光を照射して接着剤を加熱し硬化して
ＩＣチップと液晶パネルガラスの電極パターンを本圧着
接合した様子を示す。A conventional liquid crystal panel will be described below with reference to the drawings. 5 and 6 show an example of a conventional liquid crystal panel. FIG. 5 shows an insulating adhesive or an adhesive in which conductive fine particles are dispersed in the insulating adhesive sandwiched between the IC chip and the electrode pattern of the liquid crystal panel glass, which is a connection circuit formed by facing each other. 6 is a step of aligning the above-mentioned connection circuits which are relatively opposed to each other. In FIG. 6, the adhesive is heated and cured by irradiating light from the back surface of the liquid crystal panel glass, and the IC chip and the electrode pattern of the liquid crystal panel glass are permanently pressure-bonded. Show the situation.

【０００４】図５、６において２１はＩＣチップ、２２
は液晶パネル、２３は液晶パネルの基板上に形成された
電極パターン、２４は導電性微粒子を絶縁性接着剤中に
分散させた接着剤層、２５はＡｕバンプ、２６は圧着ツ
ールを示す、２７は光、２８はレンズをしめす。ＩＣチ
ップ上には電極パッドが形成されている。その電極パッ
ド上にはＡｕバンプが形成されている。液晶パネルの基
板上には上記ＩＣチップの接続電極と相対峙して接続用
回路が形成されている。In FIGS. 5 and 6, reference numeral 21 denotes an IC chip, 22
Is a liquid crystal panel, 23 is an electrode pattern formed on the substrate of the liquid crystal panel, 24 is an adhesive layer in which conductive fine particles are dispersed in an insulating adhesive, 25 is an Au bump, 26 is a pressure bonding tool, 27 Is light and 28 is a lens. Electrode pads are formed on the IC chip. Au bumps are formed on the electrode pads. A connection circuit is formed on the substrate of the liquid crystal panel, facing the connection electrodes of the IC chip.

【０００５】[0005]

【発明が解決しようとする課題】図５において、絶縁性
接着剤あるいは絶縁性接着剤中に導電性微粒子を分散さ
せた接着剤は相対峙して形成された接続用回路すなわち
ＩＣチップと液晶パネルガラスの電極パターンの間に加
熱や加圧無しに狭持される、この時相対峙して形成され
た接続用回路すなわちＩＣチップと液晶パネルガラスの
電極パターンは純粋に位置合わせされる。その後、図６
においてＩＣチップの上から比較的低温のツールによっ
て加圧されながら液晶パネルの裏面から光が照射され接
着剤層が加熱され、上記接着剤を加熱硬化してＩＣチッ
プと液晶パネルガラスの電極パターンは導通接続され
る。この時、一般的に用いられる接着剤としてのエポキ
シ系の接着剤は完全硬化する。In FIG. 5, an insulating adhesive or an adhesive in which conductive fine particles are dispersed in the insulating adhesive is a connection circuit formed by facing each other, that is, an IC chip and a liquid crystal panel. The connection circuit, which is sandwiched between the electrode patterns of glass without heating or pressurization, is formed relative to each other, that is, the IC chip and the electrode pattern of the liquid crystal panel glass are purely aligned. After that, FIG.
In, while pressure is applied from above the IC chip by a tool at a relatively low temperature, light is irradiated from the back surface of the liquid crystal panel to heat the adhesive layer, and the adhesive is heated and cured to form an electrode pattern of the IC chip and the liquid crystal panel glass. Conductive connection. At this time, an epoxy-based adhesive that is generally used as an adhesive is completely cured.

【０００６】しかし、従来の回路の接続用接着剤を用い
た接続構造体は図５、６より明らかなように光は白色光
の場合、そのままでは一般的には散乱してしまう。その
ため集光レンズを用いて、光を接着剤層に集光してい
る。すると、接着剤の光による温度分布が図７の様に焦
点中央で高く、その周辺で序々に低くなるという問題が
生じてしまう。図７は横軸にＩＣの断面方向の位置を示
し、縦軸にその部位の温度を示す。この様にＩＣの部位
による温度ばらつきが大きいと、接着剤の硬化進度が異
なることとなってしまう。この様に接着剤の硬化進度が
異なると、ＩＣ接合の信頼性が著しく低減してしまうも
のであった。特にＩＣコーナー部の接着剤材中の残留応
力は大きいのにもかかわらず、ＩＣのコーナー部の接着
剤の硬化進度が低くなりがちであるため、ＩＣのコーナ
ー部の接続信頼性はきわめて低減してしまうものであっ
た。However, as is clear from FIGS. 5 and 6, the conventional connection structure using the connection adhesive for the circuit generally scatters when the light is white light. Therefore, a condenser lens is used to condense the light on the adhesive layer. Then, there arises a problem that the temperature distribution due to the light of the adhesive is high in the center of the focal point and gradually decreases in the periphery thereof as shown in FIG. In FIG. 7, the horizontal axis indicates the position of the IC in the cross-sectional direction, and the vertical axis indicates the temperature at that portion. If there is a large temperature variation depending on the IC portion, the curing progress of the adhesive will be different. As described above, if the curing progress of the adhesive is different, the reliability of IC bonding is significantly reduced. In particular, even though the residual stress in the adhesive material at the corners of the IC is large, the curing progress of the adhesive at the corners of the IC tends to be low, so the connection reliability at the corners of the IC is extremely reduced. It was something that would end up.

【０００７】そこで、本発明は従来のこのような欠点を
解決し相対峙して形成された接続回路の接合の信頼性を
高くするものである。Therefore, the present invention solves the above-mentioned drawbacks of the prior art and improves the reliability of the connection of the connection circuits formed by facing each other.

【０００８】[0008]

【課題を解決するための手段】本発明による回路の接続
方法は、相対峙して形成された接続用回路の間に絶縁性
接着剤あるいは絶縁性接着剤中に導電性微粒子を分散さ
せた接着剤を狭持して接合する回路の接続方法におい
て、一方の回路基板が透明であり、接着剤を狭持しなが
ら上記相対峙する接続用回路のうち透明な回路基板の裏
面から光を照射し、上記光はレンズを通して照射され、
上記レンズの焦点を上記接着剤からずらして、上記接着
剤を硬化させることにより、上記相対峙する接続用回路
を導通接合せしめて接合固定することを特徴とする。SUMMARY OF THE INVENTION A circuit connecting method according to the present invention comprises an insulating adhesive or an adhesive in which conductive fine particles are dispersed in an insulating adhesive between connecting circuits formed by facing each other. In the circuit connecting method of sandwiching and bonding an agent, one circuit board is transparent, and light is irradiated from the back surface of the transparent circuit board of the connecting circuit which holds the adhesive while sandwiching the adhesive. , The light is emitted through the lens,
The focus of the lens is deviated from the adhesive and the adhesive is cured, so that the connecting circuits that are relatively facing each other are conductively joined and fixed.

【０００９】[0009]

【発明の実施の形態】図１〜３は本発明による回路の接
続工程を示す。図１は相対峙して形成された接続用回路
すなわちＩＣチップと液晶パネルガラスの電極パターン
の間に絶縁性接着剤あるいは絶縁性接着剤中に導電性微
粒子を分散させた接着剤を狭持して上記相対峙する接続
用回路を位置合わせする工程を示し、また図２，３はＩ
Ｃの上から圧力が加えられながら上記狭持された接着剤
に対し、液晶パネルのガラスの裏面よりレンズを通した
光が焦点をぼかして広く光が照射されている。1 to 3 show a circuit connecting process according to the present invention. FIG. 1 shows an insulating adhesive or an adhesive in which conductive fine particles are dispersed in an insulating adhesive sandwiched between an IC chip and an electrode pattern of a liquid crystal panel glass, which is a connection circuit formed by facing each other. FIG. 2 and FIG. 3 show the step of aligning the above-mentioned connection circuits for relative connection.
The light passing through the lens is defocused from the rear surface of the glass of the liquid crystal panel, and the light is widely irradiated to the adhesive sandwiched while pressure is applied from above C.

【００１０】図１、２、３に於て、１はＩＣチップ、２
は液晶パネル、３は液晶パネルの基板上に形成された電
極パターン、４は接着剤、５は光、６はＡｕバンプ、７
はレンズ、８は圧着ツールを示す。In FIGS. 1, 2, and 3, 1 is an IC chip, 2
Is a liquid crystal panel, 3 is an electrode pattern formed on the substrate of the liquid crystal panel, 4 is an adhesive, 5 is light, 6 is Au bumps, 7
Is a lens, and 8 is a crimping tool.

【００１１】また図４は本発明において接着剤を硬化す
る場合のＩＣ下の温度分布をＩＣの断面について図示し
たものである。FIG. 4 shows the temperature distribution under the IC in the case of curing the adhesive in the present invention with respect to the cross section of the IC.

【００１２】図１、２、３においてＩＣを液晶パネルの
上に載置し強度のつよい光を液晶パネルの裏面から照射
すれば、光の熱によってＩＣと液晶パネルのあいだに挟
持した接着剤は硬化しＩＣと液晶パネルを基本的に接合
硬化する事ができる。In FIGS. 1, 2 and 3, when the IC is placed on the liquid crystal panel and strong light is emitted from the back surface of the liquid crystal panel, the adhesive sandwiched between the IC and the liquid crystal panel by the heat of light is generated. It can be cured to basically bond and cure the IC and the liquid crystal panel.

【００１３】図４より明らかなようにＩＣの下面の温度
分布はほぼ均一になっている。光を照射するレンズの焦
点を接着剤層面よりずらしてあるで、照射される光の輝
度ばらつきが緩和されるためである。そして、照射する
光の焦点がずれると、被照射物の光のあたっている面積
が増えるためである。As is apparent from FIG. 4, the temperature distribution on the lower surface of the IC is almost uniform. This is because the focus of the lens that irradiates the light is shifted from the surface of the adhesive layer, so that the variation in the brightness of the radiated light is reduced. Then, when the focal point of the irradiation light is shifted, the area of the irradiation object irradiated with the light increases.

【００１４】この様に、ＩＣの下面の温度分布が均一に
なると、接着剤の硬化進度もＩＣ下面全域で均一とな
る。すなわち、光照射による硬化後の接着剤の硬化度合
のばらつきが極めてすなくなる 。このように、ＩＣ下
面の接着剤の硬化度合のばらつきが小さくなると、部分
的に接着強度が弱いところもなくなる。従って、接続信
頼性を大幅に向上する事が出来るものである。特に、Ｉ
Ｃコーナー部はもともと接合による残留応力が大きいと
ころであり、この様に、残留応力の大きいところに光が
充分照射され接着剤の硬化進度が他の所に引けをとらず
に充分であると信頼性がますます向上することとなる。As described above, when the temperature distribution on the lower surface of the IC becomes uniform, the curing progress of the adhesive becomes uniform over the entire lower surface of the IC. That is, the variation in the curing degree of the adhesive after curing by light irradiation becomes extremely small. As described above, when the variation in the degree of curing of the adhesive on the lower surface of the IC is reduced, there is no portion where the adhesive strength is weak. Therefore, the connection reliability can be greatly improved. In particular, I
The C-corner is originally a place where the residual stress due to the joining is large, and thus, it is reliable that the place where the residual stress is large is sufficiently irradiated with light so that the curing progress of the adhesive is not inferior to other places. Will be improved more and more.

【００１５】図２において、ＩＣ下面からレンズをとう
して光が照射され、この光の焦点はＩＣ面より上面に設
定されているのでＩＣ下面の接着剤層は焦点がぼけ、広
く光があたっている。また図３においては光の焦点はＩ
Ｃよりかなり下面に設定され、ＩＣ下面の接着剤層は同
様に光の焦点はぼけており、ＩＣ下面に広く光があたっ
ている。In FIG. 2, light is emitted from the lower surface of the IC through the lens, and the focus of this light is set to the upper surface than the IC surface. Therefore, the adhesive layer on the lower surface of the IC is defocused and widely illuminated. ing. Further, in FIG. 3, the focus of light is I
It is set considerably lower than C, and the adhesive layer on the lower surface of the IC also has a defocused light, and the lower surface of the IC is widely illuminated.

【００１６】[0016]

【発明の効果】本発明は以上説明したように、ＩＣチッ
プと液晶パネルの電極を接着剤シートを狭持して接合す
る回路の接続方法において、ＩＣ下面全域の接着剤の硬
化進度を均一にし、接合の信頼性を向上させる効果があ
る。As described above, according to the present invention, in the circuit connecting method for bonding the IC chip and the electrodes of the liquid crystal panel by sandwiching the adhesive sheet, the curing progress of the adhesive is made uniform over the entire lower surface of the IC. , Has the effect of improving the reliability of bonding.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の実施例において液晶パネルとＩＣチ
ップの間に接着剤シートを狭持した工程図。FIG. 1 is a process diagram in which an adhesive sheet is sandwiched between a liquid crystal panel and an IC chip in an embodiment of the present invention.

【図２】 本発明の実施例において液晶パネルの裏面に
光を照射して接着剤を硬化せしめ、ＩＣを液晶パネルに
固定している工程図。FIG. 2 is a process diagram of fixing the IC to the liquid crystal panel by irradiating the back surface of the liquid crystal panel with light to cure the adhesive in the embodiment of the present invention.

【図３】 本発明の実施例において液晶パネルの裏面に
光を照射して接着剤を硬化せしめ、ＩＣを液晶パネルに
固定している他の工程の例を示す図。FIG. 3 is a diagram showing an example of another step of fixing the IC to the liquid crystal panel by irradiating the back surface of the liquid crystal panel with light to cure the adhesive in the embodiment of the present invention.

【図４】 本発明におけるＩＣの下面の圧着時の温度分
布図。FIG. 4 is a temperature distribution diagram when the lower surface of the IC according to the present invention is pressure bonded.

【図５】 従来の実施例において、液晶パネルとＩＣチ
ップの間に接着剤シートを狭持した工程図。FIG. 5 is a process diagram in which an adhesive sheet is sandwiched between a liquid crystal panel and an IC chip in a conventional example.

【図６】 従来の実施例における、ＩＣを液晶パネルに
固定している工程図。FIG. 6 is a process diagram of fixing an IC to a liquid crystal panel in a conventional example.

【図７】 従来の実施例におけるＩＣの下面の圧着時の
温度分布図。FIG. 7 is a temperature distribution diagram at the time of crimping the lower surface of the IC in the conventional example.

【符号の説明】[Explanation of symbols]

１，２１ ＩＣチップ ２，２２ 液晶パネル ３，２３ 電極パターン ４，２４ 接着剤 ５，２８ 光 ６，２５ Ａｕバンプ ７，２７ レンズ ８，２６ 圧着ツール 1,21 IC chip 2,22 Liquid crystal panel 3,23 Electrode pattern 4,24 Adhesive 5,28 Light 6,25 Au bump 7,27 Lens 8,26 Crimping tool

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 相対峙して形成された接続用回路の間に
絶縁性接着剤あるいは絶縁性接着剤中に導電性微粒子を
分散させた接着剤を狭持して接合する回路の接続方法に
おいて、一方の回路基板が透明であり、接着剤を狭持し
ながら上記相対峙する接続用回路のうち透明な回路基板
の裏面から光を照射し、上記光はレンズを通して照射さ
れ、上記レンズの焦点を上記接着剤からずらして、上記
接着剤を硬化させることにより、上記相対峙する接続用
回路を導通接合せしめて接合固定することを特徴とする
回路の接続方法。1. A method for connecting a circuit in which an insulating adhesive or an adhesive in which conductive fine particles are dispersed in the insulating adhesive is sandwiched and bonded between the connecting circuits formed by facing each other. , One of the circuit boards is transparent, and light is radiated from the back surface of the transparent circuit board of the connecting circuit that holds the adhesive while sandwiching the adhesive, and the light is radiated through the lens to focus the lens. Is displaced from the adhesive, and the adhesive is cured so that the connecting circuits that are facing each other are conductively joined and fixed together.
JP7219300A 1995-08-28 1995-08-28 Connection method for circuit Pending JPH0845988A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7219300A JPH0845988A (en) 1995-08-28 1995-08-28 Connection method for circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7219300A JPH0845988A (en) 1995-08-28 1995-08-28 Connection method for circuit

Publications (1)

Publication Number Publication Date
JPH0845988A true JPH0845988A (en) 1996-02-16

Family

ID=16733342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7219300A Pending JPH0845988A (en) 1995-08-28 1995-08-28 Connection method for circuit

Country Status (1)

Country Link
JP (1) JPH0845988A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011082582A (en) * 2011-01-25 2011-04-21 Sony Chemical & Information Device Corp Method of manufacturing connection structure, method of anisotropic conductive connection, and connection structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011082582A (en) * 2011-01-25 2011-04-21 Sony Chemical & Information Device Corp Method of manufacturing connection structure, method of anisotropic conductive connection, and connection structure

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