JPH084209B2 - High frequency attenuating circuit and high frequency switching circuit including high frequency attenuating circuit - Google Patents
High frequency attenuating circuit and high frequency switching circuit including high frequency attenuating circuitInfo
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- JPH084209B2 JPH084209B2 JP61081907A JP8190786A JPH084209B2 JP H084209 B2 JPH084209 B2 JP H084209B2 JP 61081907 A JP61081907 A JP 61081907A JP 8190786 A JP8190786 A JP 8190786A JP H084209 B2 JPH084209 B2 JP H084209B2
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- circuit
- high frequency
- current limiting
- pin diode
- limiting resistor
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Description
【発明の詳細な説明】 産業上の利用分野 本発明は、短波乃至マイクロ波領域における通信機又
は放送機等の高周波信号の減衰に好適な高周波減衰回路
及び上記波長領域における高周波回路の切換に好適な高
周波切換回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for switching a high frequency attenuator circuit suitable for attenuating a high frequency signal of a communication device or a broadcaster in a short wave to microwave region and a high frequency circuit in the above wavelength range. And a high frequency switching circuit.
従来の技術 第９図は、従来の高周波減衰回路の一例を示す結線図
で、D1はピンダイオード、C1及びC2は直流阻止コンデン
サ、L1は高周波阻止コイル、T1及びT2は入出力端子、L2
は高周波阻止コイルで、高周波バイパスコンデンサC3と
共に高周波阻止回路を形成する。R1は電流制限抵抗、T3
はバイアス電圧印加端子である。2. Description of the Related Art FIG. 9 is a connection diagram showing an example of a conventional high-frequency attenuation circuit. D 1 is a pin diode, C 1 and C 2 are DC blocking capacitors, L 1 is a high-frequency blocking coil, and T 1 and T 2 are Input / output terminal, L 2
Is a high frequency blocking coil that forms a high frequency blocking circuit together with the high frequency bypass capacitor C 3 . R 1 is the current limiting resistor, T 3
Is a bias voltage application terminal.
端子T3に正バイアス電圧を加え、その大きさを変えて
ピンダイオードD1に流れる順方向バイアス電流を変化せ
しめると、ピンダイオードD1の内部高周波抵抗が変化
し、この変化に応じて端子T1に加えられる高周波信号を
減衰せしめる。A positive bias voltage applied to the terminal T 3, when allowed to change the forward bias current flowing through the pin diode D 1 changes its size, internal high-frequency resistance of the pin diode D 1 is changed, the terminal T according to this change Attenuates the high frequency signal applied to 1 .
第10図は、第９図に示した従来の高周波減衰回路を２
回路、共通端子に並列接続して形成した従来の切換スイ
ッチング回路の一例を示す結線図で、D11及びD21はピン
ダイオード、C12及びC22は直流阻止コンデンサ、L12及
びL22は高周波阻止コイル、C13及びC23は高周波バイパ
スコンデンサ、R11及びR21は電流制限抵抗、T13及びT23
はバイアス電圧印加端子、T12及びT22は入出力端子、TC
は共通入出力端子、CCは共通高周波結合コンデンサ、LC
は共通高周波阻止コイルで、これらの構成は第９図と同
様である。FIG. 10 shows the conventional high frequency attenuator circuit shown in FIG.
Circuit, a connection diagram showing an example of a conventional switching switching circuit formed by connecting in parallel to a common terminal, D 11 and D 21 are pin diodes, C 12 and C 22 are DC blocking capacitors, L 12 and L 22 are high frequency Blocking coil, C 13 and C 23 are high frequency bypass capacitors, R 11 and R 21 are current limiting resistors, T 13 and T 23
Is a bias voltage application terminal, T 12 and T 22 are input / output terminals, T C
Is a common input / output terminal, C C is a common high frequency coupling capacitor, L C
Are common high-frequency blocking coils, and their configurations are the same as in FIG.
バイアス電圧印加端子T13及びT23の中、例えば端子T
13に正バイアス電圧を加え、端子T23に零電圧を加える
と、ピンダイオードD11の内部高周波抵抗が低下し、ピ
ンダイオードD21の内部高周波抵抗は高抵抗に保たれ、
逆に、端子T13に零電圧を加え、端子T23に正バイアス電
圧を加えると、ピンダイオードD11の内部高周波抵抗が
高抵抗に保たれ、ピンダイオードD21の内部高周波抵抗
が低下するから、例えば共通入出力端子TCに加えられた
高周波信号は入出力端子T12又はT22から選択的に取り出
される。Of the bias voltage applying terminals T 13 and T 23 , for example, the terminal T
When a positive bias voltage is applied to 13 and a zero voltage is applied to the terminal T 23 , the internal high frequency resistance of the pin diode D 11 is lowered and the internal high frequency resistance of the pin diode D 21 is kept high.
Conversely, if a zero voltage is applied to the terminal T 13 and a positive bias voltage is applied to the terminal T 23 , the internal high frequency resistance of the pin diode D 11 is kept high and the internal high frequency resistance of the pin diode D 21 decreases. For example, the high frequency signal applied to the common input / output terminal T C is selectively taken out from the input / output terminal T 12 or T 22 .
第11図も亦従来の高周波減衰回路の一例を示す結線図
で、この回路においては入出力端子T1及びT2間にピンダ
イオードD11及びD12を互いに直列に挿入すると共に、ピ
ンダイオードD11及びD12間を接続する線路の長さを電気
長でλ/4（λは伝送波長）に選んで位相回路を形成して
ある。他の符号を付した素子は第９図における同符号の
素子と同様の素子である。FIG. 11 is also a connection diagram showing an example of a conventional high-frequency attenuation circuit. In this circuit, pin diodes D 11 and D 12 are inserted in series between input / output terminals T 1 and T 2 and pin diode D The length of the line connecting 11 and D 12 is selected to be λ / 4 (where λ is the transmission wavelength) in terms of electrical length to form a phase circuit. The elements with other reference numerals are the same as the elements with the same reference numerals in FIG.
端子T3に正バイアス電圧を加えてピンダイオードD12
及びD11に順方向バイアス電流を流すと、この電流の大
きさに応じてピンダイオードD12及びD11の内部高周波抵
抗が変化し、例えば端子T1に加えられる高周波信号を減
衰せしめるが、この回路は高周波減衰回路を２段縦続接
続した回路と等価となり、第９図に示した回路に比し減
衰特性を向上せしめることが出来る。Pin diode D 12 and a positive bias voltage applied to the terminal T 3
And the flow forward bias current to D 11, the internal high-frequency resistance of the pin diode D 12 and D 11 is changed in accordance with the magnitude of this current, but allowed to attenuate high frequency signals applied example to the terminal T 1, the The circuit is equivalent to a circuit in which two high-frequency attenuating circuits are connected in cascade, and the attenuation characteristics can be improved as compared with the circuit shown in FIG.
第12図は、第11図に示した高周波減衰回路を２回路、
共通端子に並列接続して形成した従来の切換スイッチン
グ回路の一例を示す結線図で、D111及びD112、D211及び
D212はピンダイオードで、それぞれλ/4線路を介して互
いに直列に接続してある。他の符号は第10図及び第11図
と同様である。FIG. 12 shows two high-frequency attenuating circuits shown in FIG.
FIG. 3 is a connection diagram showing an example of a conventional switching switching circuit formed by connecting in parallel to a common terminal, showing D 111 and D 112 , D 211 and
D 212 is a pin diode, which is connected in series with each other via a λ / 4 line. Other reference numerals are the same as those in FIGS. 10 and 11.
端子T13（又はT23）は正バイアス電圧を加えると共
に、端子T23（又はT13）に零電圧を加えると、ピンダイ
オードD111及びD112（又はD211及びD212）の内部高周波
抵抗が低下し、ピンダイオードD211及びD212（又はD111
及びD112）の内部高周波抵抗が高抵抗に保たれ、共通端
子TCに加えられた高周波信号が端子T12（又はT22）から
選択的に取り出される。When a positive bias voltage is applied to the terminal T 13 (or T 23 ), and a zero voltage is applied to the terminal T 23 (or T 13 ), the internal high frequency resistance of the pin diodes D 111 and D 112 (or D 211 and D 212 ). The pin diodes D 211 and D 212 (or D 111
The internal high frequency resistance of D 112 and D 112 ) is kept high, and the high frequency signal applied to the common terminal T C is selectively taken out from the terminal T 12 (or T 22 ).
発明が解決しようとする問題点 第９図及び第10図に示した従来の回路においては、ピ
ンダイオードの内部高周波抵抗を高抵抗となした場合に
おいても減衰量が小なる欠点を有し、第11図及び第12図
に示した従来の回路においては、ピンダイオードの内部
高周波抵抗を高抵抗となした場合、ピンダイオード間に
介在せしめたλ/4線路より成る位相回路のλに一致する
波長の信号に対する減衰量は大であるが、この位相回路
の有する大なる周波数特性のために広帯域に亙って減衰
量を大ならしめ得ない欠点を有する。Problems to be Solved by the Invention The conventional circuits shown in FIGS. 9 and 10 have the drawback that the attenuation is small even when the internal high frequency resistance of the pin diode is high. In the conventional circuits shown in Fig. 11 and Fig. 12, when the internal high frequency resistance of the pin diode is set to high resistance, the wavelength matching the λ of the phase circuit composed of the λ / 4 line interposed between the pin diodes is used. Although the amount of attenuation with respect to the signal is large, there is a drawback that the amount of attenuation cannot be increased over a wide band due to the great frequency characteristic of this phase circuit.
第９図に示した回路のピンダイオードD1に順方向バイ
アス電流を流した場合におけるD1の内部高周波抵抗は、
一般にほぼ１Ωであり、順方向バイアス電流を流さない
場合におけるピンダイオードD1の内部高周波抵抗は、ほ
ぼ5000Ωであるから、端子T1及びT2に接続される線路の
特性インピーダンスを50Ωに選ぶと、ピンダイオードD1
に順方向バイアス電流を流した場合におけるD1の内部高
周波抵抗１Ωを線路の特性インピーダンス50Ωで正規化
した値は0.02となるから、このときにおける第９図の回
路の基本マトリクスは、 この場合における回路の減衰量Liは、 順方向バイアス電流を流さない場合におけるピンダイ
オードD1の抵抗5000Ωを線路の特性インピーダンス50Ω
で正規化した値は100であるから、この場合における第
９図の回路の基本マトリクスは、 この場合における回路の減衰量Ｌ∞iは、 第11図に示した回路においてピンダイオードD11及びD
12の内部高周波抵抗を最低ならしめた場合における回路
の基本マトリクスは、 この場合における回路の減衰量Liは、 ピンダイオードD11及びD12の内部高周波抵抗を最高に
した場合における回路の基本マトリクスは、 この場合における回路の減衰量Ｌ∞iは、 問題点を解決するための手段、実施例 第１図は、本発明の一実施例を示す結線図で、T1は入
力（又は出力）端子、T2は出力（又は入力）端子、T3は
バイアス電圧引加端子、C1は第１の直流阻止コンデン
サ、C2は第２の直流阻止コンデンサ、D1は第１のピンダ
イオード（pin-diode）、D2は第２のピンダイオード、L
1は第１の高周波阻止コイル、L2は第２の高周波阻止コ
イル、R1は第１の電流制限抵抗、R2は第２の電流制限抵
抗、R3は第３の電流制限抵抗、R4は第４の電流制限抵抗
で、この中、第２の電流制限抵抗R2は可変抵抗より成
る。C3は第１のバイパスコンデンサ、C4は第２のバイパ
スコンデンサ、C5は第３のバイパスコンデンサである。The internal high frequency resistance of D 1 when a forward bias current is applied to the pin diode D 1 of the circuit shown in FIG.
Generally, the internal high frequency resistance of the pin diode D 1 when the forward bias current does not flow is approximately 5000Ω, so if the characteristic impedance of the line connected to the terminals T 1 and T 2 is selected to be 50Ω. , Pin diode D 1
The value obtained by normalizing the internal high-frequency resistance 1Ω of D 1 with the characteristic impedance of 50Ω of the line when a forward bias current is applied to is 0.02, so the basic matrix of the circuit in FIG. 9 at this time is The attenuation amount L i of the circuit in this case is The resistance of the pin diode D 1 is 5000Ω when the forward bias current is not applied and the characteristic impedance of the line is 50Ω.
Since the value normalized by is 100, the basic matrix of the circuit in FIG. 9 in this case is The attenuation amount L ∞i of the circuit in this case is In the circuit shown in FIG. 11, pin diodes D 11 and D
The basic matrix of the circuit when the internal high frequency resistance of 12 is minimized is The attenuation amount L i of the circuit in this case is The basic matrix of the circuit when the internal high frequency resistance of the pin diodes D 11 and D 12 is maximized is The attenuation amount L ∞i of the circuit in this case is Means for Solving Problems, Embodiments FIG. 1 is a connection diagram showing an embodiment of the present invention. T 1 is an input (or output) terminal, T 2 is an output (or input) terminal, T 3 Is a bias voltage applying terminal, C 1 is a first DC blocking capacitor, C 2 is a second DC blocking capacitor, D 1 is a first pin-diode, D 2 is a second pin diode, L
1 is the first high frequency blocking coil, L 2 is the second high frequency blocking coil, R 1 is the first current limiting resistor, R 2 is the second current limiting resistor, R 3 is the third current limiting resistor, R 4 is a fourth current limiting resistor, of which the second current limiting resistor R 2 is a variable resistor. C 3 is the first bypass capacitor, C 4 is the second bypass capacitor, and C 5 is the third bypass capacitor.
第２図は、第１図の中、直流成分に関係する回路部分
の等価回路図で、SDCはバイアス電圧印加用直流電源
で、他の符号は第１図と同様である。2 is an equivalent circuit diagram of a circuit portion related to a DC component in FIG. 1, S DC is a DC power supply for applying a bias voltage, and other symbols are the same as those in FIG.
第３図は、第１図の中、ピンダイオードD1及びD2にの
み着目した基本等価回路図で、RHSはピンダイオードD1
の等価内部高周波抵抗、RHPはピンダイオードD2の等価
内部高周波抵抗で、他の符号は第１図と同様である。FIG. 3 is a basic equivalent circuit diagram focusing only on the pin diodes D 1 and D 2 in FIG. 1, and R HS is the pin diode D 1
, R HP is the equivalent internal high frequency resistance of the pin diode D 2 , and other symbols are the same as in FIG.
第２図における電流制限抵抗R1乃至R4の各抵抗値の間
に、 R1＜R3 …（10） （R2はピンダイオードD1の内部直流抵抗を含むものとす
る。） なる関係が成立するように形成すると、ブリッジ回路の
対角端子Ｂ及びＣの電位が同一レベルとなり、ピンダイ
オードD1には電流が流れるが、ピンダイオードD2には電
流が流れない。Between the resistance values of the current limiting resistors R 1 to R 4 in FIG. R 1 <R 3 (10) (R 2 is assumed to include the internal DC resistance of the pin diode D 1 ) When the relationship is established such that the potentials of the diagonal terminals B and C of the bridge circuit are at the same level. Therefore, the current flows through the pin diode D 1 , but the current does not flow through the pin diode D 2 .
即ち、第３図におけるピンダイオードD1の等価内部高
周波抵抗RHSは低抵抗（ほぼ１Ω）となり、ピンダイオ
ードD2の等価内部高周波抵抗RHPは高抵抗（ほぼ5000
Ω）となる。That is, the equivalent internal high frequency resistance R HS of the pin diode D 1 in FIG. 3 is low (approximately 1Ω), and the equivalent internal high frequency resistance R HP of the pin diode D 2 is high (approximately 5000).
Ω).
したがって、第３図における端子T1及びT2間は、高周
波信号に対して低減衰領域となる。Therefore, the region between the terminals T 1 and T 2 in FIG. 3 is in the low attenuation region for high frequency signals.
次に、第２図における電流制限抵抗R3及びR4の抵抗値
の大きさをR3＝R4ならしめると共に、電流制限抵抗R2の
抵抗値を変化せしめてR1＜R2ならしめると、ピンダイオ
ードD1を流れる電流が小となり、対角端子Ｂの電位がＣ
の電位より高くなるからピンダイオードD2にも電流が流
れることとなる。Next, the magnitudes of the resistance values of the current limiting resistors R 3 and R 4 in FIG. 2 are set to R 3 = R 4, and the resistance values of the current limiting resistor R 2 are changed to set R 1 <R 2. , The current flowing through the pin diode D 1 becomes small, and the potential of the diagonal terminal B becomes C
Since it becomes higher than the potential of, the current also flows through the pin diode D 2 .
即ち、第３図におけるピンダイオードD1の等価内部高
周波抵抗RHSが高抵抗となり、ピンダイオードD2の等価
内部高周波抵抗RHPが低抵抗となり、端子T1及びT2間
は、高周波信号に対して減衰領域となる。That is, the equivalent internal high frequency resistance R HS of the pin diode D 1 in FIG. 3 becomes high resistance, the equivalent internal high frequency resistance R HP of the pin diode D 2 becomes low resistance, and a high frequency signal is generated between the terminals T 1 and T 2. On the other hand, it becomes the attenuation area.
第２図における電流制限抵抗R2の抵抗値を最高値にま
で変化せしめると、ピンダイオードD1には電流が流れな
くなり、ピンダイオードD2に流れる電流が最大となるか
ら、第３図におけるピンダイオードD1の等価内部高周波
抵抗RHSは高抵抗領域となり、ピンダイオードD2の等価
内部高周波抵抗RHPは低抵抗領域となるから、端子T1及
びT2間は高周波信号に対して高減衰領域となる。When the resistance value of the current limiting resistor R 2 in FIG. 2 is changed to the maximum value, the current stops flowing in the pin diode D 1 and the current flowing in the pin diode D 2 becomes maximum, so the pin in FIG. Since the equivalent internal high frequency resistance R HS of the diode D 1 is in the high resistance region and the equivalent internal high frequency resistance R HP of the pin diode D 2 is in the low resistance region, high attenuation of high frequency signals between the terminals T 1 and T 2 is achieved. It becomes an area.
電流制限抵抗R2を可変抵抗を以て形成する代りに第４
図に示すように構成することにより、ピンダイオードD1
の等価内部高周波抵抗RHSを最低値から最高値へ、又は
最高値から最低値へ急速に変化せしめると同時にピンダ
イオードD2の等価内部高周波抵抗RHPを最高値から最低
値へ、又は最低値から最高値へ急速に変化せしめること
が出来る。Instead of forming the current limiting resistor R 2 with a variable resistor, the fourth
With the configuration shown in the figure, the pin diode D 1
The equivalent internal high frequency resistance R HS of the pin diode D 2 is rapidly changed from the minimum value to the maximum value or from the maximum value to the minimum value, and at the same time, the equivalent internal high frequency resistance R HP of the pin diode D 2 is changed from the maximum value to the minimum value or the minimum value. It is possible to change rapidly from the maximum value.
第４図において、Ｒ′2は固定抵抗より成る電流制限
抵抗で、ピンダイオードD1の内部直流抵抗の大きさを含
むＲ′2の抵抗値と電流制限抵抗R1、R3及びR4の各抵抗
値との間に、 なる関係をもたせてある。SWは開閉スイッチで、他の符
号は第２図と同様である。In Figure 4, R '2 is a current limiting resistor made of fixed resistance, the internal DC resistance of the pin diode D 1 R includes an amplitude' a second resistance value and current limiting resistor R 1, R 3 and R 4 Between each resistance value, Have a relationship. SW is an open / close switch, and other symbols are the same as those in FIG.
開閉スイッチSWを閉成すると、ピンダイオードD1の等
価内部高周波抵抗RHSが最低値となると共にピンダイオ
ードD2の等価内部高周波抵抗RHPが最高値となり、開閉
スイッチSWを開放すると、ピンダイオードD1の等価内部
高周波抵抗RHSが最高値となると共にピンダイオードD2
の等価内部高周波抵抗RHPが最低値となる。When the open / close switch SW is closed, the equivalent internal high frequency resistance R HS of the pin diode D 1 becomes the minimum value and the equivalent internal high frequency resistance R HP of the pin diode D 2 becomes the maximum value. The equivalent internal high frequency resistance R HS of D 1 becomes the highest value and the pin diode D 2
The equivalent internal high frequency resistance R HP becomes the lowest value.
第１図に戻って、端子T3に正バイアス電圧を加えた場
合に、ピンダイオードD1に所要の順方向バイアス電流が
流れてD1の内部高周波抵抗が所要最低値となるように、
予め正バイアス電圧の大きさ及び電流制限抵抗R1乃至R4
の各抵抗値を定めると共に、電流制限抵抗R1乃至R4の各
抵抗値の間に、 R1＜R3＝R4 なる関係をもたせておくと、ピンダイオードD1の内部高
周波抵抗が最低値となり、ピンダイオードD2の内部高周
波抵抗が最高値となるから、端子T1及びT2間は高周波信
号に対して低減衰領域となる。Returning to FIG. 1, when a positive bias voltage is applied to the terminal T 3 , the required forward bias current flows through the pin diode D 1 so that the internal high frequency resistance of D 1 becomes the required minimum value.
The magnitude of the positive bias voltage and the current limiting resistors R 1 to R 4 are preset.
While defining each resistance value of, between the resistance values of the current limiting resistors R 1 to R 4 , If the relation of R 1 <R 3 = R 4 is established, the internal high frequency resistance of the pin diode D 1 becomes the minimum value and the internal high frequency resistance of the pin diode D 2 becomes the maximum value. Therefore, the terminals T 1 and T 2 The area becomes a low attenuation region for high frequency signals.
次に電流制限抵抗R2の抵抗値を変化せしめて適宜高抵
抗とすると、ピンダイオードD1に流れる順方向バイアス
電流が減少してD1の内部高周波抵抗が高くなり、逆にピ
ンダイオードD2の内部高周波抵抗が低くなるから、端子
T1に加えられた高周波信号はピンダイオードD1により適
宜減衰せしめられ、ピンダイオードD2側に分流した高周
波信号はバイパスコンデンサC5によりバイパスされる。Next, if the resistance value of the current limiting resistor R 2 is changed to a high resistance as appropriate, the forward bias current flowing through the pin diode D 1 decreases and the internal high frequency resistance of D 1 increases, and conversely the pin diode D 2 The internal high frequency resistance of the
The high frequency signal applied to T 1 is appropriately attenuated by the pin diode D 1 , and the high frequency signal shunted to the pin diode D 2 side is bypassed by the bypass capacitor C 5 .
電流制限抵抗R2の抵抗値を最高値にまで変化せしめる
と、ピンダイオードD1の内部高周波抵抗が最高値とな
り、ピンダイオードD2の内部高周波抵抗は最低値となる
から、端子T1に加えられた高周波信号はピンダイオード
D1により阻止され、ピンダイオードD2側においてバイパ
スコンデンサC5によりバイパスされることとなる。If allowed to change the resistance value of the current limiting resistor R 2 to the highest value, the internal RF resistance of the PIN diode D 1 is the maximum value, the internal RF resistance of the PIN diode D 2 is from the lowest value, in addition to the terminal T 1 High frequency signal is pin diode
It is blocked by D 1 and bypassed by the bypass capacitor C 5 on the pin diode D 2 side.
電流制限抵抗R2を可変抵抗を以て形成する代りに、第
４図について説明したように、固定抵抗と直列に機械的
開閉スイッチ又はトランジスタのような無接点スイッチ
より成る開閉スイッチを接続し、この直列回路をピンダ
イオードD1のカソード回路に接続しても本発明を実施す
ることが出来る。Instead of forming the current limiting resistor R 2 with a variable resistor, as described with reference to FIG. 4, an open / close switch consisting of a mechanical open / close switch or a contactless switch such as a transistor is connected in series with the fixed resistor, and this series connection is used. The present invention can also be implemented by connecting the circuit to the cathode circuit of the pin diode D 1 .
尚、第１図における直流阻止コンデンサC1及びC2によ
って、伝送高周波信号に重畳する直流分が阻止され、高
周波バイパスコンデンサC3及びC4によって、バイアス電
圧に重畳する交流分が除かれ、高周波阻止コイルL1及び
L2によって、ピンダイオードD1の内部高周波抵抗が低い
場合に、高周波信号が高周波バイパスコンデンサC3及び
C4を介して地気に分流するのが防がれる。The DC blocking capacitors C 1 and C 2 in FIG. 1 block the DC component superimposed on the transmission high frequency signal, and the high frequency bypass capacitors C 3 and C 4 remove the AC component superimposed on the bias voltage. Blocking coil L 1 and
Due to L 2 , when the internal high frequency resistance of the pin diode D 1 is low, the high frequency signal is transmitted to the high frequency bypass capacitor C 3 and
Diversion to the earth via C 4 is prevented.
直流阻止コンデンサC1及びC2、高周波バイパスコンデ
ンサC3及びC4、高周波阻止コイルL1及びL2は、本発明回
路の減衰又は伝送動作をより確実ならしめるためには必
要であるが、必ずしも本発明回路の構成に欠くことの出
来ない素子ではない。The DC blocking capacitors C 1 and C 2 , the high frequency bypass capacitors C 3 and C 4 , and the high frequency blocking coils L 1 and L 2 are necessary in order to make the damping or transmission operation of the circuit of the present invention more reliable, but they are not always necessary. It is not an element indispensable for the configuration of the circuit of the present invention.
第５図は、第１図乃至第４図について説明した本発明
高周波減衰回路を２回路、共通の入力（又は出力）端子
TCに並列接続して形成した２回路切換回路の一例を示す
結線図で、T11、C11、C12、D11、D12、L11、L12、R11、
R12、R13、R14、SW1、C13、C14及びC15は、第１の高周
波減衰回路を構成する素子で、T11は出力（又は入力）
端子、C11は第１の直流阻止コンデンサ、C12は第２の直
流阻止コンデンサ、D11は第１のピンダイオード、D12は
第２のピンダイオード、L11は第１の高周波阻止コイ
ル、L12は第２の高周波阻止コイル、R11は第１の電流制
限抵抗、R13は第３の電流制限抵抗、R14は第４の電流制
限抵抗、C13は第１の高周波バイパスコンデンサ、C14は
第２の高周波バイパスコンデンサ、C15は第３の高周波
バイパスコンデンサで、これらの素子は、第１図に示し
た出力（又は入力）端子T1、第１及び第２の直流阻止コ
ンデンサC1及びC2、第１及び第２のピンダイオードD1及
びD2、第１及び第２の高周波阻止コイルL1及びL2、第１
の電流制限抵抗R1、第３及び第４の電流制限抵抗R3及び
R4、第１乃至第３の高周波バイパスコンデンサC3乃至C5
と同様構成の素子で、R12は第２の電流制限抵抗、SW1は
機械的開閉スイッチ又はトランジスタのような無接点ス
イッチ等より成る開閉スイッチで、これらは第４図に示
した第２の電流制限抵抗R2及び開閉スイッチSWと同様構
成の素子である。FIG. 5 shows two high frequency attenuating circuits according to the present invention described with reference to FIGS. 1 to 4 and a common input (or output) terminal.
A connection diagram showing an example of a two-circuit switching circuit formed by connecting in parallel with T C , including T 11 , C 11 , C 12 , D 11 , D 12 , L 11 , L 12 , R 11 ,
R 12 , R 13 , R 14 , SW 1 , C 13 , C 14 and C 15 are elements that constitute the first high frequency attenuation circuit, and T 11 is an output (or input).
Terminal, C 11 is the first DC blocking capacitor, C 12 is the second DC blocking capacitor, D 11 is the first pin diode, D 12 is the second pin diode, L 11 is the first high frequency blocking coil, L 12 is the second high frequency blocking coil, R 11 is the first current limiting resistor, R 13 is the third current limiting resistor, R 14 is the fourth current limiting resistor, C 13 is the first high frequency bypass capacitor, C 14 is the second high frequency bypass capacitor, C 15 is the third high frequency bypass capacitor, and these elements are the output (or input) terminal T 1 shown in FIG. 1 , the first and second DC blocking capacitors. C 1 and C 2 , first and second pin diodes D 1 and D 2 , first and second high frequency blocking coils L 1 and L 2 , first
Current limiting resistor R 1 , third and fourth current limiting resistors R 3 and
R 4 , first to third high frequency bypass capacitors C 3 to C 5
R 12 is a second current limiting resistor, SW 1 is a mechanical opening / closing switch or an opening / closing switch composed of a contactless switch such as a transistor, and these are the second current limiting resistor shown in FIG. It is an element having the same configuration as the current limiting resistor R 2 and the open / close switch SW.
T21、C21、C22、D21、D22、L21、L22、R21、R22、
R23、R24、SW2、C23、C24及びC25は、第２の高周波減衰
回路を構成する素子で、T21は出力（又は入力）端子、C
21は第１の直流阻止コンデンサ、C22は第２の直流阻止
コンデンサ、D21は第１のピンダイオード、D22は第２の
ピンダイオード、L21は第１の高周波阻止コイル、L22は
第２の高周波阻止コイル、R21は第１の電流制限抵抗、R
23は第３の電流制限抵抗、R24は第４の電流制限抵抗、C
23は第１の高周波バイパスコンデンサ、C24は第２の高
周波バイパスコンデンサ、C25は第３の高周波バイパス
コンデンサで、これらの素子は、第１図に示した出力
（又は入力）端子T1、第１及び第２の直流阻止コンデン
サC1及びC2、第１及び第２のピンダイオードD1及びD2、
第１及び第２の高周波阻止コイルL1及びL2、第１の電流
制限抵抗R1、第３及び第４の電流制限抵抗R3及びR4、第
１乃至第３の高周波バイパスコンデンサC3乃至C5と同様
構成の素子で、R22は第２の電流制限抵抗、SW2は機械的
開閉スイッチ又はトランジスタのような無接点スイッチ
等より成る開閉スイッチで、これらは第４図に示した第
２の電流制限抵抗R2及び開閉スイッチSWと同様構成の素
子である。T 21 , C 21 , C 22 , D 21 , D 22 , L 21 , L 22 , R 21 , R 22 ,
R 23 , R 24 , SW 2 , C 23 , C 24 and C 25 are elements that constitute the second high frequency attenuation circuit, T 21 is an output (or input) terminal, and C
21 is the first DC blocking capacitor, C 22 is the second DC blocking capacitor, D 21 is the first pin diode, D 22 is the second pin diode, L 21 is the first high frequency blocking coil, L 22 is The second high frequency blocking coil, R 21 is the first current limiting resistor, R
23 is the third current limiting resistor, R 24 is the fourth current limiting resistor, C
23 is the first high-frequency bypass capacitor, C 24 is the second high-frequency bypass capacitor, C 25 is the third high-frequency bypass capacitor, and these elements are the output (or input) terminals T 1 shown in FIG. First and second DC blocking capacitors C 1 and C 2 , first and second pin diodes D 1 and D 2 ,
First and second high frequency blocking coils L 1 and L 2 , first current limiting resistor R 1 , third and fourth current limiting resistors R 3 and R 4 , first to third high frequency bypass capacitors C 3 To C 5 are elements having the same configuration, R 22 is a second current limiting resistor, SW 2 is an opening / closing switch composed of a mechanical opening / closing switch or a contactless switch such as a transistor, and these are shown in FIG. It is an element having the same configuration as the second current limiting resistor R 2 and the open / close switch SW.
T3は共通のバイアス電圧引加端子である。T 3 is a common bias voltage applying terminal.
尚、上記記載においては、例えばC11及びC21は、何れ
も第１の直流阻止コンデンサと記載したが、C11はその
添え字11によって第１の高周波減衰回路における第１の
直流阻止コンデンサであることを表わし、C21はその添
え字21によって第２の高周波減衰回路における第１の直
流阻止コンデンサであることを表わす。In the above description, for example, C 11 and C 21 are both described as the first DC blocking capacitor, but C 11 is the first DC blocking capacitor in the first high-frequency attenuating circuit due to its subscript 11. C 21 means that it is the first DC blocking capacitor in the second high frequency attenuation circuit.
他の素子についても同様である。 The same applies to the other elements.
第５図における共通のバイアス電圧引加端子T3に加え
る正バイアス電圧の大きさ、電流制限抵抗R11乃至R14及
びR21乃至R24の各抵抗値間の関係を第１図乃至第４図に
ついて説明したと同様ならしめ、開閉スイッチSW1を開
放すると共に開閉スイッチSW2を閉成すると、ピンダイ
オードD11及びD22の各内部高周波抵抗が最高値となると
共に、ピンダイオードD12及びD21の各内部高周波抵抗は
最低値となるから、共通入出力端子TCに加えられる高周
波信号は入出力端子T21側にのみ伝送される。The relationship between the magnitude of the positive bias voltage applied to the common bias voltage applying terminal T 3 and the resistance values of the current limiting resistors R 11 to R 14 and R 21 to R 24 in FIG. 5 is shown in FIGS. When the opening and closing switch SW 1 is opened and the opening and closing switch SW 2 is closed, the internal high-frequency resistances of the pin diodes D 11 and D 22 reach their maximum values, and the pin diode D 12 and Since each internal high frequency resistance of D 21 has the lowest value, the high frequency signal applied to the common input / output terminal T C is transmitted only to the input / output terminal T 21 side.
逆に、開閉スイッチSW1を閉成すると共に、開閉スイ
ッチSW2を開放すると、共通入出力端子TCに加えられる
高周波信号は入出力端子T11側にのみ伝送されることと
なる。Conversely, when the open / close switch SW 1 is closed and the open / close switch SW 2 is opened, the high frequency signal applied to the common input / output terminal T C is transmitted only to the input / output terminal T 11 side.
したがって、例えば無線通信設備又は放送機器等にお
ける高周波信号を共通入出力端子TCに加えると共に、開
閉スイッチSW1及びSW2の開閉を適当な制御機器、例えば
計算機を利用した制御機等により制御するように構成す
ることにより、直流回路の開閉によって高周波回路の切
換を行うことが出来る。Therefore, for example, a high-frequency signal in wireless communication equipment or broadcasting equipment is applied to the common input / output terminal T C , and opening / closing of the opening / closing switches SW 1 and SW 2 is controlled by an appropriate control device, for example, a controller using a computer. With such a configuration, it is possible to switch the high frequency circuit by opening and closing the DC circuit.
第６図は、第１図乃至第４図につき説明した本発明高
周波減衰回路をｎ回路（ｎは任意の正の整数）、共通の
入力（又は出力）端子TCに並列接続して構成したｎ回路
切換回路の一例を示す図で、Tn1は、第ｎの高周波減衰
回路（以下、第ｎ回路と略記する）を形成する出力（又
は入力）端子、Cn1及びCn2は第ｎ回路を形成する第１及
び第２の直流阻止コンデンサ、Dn1及びDn2は第ｎ回路を
形成する第１及び第２のピンダイオード、Ln1及びLn2は
第ｎ回路を形成する第１及び第２の高周波阻止コイル、
Rn1、Rn2、Rn3及びRn4は第ｎ回路を形成する第１、第
２、第３及び第４の電流制限抵抗、SWnは第ｎ回路を形
成する開閉スイッチ、Cn3、Cn4及びCn5は第ｎ回路を形
成する第１、第２及び第３の高周波バイパスコンデンサ
で、他の符号は第５図と同様である。FIG. 6 is a circuit diagram in which the high frequency attenuating circuit of the present invention described with reference to FIGS. 1 to 4 is connected in parallel to an n circuit (n is an arbitrary positive integer) and a common input (or output) terminal T C. In the figure showing an example of an n-circuit switching circuit, T n1 is an output (or input) terminal forming an n-th high-frequency attenuation circuit (hereinafter abbreviated as n-th circuit), and C n1 and C n2 are n-th circuits. Forming first and second DC blocking capacitors, D n1 and D n2 are first and second pin diodes forming an nth circuit, and L n1 and L n2 are first and second forming a nth circuit. 2 high frequency blocking coil,
R n1 , R n2 , R n3 and R n4 are first, second, third and fourth current limiting resistors forming the nth circuit, SW n is an open / close switch forming the nth circuit, C n3 , C n4 and C n5 are the first, second and third high frequency bypass capacitors forming the nth circuit, and other symbols are the same as those in FIG.
この実施例においても、端子T3に加えるバイアス電圧
の大きさ、電流制限抵抗R11乃至R14、−−−−−Rn1乃
至Rn4の各抵抗値間の関係を第１図乃至第４図について
説明したと同様ならしめてある。Also in this embodiment, the magnitude of the bias voltage applied to the terminal T 3, the current limiting resistor R 11 to R 14, ----- R n1 to R the relationship between the resistance value of n4 Fig. 1 through 4 The description is the same as described in the figure.
第６図に示すように、開閉スイッチSW1を閉成すると
共に開閉スイッチSW2乃至SWnを開放すると、共通の端子
TCに加えられる高周波信号は端子T11側にのみ伝送され
る。同様にして他の任意所要の開閉スイッチを閉成する
と共に、他の開閉スイッチを開放することにより、閉成
せしめた開閉スイッチに対応する端子側にのみ高周波信
号を伝送せしめることが出来る。As shown in FIG. 6, when the open / close switch SW 1 is closed and the open / close switches SW 2 to SW n are opened, a common terminal
The high frequency signal applied to T C is transmitted only to the terminal T 11 side. Similarly, by closing any other required open / close switch and opening the other open / close switch, the high frequency signal can be transmitted only to the terminal side corresponding to the closed open / close switch.
第７図は、第５図における電流制限抵抗R12及び開閉
スイッチSW1を可変抵抗RV12を以て置換えると共に、電
流制限抵抗R22及び開閉スイッチSW2を可変抵抗RV22を以
て置換えたもので、他の構成及び符号等は第５図と同様
である。FIG. 7 is a diagram in which the current limiting resistor R 12 and the opening / closing switch SW 1 in FIG. 5 are replaced by the variable resistor R V12 , and the current limiting resistor R 22 and the opening / closing switch SW 2 are replaced by the variable resistor R V22 . Other configurations, reference numerals and the like are the same as in FIG.
この実施例においては、可変抵抗RV12の抵抗値を電流
制限抵抗R11の抵抗値と等しくすると共に、可変抵抗R
V22の抵抗値を最高ならしめると、共通の端子TCと端子T
11間が導通し、TCとT21間が遮断状態となる。逆に、可
変抵抗RV11の抵抗値を最高にすると共に、可変抵抗RV21
の抵抗値を電流制限抵抗R21の抵抗値と等しくすると、
端子TCとT11間が遮断状態となり、端子TCとT21間が導通
する。In this embodiment, the resistance value of the variable resistor R V12 is made equal to the resistance value of the current limiting resistor R 11 , and
If the resistance of V22 is maximized , common terminal T C and terminal T
There is conduction between 11 and there is an interruption between T C and T 21 . Conversely, while maximizing the resistance of the variable resistor R V11, the variable resistor R V21
If the resistance value of is equal to the resistance value of the current limiting resistor R 21 ,
The terminals T C and T 11 are cut off, and the terminals T C and T 21 are electrically connected.
可変抵抗RV12及びRV22の抵抗値を手動によって調整して
もよいが、RV12及びRV22を連動して一方の抵抗値を高く
すると同時に他方の抵抗値を低くするように自動的に制
御せしめることにより、端子TCとT11間又はTCとT21間を
遮断状態を経ることなく回路の切換を可能ならしめ、チ
エンジオーバスイッチとして作動せしめることが出来る
から、ディジタル信号を用いた通信回線の切換等に好適
である。The resistance values of variable resistors R V12 and R V22 may be adjusted manually, but R V12 and R V22 are linked to automatically control one resistance value to be high and the other resistance value to be low. By making it possible to switch the circuit between terminals T C and T 11 or between T C and T 21 without breaking the circuit, it is possible to operate as a changeover switch, so communication using digital signals is possible. It is suitable for switching lines.
第７図は２回路の切換を行うように構成した場合であ
るが、ｎ回路の切換を行い得るように構成し得ること勿
論である。Although FIG. 7 shows a case in which two circuits are switched, it is needless to say that the circuit can be switched in n circuits.
以上何れの実施例においても、各ピンダイオードの極
性を反転せしめると共に、パイアス電圧の極性を反転せ
しめた場合にも本発明を実施することが出来る。In any of the above embodiments, the present invention can be implemented even when the polarities of the pin diodes are reversed and the polarities of the bias voltage are reversed.
発明の効果 第３図に示した基本等価回路の基本マトリクス、即
ち、第１図に示した本発明高周波減衰回路の基本マトリ
クスは、 但し、 RHS0＝RHS／Z0 RHP0＝RHP／Z0 Z0：回路の特性インピーダンス 回路の減衰量LdBは、（11）式における４定数Ａ、
Ｂ、Ｃ及びＤから次式で求めることが出来る。The basic matrix of the basic equivalent circuit shown in FIG. 3, that is, the basic matrix of the high frequency attenuation circuit of the present invention shown in FIG. However, R HS0 = R HS / Z 0 R HP0 = R HP / Z 0 Z 0 : Characteristic impedance of the circuit The attenuation LdB of the circuit is 4 constants A in the equation (11),
It can be calculated from B, C and D by the following equation.
次に、数値計算例を示すと、 低減衰領域においては、 RHS ＝１Ω RHP ＝5000Ω 回路の特性インピーダンスを、Z0＝50Ωとすると、 RHS0＝1/50＝0.02 RHP0＝5000/50＝100 回路の減衰量LMINdBは、 中程度の減衰領域における一例においては、 RHS ＝100Ω RHP ＝100Ω RHS0＝100/50＝２ RHP0＝100/50＝２ 回路の減衰量LMEDdBは、 高減衰領域においては、 RHS ＝5000Ω RHP ＝１Ω RHS0＝5000/50＝100 RHP0＝1/50＝0.02 回路の減衰量LMAXdBは、 以上の数値を従来の回路の減衰量、即ち、（２）式及
び（４）式の値と比較すると、低減衰領域においては、
本発明回路は第９図に示した従来の回路よりも僅かに劣
るが、高減衰領域においては、本発明回路の方が減衰量
が遥かに大である。 Next, as an example of numerical calculation, in the low attenuation region, assuming that the characteristic impedance of the R HS = 1Ω R HP = 5000Ω circuit is Z 0 = 50Ω, R HS0 = 1/50 = 0.02 R HP0 = 5000 / 50 = 100 circuit attenuation L MIN dB is In one example in the medium attenuation region, R HS = 100Ω R HP = 100Ω R HS0 = 100/50 = 2 R HP0 = 100/50 = 2 The circuit attenuation L MED dB is In the high attenuation region, R HS = 5000Ω R HP = 1Ω R HS0 = 5000/50 = 100 R HP0 = 1/50 = 0.02 The circuit attenuation L MAX dB is Comparing the above numerical values with the attenuation amount of the conventional circuit, that is, the values of the equations (2) and (4), in the low attenuation region,
The circuit of the present invention is slightly inferior to the conventional circuit shown in FIG. 9, but in the high attenuation region, the circuit of the present invention has a much larger amount of attenuation.
又、第11図に示した従来の回路と比較すると、低減衰
領域においては本発明回路が優れ、高減衰領域において
は本発明回路は従来の回路に比し、ほぼ6dB近く劣って
いるが、第11図に示した従来の回路においては、λ/4線
路より成る位相回路を用いており、この位相回路は一般
に帯域が狭いため、位相回路の作用が及ばない周波数に
おいては減衰量が40dB程度となり、本発明回路より遥か
に劣ることとなる。Further, as compared with the conventional circuit shown in FIG. 11, the circuit of the present invention is excellent in the low attenuation region, and in the high attenuation region, the circuit of the present invention is inferior to the conventional circuit by almost 6 dB, The conventional circuit shown in Fig. 11 uses a phase circuit consisting of a λ / 4 line. Since this phase circuit generally has a narrow band, the amount of attenuation is about 40 dB at frequencies where the phase circuit does not work. Therefore, the circuit of the present invention is far inferior.
これに対して本発明回路においては、従来の回路のよ
うに位相回路等の周波数特性を有する素子を全く含まな
いから高周波減衰回路又は高周波切換回路として広帯域
に亙って良好な減衰特性を呈する。On the other hand, in the circuit of the present invention, unlike the conventional circuit, since it does not include any element having frequency characteristics such as a phase circuit, it exhibits a good attenuation characteristic over a wide band as a high frequency attenuation circuit or a high frequency switching circuit.
第８図は、第１図及び第７図に示した本発明回路の減
衰特性の一例を示す曲線図で、横軸は電流制限抵抗R2と
R1との比R2／R1又は電流制限抵抗R12とR11との比R12／R
11、縦軸は減衰量LdBで、図から明らかなように、電流
制限抵抗R2とR1との比又はR12とR11との比を大ならしめ
ると、ほぼこれに比例して減衰量が大となるが、従来の
回路においては広帯域に亙ってこのような減衰量を得る
ことが不可能なこと前述のとおりである。FIG. 8 is a curve diagram showing an example of the attenuation characteristic of the circuit of the present invention shown in FIGS. 1 and 7, and the horizontal axis is the current limiting resistance R 2 and
The ratio R 12 / R of the ratio R 2 / R 1 or current limiting resistor R 12 and R 11 with R 1
11 , the vertical axis is the attenuation amount LdB, and as is clear from the figure, when the ratio of the current limiting resistors R 2 and R 1 or the ratio of R 12 and R 11 is increased, the attenuation is almost proportional to this. As described above, it is impossible to obtain such an attenuation amount over a wide band in the conventional circuit although the amount is large.
又、特に本発明回路を以て切換回路を構成した場合に
は、各構成単位回路毎にバイアス電圧印加端子を設ける
必要なく共通の端子を介して各構成単位回路に所要のバ
イアス電圧を加え得るからそれだけ回路構成を簡潔なら
しめ得る。Further, particularly when the switching circuit is configured by the circuit of the present invention, it is possible to apply a required bias voltage to each constituent unit circuit through a common terminal without providing a bias voltage application terminal for each constituent unit circuit. The circuit configuration can be simple.
第１図及び第５図乃至第７図は、本発明の一実施例を示
す結線図、第２図乃至第４図は本発明回路の作動説明の
ための等価回路図、第８図は本発明回路の減衰特性の一
例を示す曲線図、第９図乃至第12図は、従来の回路を示
す結線図で、D1、D2、D11、D12、D21、D22、Dn1、Dn2、
D111、D112、D211及びD212：ピンダイオード、C1、C2、
C11、C12、C21、C22、Cn1及びCn2：直流阻止コンデン
サ、L1、L2、L11、L12、L21、L22、Ln1及びLn2：高周波
阻止コイル、C3乃至C5、C13乃至C15、C23乃至C25、Cn3
乃至Cn5：高周波バイパスコンデンサ、R1乃至R4、R11乃
至R14、R21乃至R24、Rn1乃至Rn4：電流制限抵抗、T1、T
2、T11、T21、Tn1、T12及びT22：入出力端子、T3、
T13、T23：バイアス電圧印加端子、TC：共通入出力端
子、CC：共通高周波結合コンデンサ、LC：共通高周波阻
止コイル、SDC：直流電源、SW、SW1、SW2及びSWn：開閉
スイッチ、RV12及びRV22：可変抵抗である。1 and 5 to 7 are wiring diagrams showing an embodiment of the present invention, FIGS. 2 to 4 are equivalent circuit diagrams for explaining the operation of the circuit of the present invention, and FIG. 8 is a book. A curve diagram showing an example of the attenuation characteristic of the inventive circuit, and FIGS. 9 to 12 are connection diagrams showing the conventional circuit, which are D 1 , D 2 , D 11 , D 12 , D 21 , D 22 , D n1. , D n2 ,
D 111 , D 112 , D 211 and D 212 : Pin diode, C 1 , C 2 ,
C 11 , C 12 , C 21 , C 22 , C n1 and C n2 : DC blocking capacitors, L 1 , L 2 , L 11 , L 12 , L 21 , L 22 , L n1 and L n2 : High frequency blocking coil, C 3 to C 5 , C 13 to C 15 , C 23 to C 25 , C n3
To C n5 : high frequency bypass capacitors, R 1 to R 4 , R 11 to R 14 , R 21 to R 24 , R n1 to R n4 : current limiting resistors, T 1 , T
2 , T 11 , T 21 , T n1 , T 12 and T 22 : input / output terminals, T 3 ,
T 13 , T 23 : Bias voltage applying terminal, T C : Common input / output terminal, C C : Common high frequency coupling capacitor, L C : Common high frequency blocking coil, S DC : DC power supply, SW, SW 1 , SW 2 and SW n : open / close switch, R V12 and R V22 : variable resistors.
Claims (8)
端が接続される第１の電流制限抵抗と、 前記第１のピンダイオードのアノード回路に一端が接続
される第２の電流制限抵抗と、 前記第１の電流制限抵抗の他端に一端が接続される第３
の電流制限抵抗と、 前記第２の電流制限抵抗の他端と前記第３の電流制限抵
抗の他端との間に挿入接続されて、前記第１のピンダイ
オード及び前記第１乃至第３の電流制限抵抗と共にブリ
ッジ回路を形成する第４の電流制限抵抗と、 前記第１のピンダイオードのカソードにカソードが接続
され、前記第３及び第４の電流制限抵抗の接続点にアノ
ードが接続される第２のピンダイオードと、 前記第１及び第３の電流制限抵抗の接続点側を正側とし
て、この接続点と、前記第２及び第４の電流制限抵抗の
接続点との間に正バイアス電圧を加える回路と、 前記第２のピンダイオードのアノードに接続される高周
波バイパスコンデンサと、 前記第１のピンダイオードのカソード回路に接続される
入力（又は出力）端子と、 前記第１のピンダイオードのアノード回路に接続される
出力（又は入力）端子とを備えたことを特徴とする高周
波減衰回路。1. A first current limiting resistor whose one end is connected to a cathode circuit of a first pin diode, and a second current limiting resistor whose one end is connected to an anode circuit of the first pin diode. A third end, one end of which is connected to the other end of the first current limiting resistor
Of the current limiting resistor and the other end of the second current limiting resistor and the other end of the third current limiting resistor are inserted and connected, and the first pin diode and the first to third A fourth current limiting resistor forming a bridge circuit with a current limiting resistor, a cathode of the first pin diode is connected to a cathode, and an anode is connected to a connection point of the third and fourth current limiting resistors. The second pin diode and the connection point side of the first and third current limiting resistors are positive sides, and a positive bias is applied between this connection point and the connection points of the second and fourth current limiting resistors. A circuit for applying a voltage, a high-frequency bypass capacitor connected to the anode of the second pin diode, an input (or output) terminal connected to the cathode circuit of the first pin diode, and the first pin diode. High frequency attenuation circuit, characterized in that an output (or input) terminal connected to the anode circuit.
反転せしめると共に、バイアス電圧の極性を反転せしめ
て成る特許請求の範囲第１項記載の高周波減衰回路。2. The high frequency attenuating circuit according to claim 1, wherein the polarities of the first and second pin diodes are reversed and the polarities of the bias voltages are reversed.
許請求の範囲第１項記載の高周波減衰回路。3. A high frequency attenuating circuit according to claim 1, wherein the second current limiting resistor is a variable resistor.
ッチの直列回路で置き換えられて成る特許請求の範囲第
１項記載の高周波減衰回路。4. A high frequency attenuating circuit according to claim 1, wherein the second current limiting resistor is replaced by a series circuit of a fixed resistor and an open / close switch.
端が接続される第１の電流制限抵抗と、 前記第１のピンダイオードのアノード回路に一端が接続
される第２の電流制限抵抗と、 前記第１の電流制限抵抗の他端に一端が接続される第３
の電流制限抵抗と、 前記第２の電流制限抵抗の他端と前記第３の電流制限抵
抗の他端との間に挿入接続されて、前記第１のピンダイ
オード及び前記第１乃至第３の電流制限抵抗と共にブリ
ッジ回路を形成する第４の電流制限抵抗と、 前記第１のピンダイオードのカソードにカソードが接続
され、前記第３及び第４の電流制限抵抗の接続点にアノ
ードが接続される第２のピンダイオードと、 前記第２のピンダイオードのアノード回路に接続される
高周波バイパスコンデンサと、 前記第１のピンダイオードのアノードを出力（又は入
力）端子に接続する回路とを備えた任意複数個の高周波
減衰回路と、 前記任意複数個の高周波減衰回路のそれぞれを形成する
前記第１及び第３の電流制限抵抗の接続点側を正側とし
て、この接続点と、前記第２及び第４の電流制限抵抗の
接続点との間に共通の正バイアス電圧を加える回路と、 前記任意複数個の高周波減衰回路のそれぞれを形成する
前記第１のピンダイオードのカソードを共通の入力（又
は出力）端子に接続する回路とを備えたことを特徴とす
る高周波減衰回路より成る高周波切換回路。5. A first current limiting resistor whose one end is connected to the cathode circuit of the first pin diode, and a second current limiting resistor whose one end is connected to the anode circuit of the first pin diode. A third end, one end of which is connected to the other end of the first current limiting resistor
Of the current limiting resistor and the other end of the second current limiting resistor and the other end of the third current limiting resistor are inserted and connected, and the first pin diode and the first to third A fourth current limiting resistor forming a bridge circuit with a current limiting resistor, a cathode of the first pin diode is connected to a cathode, and an anode is connected to a connection point of the third and fourth current limiting resistors. Arbitrary plurality including a second pin diode, a high frequency bypass capacitor connected to the anode circuit of the second pin diode, and a circuit connecting the anode of the first pin diode to an output (or input) terminal. A high frequency attenuator circuit and a connection point side of the first and third current limiting resistors forming each of the arbitrary plurality of high frequency attenuator circuits are defined as a positive side, and this connection point and the second And a connection point of the fourth current limiting resistor with a circuit for applying a common positive bias voltage, and a cathode of the first pin diode forming each of the arbitrary plurality of high frequency attenuating circuits, with a common input ( Or a circuit connected to an output terminal, the high-frequency switching circuit comprising a high-frequency attenuation circuit.
形成する第１及び第２のピンダイオードの各極性を反転
せしめると共に、共通のバイアス電圧の極性を反転せし
めて成る特許請求の範囲第５項記載の高周波減衰回路よ
り成る高周波切換回路。6. The invention according to claim 5, wherein the polarities of the first and second pin diodes forming each of the arbitrary plurality of high frequency attenuating circuits are reversed, and the polarities of the common bias voltage are reversed. A high frequency switching circuit comprising the high frequency attenuating circuit according to the item.
形成する第２の電流制限抵抗が可変抵抗より成る特許請
求の範囲第５項記載の高周波減衰回路より成る高周波切
換回路。7. A high frequency switching circuit comprising the high frequency attenuation circuit according to claim 5, wherein the second current limiting resistor forming each of the arbitrary plurality of high frequency attenuation circuits is a variable resistor.
形成する第２の電流制限抵抗が固定抵抗と開閉スイッチ
の直列回路で置き換えられて成る特許請求の範囲第５項
記載の高周波減衰回路より成る高周波切換回路。8. The high frequency attenuating circuit according to claim 5, wherein the second current limiting resistor forming each of the arbitrary plurality of high frequency attenuating circuits is replaced with a series circuit of a fixed resistor and an opening / closing switch. High frequency switching circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61081907A JPH084209B2 (en) | 1986-04-08 | 1986-04-08 | High frequency attenuating circuit and high frequency switching circuit including high frequency attenuating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61081907A JPH084209B2 (en) | 1986-04-08 | 1986-04-08 | High frequency attenuating circuit and high frequency switching circuit including high frequency attenuating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62237807A JPS62237807A (en) | 1987-10-17 |
| JPH084209B2 true JPH084209B2 (en) | 1996-01-17 |
Family
ID=13759514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61081907A Expired - Lifetime JPH084209B2 (en) | 1986-04-08 | 1986-04-08 | High frequency attenuating circuit and high frequency switching circuit including high frequency attenuating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH084209B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103873158B (en) * | 2012-12-10 | 2017-08-25 | 北京普源精电科技有限公司 | A kind of radio-frequency measurement device with variable attenuator |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53100757A (en) * | 1977-02-15 | 1978-09-02 | Oki Electric Ind Co Ltd | Super-high frequency semiconductor device |
-
1986
- 1986-04-08 JP JP61081907A patent/JPH084209B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62237807A (en) | 1987-10-17 |
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