JPH0834278B2 - Semiconductor chip carrier device - Google Patents

Semiconductor chip carrier device

Info

Publication number
JPH0834278B2
JPH0834278B2 JP62256144A JP25614487A JPH0834278B2 JP H0834278 B2 JPH0834278 B2 JP H0834278B2 JP 62256144 A JP62256144 A JP 62256144A JP 25614487 A JP25614487 A JP 25614487A JP H0834278 B2 JPH0834278 B2 JP H0834278B2
Authority
JP
Japan
Prior art keywords
chip carrier
substrate
housing
chip
carrier substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62256144A
Other languages
Japanese (ja)
Other versions
JPH01102952A (en
Inventor
ジー グラッベ ディミトリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TE Connectivity Corp
Original Assignee
AMP Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AMP Inc filed Critical AMP Inc
Publication of JPH01102952A publication Critical patent/JPH01102952A/en
Publication of JPH0834278B2 publication Critical patent/JPH0834278B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体チップキャリヤー装置、特に色々の温
度並びに応力の環境下において外部回路に半導体チップ
を確実に電気的に接続できる半導体チップキャリヤー装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip carrier device, and more particularly to a semiconductor chip carrier device capable of reliably electrically connecting a semiconductor chip to an external circuit under various temperature and stress environments. .

（従来の技術とその問題点） 集積回路半導体チップは大きさが小さいことと脆い性
質を有するので通常集積回路チップキャリヤーに梱包さ
れている。チップキャリヤーは通常集積回路を取付けた
セラミックその他の剛性絶縁材料からなる基板を包含し
且つ前記基板は前記チップの近くから該基板の周囲に延
在して拡大コンタクト域又はコンタクトパッドで終端さ
れる複数本のコンダクターを含んでいる。(Prior Art and Its Problems) Integrated circuit semiconductor chips are usually packaged in integrated circuit chip carriers because of their small size and fragile nature. The chip carrier typically includes a substrate of ceramic or other rigid insulating material on which the integrated circuit is mounted, and the substrates extend from near the chip to the periphery of the substrate and terminate in extended contact areas or contact pads. Contains the book conductor.

しばしば、マルチチップキャリヤー基板はそれとその
上のチップを防護し且つ支持するフレーム又はハウジン
グ内に内包され、且つ前記基板を印刷回路盤またはその
他の外部回路に電気的に接続するためのコネクタを提供
する。一般に、前記フレームまたはハウジングは複数本
のリードを含んでいる。前記各リードの一端は基板のコ
ンタクトパッドの１つに電気的に接続されるためハウジ
ングの中に延び、且つ前記各リードの他端はハウジング
が延出して印刷回路盤のコンタクトに直接またはソケッ
トコネクタを通じて接続される。Often, a multi-chip carrier substrate is enclosed within a frame or housing that protects and supports it and the chips thereon, and provides a connector for electrically connecting the substrate to a printed circuit board or other external circuit. . Generally, the frame or housing includes a plurality of leads. One end of each lead extends into the housing for electrical connection to one of the contact pads on the board, and the other end of each lead extends into the housing to directly or contact a contact of a printed circuit board. Be connected through.

従来、集積回路半導体チップキャリヤー装置は集積回
路チップを取付けるセラミックその他の非可撓性材料か
らなる剛性基板を包含することを特徴としている。前記
剛性セラミック基板はその中に埋め込まれたコンダクタ
ー（多層コーファヤードセラミック基板）、また該基板
の表面に積層されたコンダクター（薄いかまたは厚い膜
のセラミック基板）を備えている。或る場合に、前記コ
ンダクターは基板の表面に均一に付着された膜に含まれ
た。チップから基板のコンダクターへの電気的接続並び
に基板のコンダクターからハウジングリードへの電気的
接続は金やアルミニウムのボンドワイヤーによって行わ
れ、装置の各種部品の熱膨張や収縮における変化と物理
的歪みを補償し、且つ半導体チップと基板の間に接続を
行う。しかしながら、このような接続は製作が高価であ
り且つ完全に満足とは認められなかった。Traditionally, integrated circuit semiconductor chip carrier devices have been characterized by including a rigid substrate of ceramic or other non-flexible material on which the integrated circuit chip is mounted. The rigid ceramic substrate comprises conductors embedded therein (multi-layer co-fabric ceramic substrate) and conductors (thin or thick film ceramic substrate) laminated on the surface of the substrate. In some cases, the conductors were included in a film that was uniformly deposited on the surface of the substrate. Electrical connections from the chip to the board conductors and from the board conductors to the housing leads are made with gold and aluminum bond wires to compensate for changes and physical distortions in the thermal expansion and contraction of various parts of the device. Then, a connection is made between the semiconductor chip and the substrate. However, such connections are expensive to manufacture and have not been found entirely satisfactory.

また、従来の半導体チップキャリヤー装置はハウジン
グを密封するためにハウジングとそこを貫通するリード
との間を密封するためガラスシートを含んだ大体剛性の
あるハウジング構造体を備えていた。また、このような
装置はハウジング部品の温度膨張及び収縮の変化とその
他外部応力の結果として密封性を維持することの困難性
の故に、またこのような構造物が非常に高価である故
に、完全に満足ではなかった。In addition, the conventional semiconductor chip carrier device has a generally rigid housing structure including a glass sheet for sealing between the housing and leads extending therethrough to seal the housing. Also, such a device is not fully integrated due to the difficulty of maintaining a hermetic seal as a result of changes in housing component thermal expansion and contraction and other external stresses, and because such structures are very expensive. Was not satisfied with.

また、従来の多くの半導体マルチチップキャリヤー装
置は大きさを制限されてきた。特に、従来のセラミック
基板の製造法は約２インチ×２インチ（50.8mm×50.8m
m）以上の大きさの充分偏平な基板を作ることができな
かった。これはファイヤリング作業中にセラミックの寸
法上の安全性を維持することが困難なことに基因してい
る。Also, many conventional semiconductor multi-chip carrier devices have been limited in size. In particular, the conventional ceramic substrate manufacturing method is about 2 inches x 2 inches (50.8 mm x 50.8 m
It was not possible to make a sufficiently flat substrate with a size of m) or more. This is due to the difficulty in maintaining the dimensional safety of the ceramic during the firing operation.

（問題点を解決するための手段） 本発明は使用が容易で低廉であり、且つ色々の温度と
応力の状態で１個以上の半導体チップを外部回路に確実
に相互接続できる集積回路半導体チップを提供する。本
発明の装置はそのハウジングに介在する小さな部分以外
は殆んど全体が非剛性で可撓性であるコンダクター装置
を含んでいる。本発明の好適な実施例はハウジングと基
板上の１個以上の半導体チップと、前記ハウジングの１
個以上の壁に支持される第１部分を有し且つ基板に接続
するためハウジングから内方へ延び且つ外部回路へと外
方へ延びる実質的に非剛性で柔軟な部分を有する複数本
の可撓性コンダクター装置を包含する。前記可撓性コン
ダクター装置は数が1800種類でありまた間隔が0.010イ
ンチ（0.0254mm）程度である。(Means for Solving Problems) The present invention provides an integrated circuit semiconductor chip which is easy and inexpensive to use, and which can reliably interconnect one or more semiconductor chips to an external circuit under various temperature and stress conditions. provide. The device of the present invention includes a conductor device that is almost non-rigid and flexible except for a small portion interposed in its housing. A preferred embodiment of the present invention includes a housing, one or more semiconductor chips on a substrate, and one of the housings.
A plurality of flexible members having a first portion supported by one or more walls and having a substantially non-rigid flexible portion extending inwardly from the housing for connecting to the substrate and outwardly to an external circuit. Includes a flexible conductor device. The number of flexible conductor devices is 1800 and the intervals are about 0.010 inch (0.0254 mm).

基板上のチップ間の相互接続は厚い膜、薄い膜、コー
ファイヤード、プレーテッド コンダクターのような中
間装置において作ることができる。また、相互接続を新
らしい装置で作っても良く、その場合にチップとチップ
の接続用ネットを少くとも１つの層に、或る場合には
“マイクロストリップ”状又は“ストリップーライン”
状に配置した45層のような多層に配置した薄い可撓性の
コンダクターを含む有機性材料で作る。すべての場合に
相互接続用ネットの集積回路に窓が設けられる。相互接
続用ネットは基板の全面に取付けられなくて、或る点の
みに取付けて、基板と相互接続用ネットを温度変化の結
果それぞれの膨脹係数に応じてそれぞれ別々に膨脹又は
収縮せしめる。これが一般に“バイーメタル”効果と称
されているカップリングの有害な干渉を排除する。この
ようにして本発明は従来さけることのできなかった装置
の歪と応力を排除した電気的接続を行う。Interconnects between chips on a substrate can be made in intermediate devices such as thick films, thin films, co-yards and plated conductors. Also, interconnections may be made with new equipment, in which case the chip-to-chip connecting nets are in at least one layer, in some cases "microstrip" or "strip-line".
It is made of an organic material containing thin flexible conductors arranged in multiple layers, such as 45 layers arranged in a pattern. In all cases a window is provided in the integrated circuit of the interconnection net. The interconnecting net is not attached to the entire surface of the substrate, but only at certain points to cause the substrate and the interconnecting net to expand or contract separately depending on their respective expansion coefficients as a result of temperature changes. This eliminates the detrimental interference of the coupling, commonly referred to as the "bimetal" effect. In this way, the present invention provides an electrical connection that eliminates strain and stress in the device, which could not be avoided in the past.

好適な実施例において、前記半導体チップキャリヤー
装置は１個又はそれ以上の周囲壁を貫いて延びる複数個
のリードを有する大体矩形のハウジングを包含する。前
記リードはハウジング壁に埋めた中央部分と、ハウジン
グの外側に延びて外部回路に電気的に接続されるように
なった外側の柔軟部分と、ハウジングの中に含まれるチ
ップキャリヤー基板上のコンタクトパッドに電気的に接
続されるようになった内側の柔軟部分とを包含する。チ
ップキャリヤー基板は電気的に取付けられているチップ
キャリヤーに配置された複数個の半導体チップを担持す
るようになった例えばセラミックや金属のような剛性材
料で作る。チップキャリヤー基板はハウジングの壁に固
定されている。なるべく薄く可撓性のあるプラスチック
膜を含む電気接続部材またはネットは、複数個のチップ
を電気的に相互接続するため、並びに膜の周囲に置いた
パッドをフレームの内側リードに接続するため複数個の
可撓性のコンダクターを含み且つ支持している。前記膜
は或る点において機械的に保持されて前記膜の基板に対
する横方向の移動を制限しているが、一般に基板の殆ん
ど全域から取り外されて前記膜と基板が互いに別々に撓
み歪ませるようになっている。In a preferred embodiment, the semiconductor chip carrier device includes a generally rectangular housing having a plurality of leads extending through one or more peripheral walls. The lead is a central portion embedded in a housing wall, an outer flexible portion extending outside the housing to be electrically connected to an external circuit, and a contact pad on a chip carrier substrate included in the housing. An inner flexible portion adapted to be electrically connected to. The chip carrier substrate is made of a rigid material, such as ceramic or metal, adapted to carry a plurality of semiconductor chips arranged on an electrically attached chip carrier. The chip carrier substrate is fixed to the wall of the housing. An electrical connection member or net including a plastic film that is as thin and flexible as possible is used to electrically connect a plurality of chips and to connect a pad placed around the film to an inner lead of a frame. Of flexible conductors. Although the membrane is mechanically held at some point to limit lateral movement of the membrane relative to the substrate, it is generally removed from almost all of the substrate to cause the membrane and substrate to flex independently of each other. It seems to be.

前記リードはハウジングにより支持され且つチップキ
ャリヤーのコンダクターは殆んど非剛性で柔軟であり且
つ温度変化及びその他のストレスにより生じた装置部品
の変形を許すことができるので、リードと膜の可撓性コ
ンダクターの間及び基板絶縁パッドとフレームリードの
間の中間のワイヤーボンド接続を省略することができ
る。本発明の多くの実施例において、リードは直接チッ
プキャリヤー基板のコンタクトパッドに接続することが
でき、且つチップのターミナル域はもっと効果的なテー
プ自動式接着法によりまた標準のワイヤーボンドにより
膜コンダクターに接続できる。The leads and the membrane are flexible because the leads are supported by the housing and the conductors of the chip carrier are almost non-rigid and flexible and can allow deformation of device components caused by temperature changes and other stresses. Intermediate wire bond connections between conductors and between substrate isolation pads and frame leads can be omitted. In many embodiments of the invention, the leads can be connected directly to the contact pads of the chip carrier substrate, and the terminal area of the chip is more effective with tape automated bonding and with standard wire bonds to the membrane conductor. Can be connected.

前記装置は集積回路を湿気から防護するため、またチ
ップの環境防護を提供するため防護用ジェリー状コンパ
ウンドを部分的に満たした囲繞ハウジングを提供する。
前記ハウジングのチップキャリヤー基板の反対側は金属
その他の材料のカバーで閉ざされて構造上の防護を行っ
ている。The device provides an enclosure housing that is partially filled with a protective jelly-like compound to protect the integrated circuit from moisture and to provide environmental protection for the chip.
The opposite side of the chip carrier substrate of the housing is closed by a metal or other material cover to provide structural protection.

本発明において、チップキャリヤー基板の電気的相互
接続部材またはネットは実質的に剛性基板から分離でき
る。したがって、特殊な応用分野に対し剛性基板の構造
上並びに温度特性を最高にし且つ同時にコンダクターの
送電線特性を最適化するようチップキャリヤーを設計す
るに当り大なる融通性が得られる。例えば、本発明にお
いて剛性基板を特殊な応用分野に対し必要に応じ高熱伝
導性を有する金属その他の材料で作ることができる。更
に、電気接続部材をチップキャリヤー基板のチップ支持
基板から分離できるので、偏平でなく曲った表面を相互
接続用ネットに許容することができ、且つこのようにし
て基板をもつと大きな寸法、例えば６インチ×６インチ
（15.2cm×15.2cm）以上広く作ることができ。且つ単一
のチップキャリヤー基板に多くの半導体チップを収容す
ることができる。また、コンダクターを多層可撓性膜の
中に含めることによって、チップに対し必要な電気接続
を増大するため従来より以上にコンダクターの密度を大
きくすることができる。基板の毎平方インチ当り600以
上のチャンネルが必要となる。In the present invention, the electrical interconnection members or nets of the chip carrier substrate can be substantially separated from the rigid substrate. Therefore, a great deal of flexibility is gained in designing the chip carrier for the particular application fields in order to maximize the structural and temperature characteristics of the rigid substrate and at the same time optimize the transmission line characteristics of the conductor. For example, in the present invention, the rigid substrate can be made of metal or other material having high thermal conductivity as needed for a particular application. In addition, the electrical connection member can be separated from the chip carrier substrate of the chip carrier substrate so that a non-flat curved surface can be accommodated in the interconnecting net, and in this way the substrate has a large dimension, for example 6 Can be made wider than inches x 6 inches (15.2 cm x 15.2 cm). In addition, many semiconductor chips can be accommodated on a single chip carrier substrate. Also, by including conductors in the multilayer flexible membrane, the required electrical connections to the chip are increased and the conductor density can be increased more than in the prior art. Over 600 channels are required per square inch of substrate.

本発明の１つの実施例において、セラミック基板は集
積回路半導体チップを取付ける複数個のへこみを形成さ
れている。このような構造であるから、チップのターミ
ナル域をチップキャリヤー基板のコンダクターに接続す
るため短いワイヤーやテーブ自動式ボンディング法の使
用が可能となり、かくして電気抵抗とインダクタンスを
減少し且つ装置の信頼性を増大する。相互接続用ネット
における窓の中に延びたリードを設け、このようなリー
ドを直接シップに送ることができるように、相互接続用
ネットを形成し、TAB（テープ自動式ボンディング）や
ワイヤーボンドの中間接続の必要性を無くす。本発明の
別の実施例において、前記チップキャリヤー基板を金属
で作ることができる。チップを基板上に一層正確に位置
決めするため該チップを該基板に形成したペデスタイル
に取付けることができる。In one embodiment of the present invention, the ceramic substrate is formed with a plurality of indentations for mounting integrated circuit semiconductor chips. Due to this structure, it is possible to use short wire or tape automatic bonding method to connect the terminal area of the chip to the conductor of the chip carrier substrate, thus reducing the electrical resistance and inductance and reducing the reliability of the device. Increase. Provide a lead that extends into the window of the interconnection net and form the interconnection net so that these leads can be sent directly to the ship, intermediate TAB (tape automated bonding) or wire bond Eliminates the need for connections. In another embodiment of the invention, the chip carrier substrate can be made of metal. To more accurately position the chip on the substrate, the chip can be mounted on a pedestal formed on the substrate.

本発明において、個々の半導体チップを色々の工法に
よりチップキャリヤー基板に取付けることができる。例
えば、チップを“フリップチップ”取付け構造及びモジ
ュールスプリング取付け構造を使用して基板に取付ける
ことができるのでチップキャリヤーの設計に大きな融通
性を与える。このような取付法は誘電率１〜６を有し且
つ“アズファヤード”状態における５ミクロンインチ表
面仕上げ以上の良好な仕上げを有するセラミック基板を
使用して、基板上に支持された複数個のチップの間に必
要な相互接続用ネットワークを提供できる多数層の有機
性コンパウンドを支持することができる。In the present invention, individual semiconductor chips can be attached to the chip carrier substrate by various methods. For example, the chips can be mounted to the substrate using "flip chip" mounting structures and module spring mounting structures, thus providing great flexibility in the design of the chip carrier. Such a mounting method uses a ceramic substrate having a dielectric constant of 1 to 6 and a good finish of 5 micron inch surface finish or more in the "as far yard" state, and a plurality of chips supported on the substrate are mounted. It can support multiple layers of organic compounds that can provide the necessary interconnection network in between.

本発明のそれ以上の効果と詳細がここに提供した実施
例の詳細な説明に関連して以下詳しく述べられる。Further advantages and details of the invention are detailed below in connection with the detailed description of the embodiments provided herein.

（実 施 例） 第１図および第２図は本発明の半導体チップキャリヤ
ー装置の好適実施例を示す。この装置は全体を参照番号
10で示され且つハウジング11を備えている。該ハウジン
グ11は複数個の集積回路半導体チップ13を取付けたチッ
プキャリヤー基板12を収容している。ハウジング11はチ
ップキャリヤー基板12とその上のチップ13を防護し且つ
支持し、且つチップキャリヤー基板12上のチップ13を印
刷回路盤14のような外部回路に電気的に接続する。(Example) FIGS. 1 and 2 show a preferred embodiment of the semiconductor chip carrier device of the present invention. This device is referenced in its entirety
It is shown at 10 and comprises a housing 11. The housing 11 contains a chip carrier substrate 12 having a plurality of integrated circuit semiconductor chips 13 mounted thereon. The housing 11 protects and supports the chip carrier substrate 12 and the chips 13 thereon, and electrically connects the chips 13 on the chip carrier substrate 12 to an external circuit such as a printed circuit board 14.

ハウジング11は凡そ正方形または矩形の箱状構造体を
含み且つ側壁21,22,23,24とチップキャリヤー基板12が
形成する頂壁とカバー17が形成する底壁を有する周囲フ
レーム15を含んでいる。組立てたとき前記ハウジングの
壁が第２図に示すよう密閉室18を形成する。フレーム15
は頑丈であるが幾分柔軟な塑造性プラスチック（液晶ポ
リマーが特に適している）でなるべく作られ且つチップ
キャリヤー基板12とカバー17をそれぞれ収容するための
上部凹み26と下部凹み27を形成している。チップキャリ
ヤー基板12は第２図において頂板を形成するように図示
されているが、チップキャリヤー基板12とカバー板17を
第３図に示すように逆にして、チップキャリヤー基板12
が底壁を形成し且つカバー板17が頂板を形成するように
しても良い。The housing 11 comprises a generally square or rectangular box-like structure and includes a peripheral frame 15 having side walls 21, 22, 23, 24 and a top wall formed by the chip carrier substrate 12 and a bottom wall formed by a cover 17. . When assembled, the walls of the housing form a closed chamber 18 as shown in FIG. Frame 15
Is preferably made of a tough but somewhat flexible plastic (liquid crystal polymer is particularly suitable) and forms an upper recess 26 and a lower recess 27 for accommodating the chip carrier substrate 12 and the cover 17, respectively. There is. Although the chip carrier substrate 12 is shown in FIG. 2 as forming a top plate, the chip carrier substrate 12 and cover plate 17 are reversed as shown in FIG.
May form the bottom wall and the cover plate 17 may form the top plate.

チップキャリヤー基板12は、半導体チップ13が取り付
けられた一面をハウジング11の内方に向けた状態でハウ
ジング11の上部凹み26または下部凹み27のいずれにも取
り付けられるようになっているので、チップキャリヤー
基板12のハウジング11への取付作業において自由度の大
きいものとなる。The chip carrier substrate 12 is adapted to be mounted in either the upper recess 26 or the lower recess 27 of the housing 11 with one surface on which the semiconductor chip 13 is mounted facing inward of the housing 11, so that the chip carrier substrate 12 is mounted. The degree of freedom in attaching the substrate 12 to the housing 11 is high.

あとで詳細に説明するチップキャリヤー基板12は剛性
材料例えばセラミックのような偏平で比較的薄い板から
なる基板30を含んでいる。複数個の集積回路半導体チッ
プ13が当業者に周知の方法で基板30の表面35に取付けら
れている。しかしながら、後述するようにその他の取付
構造を使用しても良い。The chip carrier substrate 12, which will be described in detail below, includes a substrate 30 which is a rigid, relatively flat plate such as a ceramic. A plurality of integrated circuit semiconductor chips 13 are mounted on surface 35 of substrate 30 in a manner well known to those skilled in the art. However, other mounting structures may be used as described below.

また、チップキャリヤー基板12は複数個のチップ13を
互に接続するため並びにキャリヤー基板12の周囲の近く
に設けた複数個の接触パッド32に接続するための複数本
のコンダクター31（第１図）を備えている。周知のよう
に、コンダクター31が基板30（多層のコーファヤードセ
ラミック基板）の中に埋め込まれるか、または基板30
（薄いかまたは厚い膜状セラミック基板）の表面30に層
状に造られる。セミコンダクターチップ13のターミナル
域はゴールドワイヤーテープまたはテープ状ボンド33に
よってコンダクター31に接続される。Also, the chip carrier substrate 12 has a plurality of conductors 31 (FIG. 1) for connecting a plurality of chips 13 to each other and to a plurality of contact pads 32 provided near the periphery of the carrier substrate 12. Is equipped with. As is well known, the conductor 31 is either embedded in the substrate 30 (multi-layer coferyard ceramic substrate) or the substrate 30.
Layered on the surface 30 (thin or thick film ceramic substrate). The terminal area of the semiconductor chip 13 is connected to the conductor 31 by a gold wire tape or tape-like bond 33.

複数本の導電性リード36がフレーム15によって支持さ
れている。リード36はフレーム15の周囲に殆んど均一に
隔置され且つ例えば銅合金のような可撓性金属で作った
リボン状部材を備えている。このようにして1800本以上
の多くのリードが0.01インチ（0.254mm）の間隔で使用
される。第２図に示すように、リード36はそれぞれフレ
ーム15を貫通し且つ該フレームによって支持される中央
部分36aと、ハウジング11の中に延在する内側部分36b
と、ハウジング11の外に延在する外側部分36cとを備え
ている。リード36はなるべくリード中央部分36aの周り
にフレーム15をモールドすることにより該フレーム15に
固定される。A plurality of conductive leads 36 are supported by the frame 15. The leads 36 are substantially evenly spaced around the frame 15 and comprise ribbon-like members made of a flexible metal such as a copper alloy. In this way, more than 1800 leads are used with 0.01 inch (0.254 mm) spacing. As shown in FIG. 2, the leads 36 each extend through the frame 15 and have a central portion 36a supported by the frame and an inner portion 36b extending into the housing 11.
And an outer portion 36c extending outside the housing 11. The lead 36 is fixed to the frame 15 by molding the frame 15 around the lead central portion 36a as possible.

内側リード部分36bはフレーム15から内側に一定の距
離突出し且つ曲げられて、チップキャリヤー基板12上の
コンタクトパッド32に直接接続されるビームを形成す
る。内側リード部分36bの端部はパッド32に接触する場
所が大体偏平となるように配置されている。外側リード
部分36cはフレーム15から外方に突出し且つ印刷回路盤1
4のコンタクトパッド37（第２図参照）に直接接続され
る形状となっている。第１図および第２図の実施例にお
いて、外側リード部分36cはＪ形であるるが、例えば第
３図に示すような別の形状を使用するこもできる。The inner lead portion 36b protrudes a certain distance inward from the frame 15 and is bent to form a beam that is directly connected to the contact pad 32 on the chip carrier substrate 12. The ends of the inner lead portions 36b are arranged so that the places where they come into contact with the pads 32 are generally flat. The outer lead portion 36c projects outward from the frame 15 and is printed circuit board 1
The shape is such that it is directly connected to the fourth contact pad 37 (see FIG. 2). In the embodiment of FIGS. 1 and 2, the outer lead portion 36c is J-shaped, although other shapes, such as that shown in FIG. 3, can be used.

装置10を組立てるため、半導体チップ13を取付け且つ
コンダクター31を設けてあるチップキャリヤー基板12が
フレーム15の上部凹み26の中に配置されている。つぎに
チップキャリヤー基板12がそれとたな28との間に施され
た適当な接着剤28によってフレーム15に固定されてい
る。To assemble the device 10, the chip carrier substrate 12 with the semiconductor chip 13 attached and the conductors 31 is placed in the upper recess 26 of the frame 15. The chip carrier substrate 12 is then fixed to the frame 15 by a suitable adhesive 28 applied between it and the tray 28.

チップキャリヤー基板12をフレーム15に取付ける際
に、コンタクトパッド32がリード36の内側部分36bの端
部に整列して接触させられる。つぎに各リード部分36b
の端部が加熱加圧接着法、半田付け法、蝋付け法やその
他の適当な方法で前述の整列したコンタクトパッドに取
付けられる。第２図に半田付け部39を示す。リード部分
36bは非剛性で柔軟性を有するので、中間の接続部を使
用しなくて、直接コンタクトパッド32に接続することが
できる。熱膨脹並びに熱収縮または機械的な応力によっ
て発生したチップキャリヤー基板12またはハウジング11
の歪みや曲がりはリード部分36bの弾力性によって許容
され、その結果信頼性の高い接続がリード36とコンタク
トパッド32の間に確保される。When mounting the chip carrier substrate 12 to the frame 15, the contact pads 32 are aligned and contact the ends of the inner portions 36b of the leads 36. Next, each lead part 36b
The ends are attached to the aligned contact pads by heat and pressure bonding, soldering, brazing, or any other suitable method. FIG. 2 shows the soldering part 39. Lead part
Since 36b is non-rigid and flexible, it can be directly connected to the contact pad 32 without using an intermediate connecting portion. Chip carrier substrate 12 or housing 11 generated by thermal expansion and contraction or mechanical stress
Distortion or bending is allowed by the elasticity of the lead portion 36b, so that a reliable connection is secured between the lead 36 and the contact pad 32.

組立てを一部分完成したハウジングをつぎに裏返えし
且つ室18の一部分又は全部にコンパウンド例えばポリジ
メチルシロキシン（第２図に40で示す）を注入して、チ
ップキャリヤー基板12と半導体チップに対し湿気と環境
の防護を与える。つぎに、金属製またはその他の材料で
作ったカバー17をフレーム15の下部凹み27の中に取付け
且つカバー17とたな29の間に接着剤41を施すことによっ
て該下部凹み27に接着するかまたは機械的に取付ける。The partially assembled housing is then flipped over and a portion of or the entire chamber 18 is filled with a compound such as polydimethyl thyroxine (shown at 40 in FIG. 2) to wet the chip carrier substrate 12 and the semiconductor chip. And give environmental protection. Next, a cover 17 made of metal or other material is attached to the lower recess 27 by mounting it in the lower recess 27 of the frame 15 and applying an adhesive 41 between the cover 17 and the rack 29. Or mechanically install.

組立てたとき前記ハウジング11はチップキャリヤー基
板12と該基板上の傷つき易い半導体チップ13を密閉シー
ルを施さずに確実に防護することができる完全囲繞コン
テーナーを包含する。リード36は柔軟性があるので破か
いや割れを発生ずに一定限曲げたり撓わませることがで
き、したがって熱応力と機械的応力のもとでハウジング
の形状を保つことができる。When assembled, the housing 11 contains a chip carrier substrate 12 and a fully enclosed container which can securely protect the vulnerable semiconductor chip 13 on the substrate without providing a hermetic seal. The flexibility of the leads 36 allows them to be bent or flexed to a certain extent without breaking or cracking, thus maintaining the shape of the housing under thermal and mechanical stress.

組立作業に続いて装置10を使用のためまたは試験のた
め印刷回路盤14やその他の外部回路に接続する。第２図
に示すように、リード36の外側部分36cは印刷回路盤14
のコンタクトパッド37にのせられ、そこに導電性半田43
によって直接接続されて、チップキャリヤー基板12とそ
の上の半導体チップ13を印刷回路盤に電気的に接続す
る。Following the assembly operation, device 10 is connected to printed circuit board 14 or other external circuitry for use or testing. As shown in FIG. 2, the outer portion 36c of the lead 36 is the printed circuit board 14
Placed on the contact pad 37 of the
To directly connect the chip carrier substrate 12 and the semiconductor chip 13 thereon to the printed circuit board.

第３図は本発明の数種の実施例を示す。例えば第３図
においてリード56は印刷回路盤14のコンタクトパッド37
に直接接続するためかもめの羽根の形状をした外側部分
56c（実線部分）を含んでいる。リード56の内側部分56b
は第１図及び第２図の実施例の中より幾分長い距離ハウ
ジング11の中に延在して該リード部分に大きな可撓性を
与えるような形状をしている。第３図に点線で示すよう
に、またリード56は印刷回路盤14にソケット接続できる
よう偏平な外側リード部分56dを設けることもできる。
これらの例は説明上のものであって、リード56の外側部
分をこれら図示の形状に限定しようとする考えはない。FIG. 3 shows several embodiments of the present invention. For example, in FIG. 3, the lead 56 is the contact pad 37 of the printed circuit board 14.
Outer part in the shape of a seagull wing for direct connection to
Includes 56c (solid line). Inner portion 56b of lead 56
Is shaped to extend into the housing 11 a somewhat longer distance than in the embodiment of FIGS. 1 and 2 to provide greater flexibility to the lead portion. As shown by the dotted lines in FIG. 3, the leads 56 may also be provided with flat outer lead portions 56d for socket connection to the printed circuit board 14.
These examples are illustrative and there is no intention to limit the outer portion of the lead 56 to the shapes shown.

第３図の実施例において、防護用コンパウンド40とカ
バー17を、半導体チップ13のそれぞれを外部環境から密
閉するための分離状のキャップ61ととりかえている。キ
ャップ61はセラミックやその他の適当な材料で作り且つ
半導体チップ13を完全に囲繞する形状にすることができ
る。キャップ61はチップを囲繞して収容するようにチッ
プキャリヤー12aの基板30に接着されて外部環境からチ
ップを防護する。このようなキャップが使用されると
き、相互連結装置はキャップの下に延長するコンダクタ
ー部分62を含んでいる。この明細書の中に参考のため含
まれている米国特許第4,426,769号に適当な密封用キャ
ップが図示且つ説明されており、これについて詳細に説
明する必要がない。In the embodiment shown in FIG. 3, the protective compound 40 and the cover 17 are replaced with a separate cap 61 for sealing each of the semiconductor chips 13 from the external environment. The cap 61 can be made of ceramic or other suitable material and can be shaped to completely surround the semiconductor chip 13. The cap 61 is adhered to the substrate 30 of the chip carrier 12a so as to surround and accommodate the chip, and protects the chip from the external environment. When such a cap is used, the interconnection device includes a conductor portion 62 that extends under the cap. A suitable sealing cap is shown and described in U.S. Pat. No. 4,426,769, which is incorporated herein by reference, and need not be described in detail.

第4A図と第5A図は本発明のチップキャリヤー装置に組
入れることができる別のチップキャリヤー基板71のそれ
ぞれ分解図及び組立断面図である。チップキャリヤー基
板71は表面74（第5A図）に複数個の半導体チップ73を取
付けたセラミックやその他の材料からなる剛性基板72を
包含する。チップキャリヤー基板71のために相互連結部
材76が設けられている。相互連結部材76は半導体チップ
73を互に電気的に接続し且つ該相互連結部材76の周囲近
くに配置したコンタクトパッド78（第4A図）に電気的に
接続するための複数本のコンダクター77を提供する。相
互連結部材76はなるべく一層または複数層からなる薄い
可撓性のプラスチック膜またはシート79を包含してい
る。前記膜の表面または該膜の内部にコンダクター77を
備えるか、または表面と膜の内部の両方においてリード
77が窓80の中に延びている。4A and 5A are an exploded view and an assembled sectional view, respectively, of another chip carrier substrate 71 which can be incorporated in the chip carrier device of the present invention. The chip carrier substrate 71 includes a rigid substrate 72 of ceramic or other material with a plurality of semiconductor chips 73 attached to a surface 74 (Fig. 5A). An interconnection member 76 is provided for the chip carrier substrate 71. The interconnection member 76 is a semiconductor chip
A plurality of conductors 77 are provided for electrically connecting 73 to each other and to contact pads 78 (FIG. 4A) located near the perimeter of the interconnecting member 76. The interconnecting member 76 comprises a thin flexible plastic film or sheet 79, preferably in one or more layers. A conductor 77 is provided on the surface of the film or inside the film, or leads are provided both on the surface and inside the film.
77 extends into window 80.

例えば、プラスチック膜79は誘電率１〜３を有するポ
リアミド，テフロンその他の誘電性有機材料で作ること
ができ、且つ例えば第4B図に示すように高密度の誘電体
を提供するため多数層膜をなるべく包含する。第4B図に
おいて、相互連結部材76は２枚の誘電性箔層84,86によ
って分離されている３枚の誘電層81,82,83を持った多層
膜を包含する。誘電層81,82,83はそれぞれ複数本のコン
ダクター87,88,89（第4B図の面に垂直方向に延びるよう
図示している）を有する。For example, the plastic film 79 can be made of a dielectric organic material such as polyamide, Teflon, or the like having a dielectric constant of 1 to 3, and a multi-layer film to provide a high density dielectric as shown in FIG. 4B, for example. Include as much as possible. In FIG. 4B, interconnection member 76 comprises a multilayer film having three dielectric layers 81, 82, 83 separated by two dielectric foil layers 84, 86. The dielectric layers 81, 82, 83 each have a plurality of conductors 87, 88, 89 (shown as extending perpendicular to the plane of FIG. 4B).

コンダクター87,88,89は多くの半導体チップ73の間並
びにチップ73からコンタクトパッド78に信号を送るため
の信号搬送用コンダクターを包含する。箔層84はパワー
プレイン（power plane）を含み、且つ箔層86はグラン
ドプレイン（ground plane）を含むことができる。コン
ダクター担持用の多層膜とその製造方法は当業者に公知
であり且つ例えば米国特許第4,480,288号に説明されて
おり、ここに詳細に説明する必要がない。基本的に、前
記コンダクターは印刷技法とエッチング技法によって形
成され且つ一緒に積層されて完全な膜を形成する。また
その代りに、スパッタ法と真空蒸着法とプラズマエッチ
ング法によって絶縁層や導電層を順番に蒸着する方法を
使用し、同様に半導体溶液に相互接続を行なったときに
使用する加算法と減算法の組合せを使用しても良い。Conductors 87, 88, 89 include signal carrying conductors between many semiconductor chips 73 and for sending signals from chips 73 to contact pads 78. Foil layer 84 may include a power plane and foil layer 86 may include a ground plane. Multilayer films for carrying conductors and methods for making the same are known to those skilled in the art and are described, for example, in US Pat. No. 4,480,288 and need not be described at length here. Basically, the conductors are formed by printing and etching techniques and laminated together to form a complete film. Instead, the method of sequentially depositing the insulating layer and the conductive layer by the sputtering method, the vacuum deposition method, and the plasma etching method is used. Similarly, the addition method and the subtraction method used when interconnecting the semiconductor solution are used. You may use the combination of.

可撓性の相互接続部材76は約６〜20ミル（0.15〜0.50
mm）の厚さを有し、且つ各誘電層は約３ミル（0.075m
m）の厚さを有する。前記コンダクターは例えば約0.000
5〜0.002インチ（0.0127〜0.05mm）の厚さと0.001〜0.0
03インチ（0.025〜0.075mm）の幅を有し且つ前記箔層は
約１ミル（0.0254mm）の厚さを有する。膜の層の数とそ
の大きさは勿論特定の使用に応じて変えることができ
る。The flexible interconnect member 76 is approximately 6-20 mils (0.15-0.50
mm) and each dielectric layer is about 3 mils (0.075 m)
m) thickness. The conductor is, for example, about 0.000
5-0.002 inch (0.0127-0.05mm) thickness and 0.001-0.0
It has a width of 03 inches (0.025 to 0.075 mm) and the foil layer has a thickness of about 1 mil (0.0254 mm). The number of layers in the membrane and its size can, of course, vary depending on the particular use.

特に第4A図の実施例を参照すれば、相互接続部材76は
複数個の孔80を備え、該部材76を基板74上にのせるとき
チップ73が前記孔80の中を貫通する。With particular reference to the embodiment of FIG. 4A, the interconnect member 76 includes a plurality of holes 80 through which a chip 73 penetrates when the members 76 are mounted on a substrate 74.

可撓性膜79を備え表面にコンダクター77とコンタクト
パッド78を有する相互接続部材76が接着剤や任意の適当
な機械的取付装置によって第4A図の数個所（例えば４個
所）91で基板72の表面に取付けられている。相互接続部
材76はこのようにして保持されているが、そうしなけれ
ば基板72の表面の全域から外れて、幾分該表面にゆるく
（張った状態でない）配置されている。相互接続部材76
を剛性のある基板に対し非常に小数の個所で取付けてい
るので、相互接続部材76が基板72に対し横方向に移動す
るのを抑制するが、コンダクター77を自由に基板72とチ
ップ73に対し撓わませ且つ変形させる。換言すれば、チ
ップキャリヤー基質71において可撓性のコンダクター担
持用相互接続部材76は物理的に剛性基板72から分離して
おり、基板72の歪みや曲りがコンダクター77に影響せず
且つチップキャリヤー基板71の電気的性能に干渉しな
い。相互接続部材76とコンダクター77は可撓性を有する
ので、基板72と膜の膨脹係数に差が存在しても、チップ
キャリヤー基板71に電気的接続を確実に維持するように
充分に撓み且つ曲ることができる。An interconnect member 76 having a flexible membrane 79 and a conductor 77 and contact pads 78 on its surface is attached to the substrate 72 at several locations (eg, four locations) 91 in FIG. 4A by an adhesive or any suitable mechanical attachment device. Mounted on the surface. The interconnecting member 76 is retained in this manner, but is otherwise placed loosely (not taut) on the surface of the substrate 72, off the entire surface thereof. Interconnect member 76
Attaches to the rigid board in a very small number of locations to prevent the interconnecting member 76 from moving laterally with respect to the board 72, but leaves the conductor 77 free to attach to the board 72 and the chip 73. Bend and deform. In other words, in the chip carrier substrate 71, the flexible conductor-carrying interconnection member 76 is physically separated from the rigid substrate 72 so that the distortion or bending of the substrate 72 does not affect the conductor 77 and the chip carrier substrate. Does not interfere with the electrical performance of the 71. The interconnection member 76 and conductor 77 are flexible so that they flex and bend sufficiently to ensure electrical connection to the chip carrier substrate 71 despite differences in the expansion coefficients of the substrate 72 and the film. You can

コンダクター担持用相互接続部材76と基板72が物理的
に分離しているので、チップキャリヤー基板71を設計す
るに当り大きな融通性が存在する。例えば、相互連結部
材76はチップキャリヤー基板71の送電線特性を最適化さ
せるように設計することができ、且つ基板72をチップキ
ャリヤー71の構造特性と温度特性を最大限になるように
設計することができる。Since the conductor-carrying interconnect member 76 and the substrate 72 are physically separated, there is great flexibility in designing the chip carrier substrate 71. For example, the interconnection member 76 may be designed to optimize the power transmission line characteristics of the chip carrier substrate 71, and the substrate 72 should be designed to maximize the structural and temperature characteristics of the chip carrier 71. You can

第5A図に示すように、各半導体チップ73のターミナル
域はワイヤーボンド93によって相互連結部材76の導電性
通路77に電気的に接続することができ、且つ表面膜79に
形成されている部材76上のコンタクトパッド78（第4A
図）は第１図乃至第３図に示すようにリード36又はリー
ド56の内側部分に直接取付ける。このようにして、第１
図の印刷回路盤14から第4A図及び第5A図の半導体チップ
73に至る複数本の電気コンダクターの殆んど全長が可撓
性の非剛性となるが、但しハウジングのフレーム内に含
まれるリード36,56の一部分36a,56aのみは例外である。As shown in FIG. 5A, the terminal area of each semiconductor chip 73 can be electrically connected to the conductive path 77 of the interconnection member 76 by the wire bond 93, and the member 76 formed on the surface film 79. Upper contact pad 78 (4A
Is attached directly to the inner portion of lead 36 or lead 56 as shown in FIGS. In this way, the first
Printed circuit board 14 to semiconductor chip of FIGS. 4A and 5A
Almost the entire length of the electrical conductors up to 73 is flexible and non-rigid, except for the portions 36a, 56a of the leads 36, 56 contained within the frame of the housing.

第5B図及び第5C図は可撓性の相互接続部材を支持する
チップキャリヤー基板の別の実施例を示す。5B and 5C show another embodiment of a chip carrier substrate supporting a flexible interconnect member.

第5B図において、チップキャリヤー基板71bは個々の
半導体チップ103を中に配置している複数個のへこみ102
を有するセラミック基板101を包含する。チップ103は例
えばチップ103とへこみ102の底部との間に施された半田
によって基板101に固定できる。へこみ102の深さはなる
べく半導体チップ103の厚さよりも僅かに深い。第5B図
の実施例において、チップ103のターミナル域はもっと
低廉でもっと信頼性のあるテープ自動式接着法により可
撓性部材106のコンダクターに接続できる。周知のよう
に、導電性バンプ107が相互接続ブリッジ108の導電域と
チップ103に接着されている。ブリッジ108は加熱加圧接
着法すなわちAuSu“Eutectic"接着法によって接着さ
れ、且つチップキャリヤーのすべてのブリッジ108は周
知のように同時に接着することができる。また、第4A図
に示すようにリードがネット76から窓80に延び且つ上述
の方法と同じように直接チップチーミナル107に接着さ
れている。チップ103とコンダクターを相互接続部材106
上で整列させることにより、ワイヤーボンドによっても
またテープ自動式接着法によっても、相互接続部の長さ
は極限されて相互接続の抵抗を減少し且つ一層効果的な
導電通路を提供する。In FIG. 5B, the chip carrier substrate 71b has a plurality of indentations 102 having individual semiconductor chips 103 disposed therein.
A ceramic substrate 101 having The chip 103 can be fixed to the substrate 101 by solder applied between the chip 103 and the bottom of the dent 102, for example. The depth of the dent 102 is slightly deeper than the thickness of the semiconductor chip 103. In the embodiment of FIG. 5B, the terminal area of the chip 103 can be connected to the conductor of the flexible member 106 by a cheaper and more reliable tape automated bonding method. As is known, conductive bumps 107 are adhered to the conductive areas of interconnect bridge 108 and chip 103. The bridges 108 are bonded by a heat and pressure bonding method or AuSu "Eutectic" bonding method, and all the bridges 108 of the chip carrier can be bonded simultaneously as is well known. Also, as shown in FIG. 4A, leads extend from the net 76 to the window 80 and are directly bonded to the chip teamminal 107 in the same manner as described above. Chip 103 and conductor interconnecting member 106
With the above alignment, either by wirebonding or by tape automated bonding, the length of the interconnect is limited to reduce the resistance of the interconnect and provide a more effective conductive path.

上述のように、２つの非類似の材料を一緒に接着して
温度の変化を受けるとき、この２つの材料は異なった量
膨張する。このことはサンドイッチ接着を生じ、いわゆ
る“バイメタリック効果”をもたらす。これはつぎに半
導体を圧縮して、例えばゲインやリニアリティの変化の
ような性能変化を生ずる。基板と連続用ネットを物理的
に分離しているので、チップキャリヤー装置の設計に大
きな融通性を与える。As mentioned above, when two dissimilar materials are bonded together and undergo a change in temperature, the two materials expand different amounts. This results in a sandwich bond, resulting in the so-called "bimetallic effect". This in turn compresses the semiconductor, resulting in performance changes such as gain and linearity changes. The physical separation of the substrate and the continuity net provides great flexibility in the design of the chip carrier device.

例えば、第5C図においてチップキャリヤー71cは金属
で作った基板111を有する。強力な熱伝達を必要とする
分野に金属基板が望ましい。第5C図に示すように、金属
基板は使用するとき、集積回路チップ113を取付ける複
数個のペデスタル112を形成している。このペデスタル
は公知のパンチ成形法によって基板に形成し、且つなる
べくそれに取付けるチップと大体同一大きさである。ペ
デスタル112はチップを簡単な方法で基板上に正確に位
置決めさせる。特に、ペデスタルの上面に半田成形品を
載せ、チップをこの半田の上に載せる。つぎに半田を水
素の存在のもとに加熱して半田を溶かす。チップが半田
の表面を浮遊し、表面張力によってチップをペデスタル
上で自動的に中心に位置決めし、半田が硬化したときに
チップがペデスタル上に正しく配置され且つ半田付けさ
れるようにする。この方法によって複数個のチップが同
時にそれぞれのペデスタル上に配置され且つ半田付けさ
れる。また、表面張力によって半田がペデスタルからこ
ぼれるのを防止する。For example, in FIG. 5C, the chip carrier 71c has a substrate 111 made of metal. Metallic substrates are desirable for areas requiring strong heat transfer. As shown in FIG. 5C, the metal substrate, when used, forms a plurality of pedestals 112 for mounting integrated circuit chips 113. The pedestal is formed on a substrate by a known punch forming method, and has a size substantially the same as that of a chip attached to the substrate as much as possible. The pedestal 112 accurately positions the chip on the substrate in a simple manner. In particular, the solder molded product is placed on the upper surface of the pedestal, and the chip is placed on this solder. Next, the solder is heated in the presence of hydrogen to melt the solder. The chip floats on the surface of the solder, and surface tension automatically centers the chip on the pedestal so that when the solder cures, the chip is properly positioned and soldered on the pedestal. By this method, multiple chips are simultaneously placed and soldered onto their respective pedestals. It also prevents solder from spilling from the pedestal due to surface tension.

半導体チップ113はワイヤボンド117やその他の連結構
造例えばTABやTAB状装置によって可撓性膜116の導電性
通路に電気的に接続できる。The semiconductor chip 113 can be electrically connected to the conductive path of the flexible film 116 by wire bonds 117 or other connection structures such as TAB or TAB-like devices.

コンダクターとチップを基板から絶縁するために金属
基板の表面に非導電性すなわち絶縁性被膜118を施すこ
とが通常望ましい。この被膜は公知のスパッタリング法
によっても施すことができるテフロンやその他の材料で
作る。被膜18はマイクロウェーブを使用するメタン・水
素法によりまたはアセトン法その他の方法によって付着
されるダイヤモンドの薄層である。ダイヤモンドは理想
的な熱の伝導体すなわちコンダクターである。ボンド11
7の長さを縮小するため凡そペデスタル112のレベルに達
するまで基板から相互接続部材116を隔てるために非伝
導性のスペーサ119を設けても良い。It is usually desirable to apply a non-conductive or insulating coating 118 to the surface of the metal substrate to insulate the conductors and chips from the substrate. This coating is made of Teflon or other material that can also be applied by known sputtering techniques. The coating 18 is a thin layer of diamond deposited by the methane-hydrogen method using microwaves or by the acetone method or other methods. Diamond is an ideal heat conductor. Bond 11
A non-conductive spacer 119 may be provided to separate the interconnect member 116 from the substrate until the level of the pedestal 112 is reached to reduce the length of 7.

本発明の好適な実施例について説明したけれども、本
発明はその他色々の形態を取ることができる。したがっ
て、本発明は特許請求の範囲によってのみ限定されると
解釈すべきである。While the preferred embodiment of the invention has been described, the invention can take various other forms. Therefore, the present invention should be construed as limited only by the appended claims.

（発明の効果） チップキャリヤー基板は、半導体チップが取り付けら
れた一面をハウジングの内方に向けた状態でハウジング
の上部凹みまたは下部凹みのいずれにも取り付けられる
ようになっているので、チップキャリヤー基板のハウジ
ングへの取付作業において自由度の大きいものとなる。(Advantages of the Invention) The chip carrier substrate is designed to be mounted in either the upper recess or the lower recess of the housing with one surface on which the semiconductor chip is mounted facing inward of the housing. There is a high degree of freedom in the work of attaching the to the housing.

【図面の簡単な説明】[Brief description of drawings]

第１図は本発明の半導体チップキャリヤー装置と該装置
を取付ける印刷回路盤の分解斜視図、第２図は組立状態
にある第１図の装置の一部分の断面図、第３図は本発明
の半導体チップキャリヤーの別の実施例を示す断面図、
第4A図は本発明の好適実施例のチップキャリヤー装置の
分解斜視図、第4B図は第4A図の可撓性相互接続部材の拡
大断面図、第5A図は組立状態にある第4A図及び第4B図の
チップキャリヤーの一部分の断面図、第5B図と第5C図は
本発明のチップキャリヤーの別の実施例を示す断面図で
ある。 10……半導体チップキャリヤー装置 11……ハウジング 12……チップキャリヤー基板 13……半導体チップ 14……印刷回路盤 17……カバー 26……上部凹み 27……下部凹み 30……基板 71……チップキャリヤー基板 73……半導体チップFIG. 1 is an exploded perspective view of a semiconductor chip carrier device of the present invention and a printed circuit board to which the device is attached, FIG. 2 is a sectional view of a part of the device of FIG. 1 in an assembled state, and FIG. Sectional drawing which shows another Example of a semiconductor chip carrier,
FIG. 4A is an exploded perspective view of a chip carrier device of a preferred embodiment of the present invention, FIG. 4B is an enlarged cross-sectional view of the flexible interconnect member of FIG. 4A, and FIG. 5A is an assembled state of FIG. 4A and FIG. 4B is a sectional view showing a part of the chip carrier, and FIGS. 5B and 5C are sectional views showing another embodiment of the chip carrier of the present invention. 10 …… Semiconductor chip carrier device 11 …… Housing 12 …… Chip carrier substrate 13 …… Semiconductor chip 14 …… Printed circuit board 17 …… Cover 26 …… Upper recess 27 …… Lower recess 30 …… Board 71 …… Chip Carrier substrate 73 ... Semiconductor chip

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】一面に複数の半導体チップが配置接続され
た略矩形状のチップキャリヤー基板を印刷回路盤に接続
する半導体チップキャリヤー装置において、 夫々前記チップキャリヤー基板の端部を受ける寸法形状
の上部凹みおよび下部凹みを有する略矩形枠状のハウジ
ングと、 該ハウジングの壁面の略中央に該壁面に対して略直交し
て設けられた前記ハウジングの内方および外方へ延出す
る可撓性の内部および外部リード部分を有する複数のリ
ードと、 前記チップキャリヤー基板の前記半導体チップを外気か
ら密閉するカバーとを備え、 前記チップキャリヤー基板は、前記一面を前記ハウジン
グの内方に向けた状態で前記ハウジングの前記上部凹み
または下部凹みに取り付け、前記リードの前記内部リー
ド部分と前記半導体チップを接続し、前記カバーは前記
チップキャリヤー基板の取り付けられていない側にある
前記下部凹みまたは上部凹みに取り付けた板状部材また
は前記各半導体チップを包囲する個別キャップとするこ
とを特徴とする半導体チップキャリヤー装置。1. A semiconductor chip carrier device for connecting a substantially rectangular chip carrier substrate, in which a plurality of semiconductor chips are arranged and connected to one surface, to a printed circuit board, wherein upper portions each having a size and shape for receiving an end portion of the chip carrier substrate. A substantially rectangular frame-shaped housing having a recess and a lower recess, and a flexible housing extending inwardly and outwardly of the housing provided substantially at the center of the wall surface of the housing and substantially orthogonal to the wall surface. A plurality of leads having inner and outer lead portions; and a cover for sealing the semiconductor chip of the chip carrier substrate from the outside air, wherein the chip carrier substrate has the one surface facing inward of the housing. Attached to the upper recess or the lower recess of the housing, connecting the inner lead portion of the lead and the semiconductor chip. The semiconductor chip carrier device according to claim 1, wherein the cover is a plate-shaped member attached to the lower recess or the upper recess on the non-attached side of the chip carrier substrate or an individual cap surrounding each of the semiconductor chips.
JP62256144A 1986-10-09 1987-10-09 Semiconductor chip carrier device Expired - Lifetime JPH0834278B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US91697486A 1986-10-09 1986-10-09
US916974 1986-10-09

Publications (2)

Publication Number Publication Date
JPH01102952A JPH01102952A (en) 1989-04-20
JPH0834278B2 true JPH0834278B2 (en) 1996-03-29

Family

ID=25438169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62256144A Expired - Lifetime JPH0834278B2 (en) 1986-10-09 1987-10-09 Semiconductor chip carrier device

Country Status (2)

Country Link
JP (1) JPH0834278B2 (en)
GB (1) GB2196178B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW212261B (en) * 1992-03-09 1993-09-01 Matsushita Electric Ind Co Ltd Electronic circuit device and manufacturing method
EP0576735B1 (en) * 1992-06-29 1997-09-10 Océ-Nederland B.V. Mounting structure for electro-optical devices
US5824950A (en) * 1994-03-11 1998-10-20 The Panda Project Low profile semiconductor die carrier
US5821457A (en) * 1994-03-11 1998-10-13 The Panda Project Semiconductor die carrier having a dielectric epoxy between adjacent leads
US6339191B1 (en) 1994-03-11 2002-01-15 Silicon Bandwidth Inc. Prefabricated semiconductor chip carrier
US6016256A (en) 1997-11-14 2000-01-18 The Panda Project Multi-chip module having interconnect dies
US6141869A (en) * 1998-10-26 2000-11-07 Silicon Bandwidth, Inc. Apparatus for and method of manufacturing a semiconductor die carrier
EP1324386B1 (en) * 2001-12-24 2011-06-15 ABB Research Ltd. Semiconductor module and method of manufacturing a semiconductor module
JP2007141667A (en) * 2005-11-18 2007-06-07 Furukawa Electric Co Ltd:The Method for connecting terminals on base plates

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4976066A (en) * 1972-11-27 1974-07-23
US4074342A (en) * 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
DE3124692A1 (en) * 1981-06-24 1983-01-13 Robert Bosch Gmbh, 7000 Stuttgart "SEMICONDUCTOR RECTIFIER"
JPS5875863A (en) * 1981-10-13 1983-05-07 フエアチヤイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン Hybrid circuit module and method of producing same
DE3241509A1 (en) * 1982-11-10 1984-05-10 Brown, Boveri & Cie Ag, 6800 Mannheim POWER TRANSISTOR MODULE

Also Published As

Publication number Publication date
GB2196178B (en) 1990-04-11
GB8721203D0 (en) 1987-10-14
JPH01102952A (en) 1989-04-20
GB2196178A (en) 1988-04-20

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