JPH0832547A - Synchronization acquisition method - Google Patents
Synchronization acquisition methodInfo
- Publication number
- JPH0832547A JPH0832547A JP16726894A JP16726894A JPH0832547A JP H0832547 A JPH0832547 A JP H0832547A JP 16726894 A JP16726894 A JP 16726894A JP 16726894 A JP16726894 A JP 16726894A JP H0832547 A JPH0832547 A JP H0832547A
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- JP
- Japan
- Prior art keywords
- correlation
- trial
- power
- synchronization
- result
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＤＳ（Direct Sequenc
e ）と呼ばれるスペクトル拡散によって変調された信号
を、同一周波数帯域内に多重化して通信を行うコード分
割多元接続（Code Division Multiple Access 、以下Ｃ
ＤＭＡという）通信方式に基づく、移動通信システムに
おける受信局での同期捕捉方法に関するものである。This invention relates to a DS (Direct Sequenc
e) a signal modulated by spread spectrum, which is multiplexed within the same frequency band for communication, and is used for code division multiple access (hereinafter C).
The present invention relates to a synchronization acquisition method at a receiving station in a mobile communication system based on a communication system called DMA.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
例えば次のような文献に記載されるものがあった。 文献；信学技報、SST92-21（1992）電子通信学会、田近
著“スペクトル拡散通信におけるディジタルマッチドフ
ィルタ技術とその問題点”P.1-6 従来、ＣＤＭＡ通信では、送信側と受信側で同一の擬似
コード（pseudo noisecode 、以下ＰＮコードという）
を用いてデータの拡散及び逆拡散を行うために、ベース
バンド帯域での受信信号と受信局との同期が必要とな
る。即ち、受信信号のＰＮコードと受信局内で発生され
るＰＮコードとが一致した時のみ正確に復調される。こ
のため、ＣＤＭＡ通信の受信局では、通信の初期におい
て正確な同期位置をつかむ必要がある。これを同期の捕
捉という。受信局では、まず、アンテナより受信された
信号に、搬送波信号及びそれよりπ／２ずれた信号を乗
算することによってベースバンド帯域（ＰＮコード帯
域）の同相成分信号（以下、Ｉ相信号という）及び直交
成分信号（以下、Ｑ相信号という）に変換する。同期捕
捉方法では、各相信号にＰＮコード系列を１チップ毎に
乗算し、加算することで相関をとる。各相相関結果を２
乗して加算し、受信信号の相関結果の絶対値（パワー）
を得る。理想的な状態では、受信信号のＰＮコードと受
信局が発生するＰＮコードとが一致した時のみ高いパワ
ーが得られ、１チップでも外れるとパワーが０に近くな
る。2. Description of the Related Art Conventionally, techniques in such a field include:
For example, some documents were described in the following documents. References: IEICE Technical Report, SST92-21 (1992) The Institute of Electronics and Communication Engineers, Tajika, “Digital Matched Filter Technology and Its Problems in Spread Spectrum Communication” P.1-6 Conventionally, in CDMA communication, the transmitting side and the receiving side Identical pseudo code (pseudo noise code, hereinafter referred to as PN code)
In order to perform data spreading and despreading by using, it is necessary to synchronize the received signal with the receiving station in the baseband. That is, the demodulation is accurately performed only when the PN code of the received signal and the PN code generated in the receiving station match. Therefore, the receiving station of the CDMA communication needs to grasp an accurate synchronization position in the initial stage of the communication. This is called synchronization acquisition. In the receiving station, first, a signal received from the antenna is multiplied by a carrier signal and a signal shifted by π / 2 from the carrier signal to in-phase component signal in the baseband (PN code band) (hereinafter referred to as I-phase signal). And a quadrature component signal (hereinafter referred to as a Q-phase signal). In the synchronization acquisition method, a correlation is obtained by multiplying each phase signal by a PN code sequence chip by chip and adding them. 2 for each phase correlation result
Multiply and add, absolute value (power) of correlation result of received signal
Get. In an ideal state, high power is obtained only when the PN code of the received signal and the PN code generated by the receiving station match, and the power becomes close to 0 when even one chip is removed.
【０００３】同期位置を見つける方法としては、一般
に、前記文献に記載されたマッチドフィルタと呼ばれる
方法がとられる。これは、前記の相関パワーを算出する
手段を１チップまたは数分の１チップづつずらしながら
行い、相関パワーが最も高い位置、または相関パワーし
きい値を超えた位置をＰＮコードが一致した位置とみな
し、同期位置とする方法である。通常、同期捕捉には、
パイロット信号あるいはプリアンブル信号といった既知
データ信号が用いられる。一般的に、既知データとして
は、オール１または−１が用いられる。即ち、データ変
調されていないＰＮコードとなる。パイロット信号は、
通話信号に重ねて常時送信され、プリアンブル信号は通
話信号に先立って送信される。受信局では、データ変調
されていない信号との相関をとるため、複数ビット間に
渡る相関が可能となり、高い相関利得が得られる。前記
のマッチドフィルタでは、相関長分（チップ数）のレジ
スタに受信信号を蓄積し、相関長分のＰＮコードを乗算
係数として、チップ毎に受信信号とＰＮコードの乗算を
並列に行い、加算し、相関結果を得る。次チップの受信
信号が入力されたら、受信信号レジスタを１シフトさせ
た後、レジスタに蓄積し、次の相関演算を行う。これに
より、１チップずれた位置での相関結果が得られる。こ
のため、次チップの信号が入力される前に全相関演算を
終わらせる必要がある。数分の１チップの精度で結果を
得たい場合は、更にレジスタ数を増す。As a method for finding the synchronization position, a method called a matched filter described in the above document is generally used. This is performed by shifting the above-mentioned means for calculating the correlation power by one chip or a fraction of a chip, and the position where the correlation power is highest or the position where the correlation power threshold is exceeded is defined as the position where the PN code matches. This is the method of setting the synchronization position. Normally, for synchronous acquisition,
Known data signals such as pilot signals or preamble signals are used. Generally, all 1 or -1 is used as the known data. That is, the PN code is not data-modulated. The pilot signal is
The preamble signal is always transmitted over the call signal, and the preamble signal is transmitted prior to the call signal. Since the receiving station correlates with a signal that has not been data-modulated, correlation over a plurality of bits is possible and high correlation gain is obtained. In the matched filter described above, the received signal is stored in a register corresponding to the correlation length (the number of chips), the PN code corresponding to the correlation length is used as a multiplication coefficient, the received signal and the PN code are multiplied in parallel for each chip, and the addition is performed. , Get the correlation result. When the reception signal of the next chip is input, the reception signal register is shifted by 1 and then stored in the register to perform the next correlation calculation. As a result, the correlation result at the position shifted by one chip is obtained. For this reason, it is necessary to complete all correlation calculations before the signal of the next chip is input. If you want to obtain results with a fraction of a chip, increase the number of registers.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
同期捕捉方法では、次のような問題があり、それを解決
することが困難であった。従来の同期捕捉方法における
相関演算は、受信信号とＰＮコードの乗算、その結果の
加算及びその２乗加算で行われる。例えば、拡散を６４
倍とし、相関をとる区間を１ビットとすると、次の受信
信号が入力されるまでの１チップ間（即ち、１ビットの
１／６４の間）に、６４回の乗算を並列に行い、その６
４個の結果を加算し、更にその２乗加算を行わなければ
ならない。高雑音下においては、１ビット区間の相関で
は精度の高い結果が得られないため、複数ビット間にお
いて相関をとる必要が生じる。例えば、相関区間を１０
ビットとすると、１チップ間に６４０回の乗算累積を行
うことになる。即ち、６４０個の受信信号レジスタ及び
ＰＮコードレジスタと、６４０個の乗算器とが必要とな
り、回路規模が非常に大きなものとなる。また、乗算さ
れた結果を６４０回加算しなければならず、非常に高速
の演算が要求される。本発明は、前記従来技術が持って
いた課題として、回路規模が大きく、高速度演算が要求
されるという点について解決した同期捕捉方法を提供す
るものである。However, the conventional synchronization acquisition method has the following problems and it is difficult to solve them. The correlation calculation in the conventional synchronization acquisition method is performed by multiplying the received signal by the PN code, adding the results, and adding the squares thereof. For example, spread 64
If the interval is doubled and the interval for correlation is 1 bit, 64 multiplications are performed in parallel during 1 chip (that is, 1/64 of 1 bit) until the next received signal is input. 6
The four results must be added together, and the squared addition must be performed. Under high noise, a highly accurate result cannot be obtained by the correlation in the 1-bit section, so that it becomes necessary to obtain the correlation between a plurality of bits. For example, if the correlation interval is 10
If the number of bits is set, multiplication and accumulation are performed 640 times in one chip. That is, 640 reception signal registers and PN code registers and 640 multipliers are required, which makes the circuit size very large. Also, the multiplied result has to be added 640 times, which requires very high-speed operation. The present invention provides a synchronization acquisition method that solves the problems that the above-mentioned conventional technique has, that is, that the circuit scale is large and high-speed calculation is required.
【０００５】[0005]
【課題を解決するための手段】第１の発明は、前記課題
を解決するために、ＣＤＭＡ通信方式に基づく移動通信
システムにおける受信局での同期捕捉方法において、受
信信号をベースバンド帯域に変換してベースバンド受信
信号を出力するベースバンド帯域変換手段と、所望局の
所望位置でのＰＮコードを発生させるＰＮコード発生手
段と、前記ベースバンド受信信号と前記ＰＮコードとを
掛け合わせてその乗算結果を累積する乗算・累積手段
と、前記乗算・累積手段での累積数をカウントするカウ
ント手段と、前記乗算・累積手段におけるＩ相信号の累
積結果とＱ相信号の累積結果とをそれぞれ２乗し、それ
らの２乗結果を加算して相関パワーを算出する２乗加算
手段と、前記相関パワーより同期判定を行う同期判定手
段とを用い、次のような処理を行う。ある相関位置にお
いて前記乗算・累積手段によって相関演算を行う。前記
カウント手段のカウント値が相関値に達した時点で、前
記２乗加算手段によって相関パワーを算出し、更に１チ
ップずれた相関位置において相関パワーを算出する。以
後、同様の動作を繰り返し行うことで、前記同相判定手
段によって同相位置を判定させる。In order to solve the above-mentioned problems, a first invention converts a received signal into a baseband band in a synchronization acquisition method at a receiving station in a mobile communication system based on a CDMA communication system. Baseband band conversion means for outputting a baseband received signal, a PN code generation means for generating a PN code at a desired position of a desired station, and a multiplication result obtained by multiplying the baseband received signal by the PN code. The multiplication / accumulation means for accumulating, the counting means for counting the accumulation number in the multiplication / accumulation means, the accumulation result of the I-phase signal and the accumulation result of the Q-phase signal in the multiplication / accumulation means are each squared. Using the square addition means for calculating the correlation power by adding the squared results and the synchronization determination means for performing the synchronization determination based on the correlation power, Perform Do processing. Correlation calculation is performed by the multiplication / accumulation means at a certain correlation position. When the count value of the counting means reaches the correlation value, the square power adding means calculates the correlation power, and further calculates the correlation power at the correlation position deviated by one chip. After that, by repeating the same operation, the in-phase position is determined by the in-phase determination means.
【０００６】第２の発明では、第１の発明のベースバン
ド帯域変換手段、ＰＮコード発生手段、乗算・累積手
段、カウント手段、２乗加算手段及び同期判定手段と、
前記乗算・累積手段によって求めたＩ相信号の試行相関
累積結果とＱ相信号の試行相関累積結果とをそれぞれ２
乗し、それらの２乗結果を加算して試行相関パワーを算
出する試行２乗加算手段と、前記試行相関パワーより試
行相関判定を行う試行相関判定手段とを用い、次のよう
な処理を行う。ある相関位置において前記乗算・累積手
段によって相関演算を行い、前記カウント手段によって
相関数より短い試行相関数をカウントさせる。そのカウ
ント値が試行相関数に達した時点で、前記試行２乗加算
手段によって試行相関パワーを算出し、その算出結果を
前記試行相関判定手段で判定して該算出結果がしきい値
以上の場合のみ第１の発明の相関演算を行わせる。第３
の発明では、第１の発明のベースバンド帯域変換手段及
びＰＮコード発生手段と、第１の発明の乗算・累積手
段、２乗加算手段及びカウント手段と第２の発明の試行
２乗加算手段とでそれぞれ構成される複数のパワー算出
手段と、前記複数のパワー算出手段から出力される複数
の相関パワーより同期判定を行う同期判定手段と、前記
複数のパワー算出手段から出力される複数の試行相関パ
ワーより試行相関判定を行う試行相関判定手段とを用
い、次のような処理を行う。前記ＰＮコード発生手段か
ら発生するＰＮコードを１チップづつずらして前記複数
のパワー算出手段に与え、それらのパワー算出手段を並
列に動作させる。According to a second aspect of the invention, the baseband band conversion means, the PN code generation means, the multiplication / accumulation means, the counting means, the square addition means and the synchronization determination means of the first invention,
The trial correlation cumulative result of the I-phase signal and the trial correlation cumulative result of the Q-phase signal obtained by the multiplying / accumulating means are respectively 2
The following processing is performed using trial square addition means for multiplying and squaring the squared results to calculate trial correlation power, and trial correlation determination means for performing trial correlation determination from the trial correlation power. . At a certain correlation position, the multiplication / accumulation means performs the correlation calculation, and the counting means counts the trial correlation number shorter than the correlation number. When the count value reaches the trial correlation number, the trial square addition means calculates the trial correlation power, and the calculation result is judged by the trial correlation judgment means, and the calculation result is equal to or more than the threshold value. Only the correlation calculation of the first invention is performed. Third
In the invention, the baseband band conversion means and the PN code generation means of the first invention, the multiplication / accumulation means, the square addition means and the counting means of the first invention, and the trial square addition means of the second invention. A plurality of power calculation units respectively configured, a synchronization determination unit that performs a synchronization determination based on a plurality of correlation powers output from the plurality of power calculation units, and a plurality of trial correlations output from the plurality of power calculation units. The following processing is performed by using a trial correlation determining unit that performs trial correlation determination from power. The PN code generated from the PN code generating means is shifted by one chip and supplied to the plurality of power calculating means, and these power calculating means are operated in parallel.
【０００７】[0007]
【作用】第１の発明によれば、ある相関位置において相
関演算が行われ、カウント値が相関数に達した時点で相
関パワーが算出され、更に１チップずれた相関位置にお
いて相関パワーが算出され、同様の動作が繰り返し行わ
れて同期位置の判定が行われる。これにより、受信信号
をレジスタに蓄積することなく、１相関区間の受信信号
で１つの相関結果が得られる。第２の発明によれば、あ
る相関位置において相関演算が行われ、カウント値が試
行相関数に達した時点で試行相関パワーが算出され、試
行相関結果がしきい値以上の場合のみ通常の相関が行わ
れる。これにより、同期捕捉時間が短縮される。第３の
発明によれば、複数のパワー算出手段を用い、１チップ
づつずれたＰＮコードを乗算することで、該パワー算出
手段が並列に動作する。これにより、同期捕捉時間が短
縮される。従って、前記課題を解決できるのである。According to the first invention, the correlation calculation is performed at a certain correlation position, the correlation power is calculated when the count value reaches the correlation number, and the correlation power is calculated at the correlation position shifted by one chip. The same operation is repeated to determine the synchronization position. As a result, one correlation result can be obtained with the received signal in one correlation section without accumulating the received signal in the register. According to the second invention, the correlation calculation is performed at a certain correlation position, the trial correlation power is calculated when the count value reaches the trial correlation number, and the normal correlation is obtained only when the trial correlation result is equal to or more than the threshold value. Is done. This shortens the synchronization acquisition time. According to the third invention, a plurality of power calculating means are used, and the PN codes shifted by one chip are multiplied, whereby the power calculating means operate in parallel. This shortens the synchronization acquisition time. Therefore, the above problem can be solved.
【０００８】[0008]
【実施例】第１の実施例 まず、本発明の第１の実施例の同期捕捉方法の原理を図
３を参照しつつ説明する。図３は、本発明の第１の実施
例の原理説明図である。この同期捕捉方法では、試行相
関を取り入れ、例えば、拡散数を６４とし、ＰＮ系列長
も６４としている。ある局において受信される受信信号
には、その局に対応した１つのＰＮ信号系列ＰＮ０〜Ｐ
Ｎ６３の繰り返しの情報が含まれる。この同期捕捉方法
の同期捕捉時においては、パイロット信号またはプリア
ンブル信号において、ビットデータは全て１となる。こ
のため、ビットの間において１８０度の位相回転は生じ
ない。受信信号の位相は、フェージング（fading）等に
より回転するが、その回転の速度が１ビットより十分に
遅いとする。即ち、受信信号の隣接する数ビット間では
位相の回転は無いと仮定できる。これにより、複数ビッ
ト間での相関が可能となる。相関区間を２ビットとし、
試行相関区間を１ビットとする。試行相関は、通常の相
関より短区間で相関を行い、相関パワーの予備的な結果
を得る。この予備結果と試行相関しきい値との比較を行
い、しきい値以上の場合のみ通常の相関区間まで相関を
継続させる。つまり、可能性の少ない相関を切り捨てる
ことで、同期捕捉にかかる時間を短縮させる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment First, the principle of the synchronization acquisition method of the first embodiment of the present invention will be described with reference to FIG. FIG. 3 is an explanatory diagram of the principle of the first embodiment of the present invention. In this synchronization acquisition method, trial correlation is introduced, and the spreading number is set to 64 and the PN sequence length is set to 64, for example. The received signal received at a certain station includes one PN signal series PN0-P corresponding to that station.
Information on the repetition of N63 is included. At the time of the synchronous acquisition of this synchronous acquisition method, all the bit data is 1 in the pilot signal or the preamble signal. Therefore, there is no 180 degree phase rotation between bits. The phase of the received signal rotates due to fading or the like, but the rotation speed is assumed to be sufficiently slower than 1 bit. That is, it can be assumed that there is no phase rotation between adjacent several bits of the received signal. This enables correlation among a plurality of bits. The correlation interval is 2 bits,
The trial correlation section is 1 bit. In the trial correlation, the correlation is performed in a shorter section than the normal correlation, and a preliminary result of the correlation power is obtained. This preliminary result is compared with the trial correlation threshold, and the correlation is continued up to the normal correlation section only when the trial correlation threshold is exceeded. That is, the time required for the synchronization acquisition is shortened by discarding the correlation that is unlikely to occur.
【０００９】まず、ＰＮ信号ＰＮ０〜ＰＮ６３と受信信
号の相関をとる。この時は、１チップの間に１回の乗算
累積を行う。１ビット間の試行相関後にＩ，Ｑ相の２乗
加算を行い、試行相関パワーを算出する。この算出結果
と試行相関しきい値との比較を行い、その比較結果がし
きい値以下とし、この位置での同期の可能性はないもの
とする。次に、相関をとるＰＮ値を１つ遅らせること
で、１チップずれた位置での相関を行う。つまり、受信
信号に乗算するＰＮ信号をＰＮ６３〜ＰＮ６２の１ビッ
トとする。この位置では、先の位置より同期位置に近い
ため、試行相関においてしきい値以上となる。これによ
り、更に１ビット分の相関が行われ、その相関結果が累
積される。２ビット間の相関後に２乗加算を行い、相関
パワーを算出する。この算出結果と相関しきい値との比
較を行い、その比較結果がしきい値以下とし、この位置
での同期はないものとする。更にＰＮ値を１つ遅らせ、
相関を行う。この位置においては、受信信号のＰＮ値と
相関をとるＰＮ値が一致しているため、試行相関での判
定も成功し、同期の判定も成功として、この位置におい
て同期がとられる。以上のように、この同期捕捉方法で
は、従来のマッチドフィルタに比べ、同期位置を得るま
でに時間を要するが、１チップの間に１つの乗算加算の
みを行うため、回路（ハード）での実現が容易となる。
しかも、試行相関を行うことで、同期にかかる時間の短
縮化が図れる。First, the received signals are correlated with the PN signals PN0 to PN63. At this time, multiplication and accumulation are performed once during one chip. After trial correlation for 1 bit, square addition of I and Q phases is performed to calculate trial correlation power. The calculation result is compared with the trial correlation threshold value, and the comparison result is less than or equal to the threshold value, and there is no possibility of synchronization at this position. Next, the PN value for correlation is delayed by 1 to perform correlation at a position shifted by one chip. That is, the PN signal by which the received signal is multiplied is set to 1 bit of PN63 to PN62. At this position, since it is closer to the synchronization position than the previous position, the trial correlation is more than the threshold value. As a result, one bit of correlation is further performed, and the correlation result is accumulated. After the correlation between the two bits, square addition is performed to calculate the correlation power. The calculation result is compared with the correlation threshold value, the comparison result is equal to or less than the threshold value, and it is assumed that there is no synchronization at this position. Further delay the PN value by 1,
Correlate. At this position, since the PN value that correlates with the PN value of the received signal matches, the determination by trial correlation is also successful, and the determination of synchronization is also successful, and synchronization is established at this position. As described above, in this synchronization acquisition method, it takes more time to obtain the synchronization position than in the conventional matched filter, but since only one multiplication and addition is performed in one chip, it is realized in a circuit (hardware). Will be easier.
Moreover, the time required for synchronization can be shortened by performing the trial correlation.
【００１０】次に、以上のような原理に基づき構成され
た第１の実施例の同期捕捉方法を説明する。図１は、本
発明の第１の実施例の同期捕捉方法に用いられる同期捕
捉回路の機能ブロック図である。この同期捕捉回路は、
アンテナより受信された受信信号１をベースバンド帯域
に変換するための搬送波信号を発生する搬送波発生器２
を有し、該搬送波発生器２に、π／２位相回転器３及び
乗算器４が接続され、更に、該π／２位相回転器３に、
乗算器５が接続されている。π／２位相回転器３は、搬
送波発生器２から発生される搬送波信号をπ／２だけず
らす回路である。乗算器４は、受信信号１と搬送波信号
とを乗算してベースバンド帯域（ＰＮコード帯域）のＩ
相信号Ｒｉを出力する回路である。乗算器５は、受信信
号１とπ／２ずれた搬送波信号とを乗算してベースバン
ド帯域（ＰＮコード帯域）のＱ相信号Ｒｑを出力する回
路である。これらの搬送波発生器２、π／２位相回転器
３、及び乗算器４，５により、受信信号１をベースバン
ド帯域に変換してベースバンド受信信号（Ｒｉ，Ｒｑ）
を出力するベースバンド帯域変換手段が構成されてい
る。また、この同期捕捉回路には、所望局の所望位置で
のＰＮコードを発生させるＰＮコード発生手段であるＰ
Ｎコード発生器６が設けられている。ＰＮコード発生器
６には、カウント手段であるカウンタ７、及び乗算器
８，９が接続されている。カウンタ７は、ＰＮコード発
生器６からＰＮコードが発生される度にカウントアップ
を行い、相関数（相関チップ数）をカウントする回路で
ある。乗算器８はＰＮコード発生器６から発生されるＰ
ＮコードとＩ相信号Ｒｉとを乗算する回路、乗算器９は
該ＰＮコードとＱ相信号Ｒｑとを乗算する回路である。
各乗算器８，９には、蓄積器（アキュムレータ）１０，
１１がそれぞれ接続されている。蓄積器１０は乗算器８
の乗算結果を累積する回路、蓄積器１１は乗算器９の乗
算結果を累積する回路である。これらの乗算器８，９及
び蓄積器１０，１１により、乗算・累積手段が構成され
ている。Next, the synchronization acquisition method of the first embodiment constructed on the basis of the above principle will be described. FIG. 1 is a functional block diagram of a synchronization acquisition circuit used in the synchronization acquisition method according to the first embodiment of the present invention. This synchronization acquisition circuit
Carrier wave generator 2 for generating a carrier wave signal for converting a received signal 1 received from an antenna into a baseband band
And a π / 2 phase rotator 3 and a multiplier 4 are connected to the carrier wave generator 2, and further, the π / 2 phase rotator 3 is
The multiplier 5 is connected. The π / 2 phase rotator 3 is a circuit that shifts the carrier wave signal generated from the carrier wave generator 2 by π / 2. The multiplier 4 multiplies the received signal 1 by the carrier signal to obtain I of the baseband (PN code band).
It is a circuit that outputs the phase signal Ri. The multiplier 5 is a circuit that multiplies the received signal 1 and a carrier signal deviated by π / 2 and outputs a Q-phase signal Rq in the baseband (PN code band). The carrier wave generator 2, the π / 2 phase rotator 3, and the multipliers 4 and 5 convert the reception signal 1 into a baseband band to generate a baseband reception signal (Ri, Rq).
A baseband band conversion means for outputting is output. Further, this synchronization acquisition circuit is a PN code generating means for generating a PN code at a desired position of a desired station.
An N code generator 6 is provided. The PN code generator 6 is connected to a counter 7, which is a counting means, and multipliers 8 and 9. The counter 7 is a circuit that counts up each time a PN code is generated from the PN code generator 6, and counts the number of correlations (correlation chip number). The multiplier 8 is the P generated by the PN code generator 6.
A circuit for multiplying the N code by the I-phase signal Ri, and a multiplier 9 is a circuit for multiplying the PN code by the Q-phase signal Rq.
Each of the multipliers 8 and 9 includes a storage device (accumulator) 10,
11 are connected to each other. Accumulator 10 is multiplier 8
The accumulator 11 is a circuit for accumulating the multiplication result of 1. and the accumulator 11 is a circuit for accumulating the multiplication result of the multiplier 9. The multipliers 8 and 9 and the accumulators 10 and 11 form a multiplication / accumulation unit.
【００１１】一方の蓄積器１０には２乗器１２，１３が
接続され、他方の蓄積器１１にも２乗器１４，１５が接
続され、更に該２乗器１２，１４が加算器１６に接続さ
れると共に、該２乗器１３，１５が加算器１７に接続さ
れている。２乗器１２は蓄積器１０におけるＩ相信号Ｒ
ｉの試行相関累積結果を２乗する回路、２乗器１４は蓄
積器１１におけるＱ相信号Ｒｑの試行相関累積結果を２
乗する回路、更に加算器１６は該２乗器１２，１４の２
乗結果を加算して試行相関パワーを出力する回路であ
る。これらの２乗器１２，１４及び加算器１６により、
試行２乗加算手段が構成されている。また、２乗器１３
は蓄積器１０におけるＩ相信号Ｒｉの累積結果を２乗す
る回路、２乗器１５は蓄積器１１におけるＱ相信号Ｒｑ
の累積結果を２乗する回路、更に加算器１７は該２乗器
１３，１５における２乗結果を加算して相関パワーを出
力する回路である。これらの２乗器１３，１５及び加算
器１７により、２乗加算手段が構成されている。一方の
加算器１６には試行相関判定手段である試行相関判定器
１８が接続され、他方の加算器１７にも同期判定手段で
ある同期判定器１９が接続されている。試行相関判定器
１８は、加算器１６より出力される試行相関パワーを試
行相関しきい値と比較して試行相関判定を行う回路であ
る。同期判定器１９は、加算器１７から出力される相関
パワーを相関しきい値と比較し、同期判定を行う回路で
ある。Squares 12 and 13 are connected to one of the accumulators 10, squarers 14 and 15 are also connected to the other accumulator 11, and the squarers 12 and 14 are connected to an adder 16. In addition to being connected, the squarers 13 and 15 are connected to the adder 17. The squarer 12 is the I-phase signal R in the accumulator 10.
A circuit for squaring the trial correlation cumulative result of i, the squarer 14 outputs the trial correlation cumulative result of the Q-phase signal Rq in the accumulator 11 to 2
The circuit for multiplying, and the adder 16 are the two of the squarers 12, 14
This is a circuit for adding trial results and outputting trial correlation power. With these squarers 12, 14 and adder 16,
A trial square addition means is configured. Also, the squarer 13
Is a circuit for squaring the accumulation result of the I-phase signal Ri in the accumulator 10, and the squarer 15 is a Q-phase signal Rq in the accumulator 11.
And a adder 17 is a circuit for adding the squared results of the squarers 13 and 15 and outputting the correlation power. The square adders 13 and 15 and the adder 17 constitute a square adder. One of the adders 16 is connected to a trial correlation determiner 18 which is a trial correlation determining means, and the other adder 17 is also connected to a synchronization determiner 19 which is a synchronization determining means. The trial correlation determiner 18 is a circuit that compares the trial correlation power output from the adder 16 with a trial correlation threshold value to perform trial correlation determination. The synchronization determiner 19 is a circuit that compares the correlation power output from the adder 17 with a correlation threshold value and determines synchronization.
【００１２】図２は、図１の同期捕捉回路を用いた同期
捕捉方法の処理手順を示すフローチャートであり、この
図２を参照しつつ本実施例の同期捕捉方法を説明する。
なお、図２のフローチャートは、ベースバンド帯域へ変
換された後の動作を示している。アンテナより受信され
た受信信号１は、各乗算器４，５へ送られる。一方の乗
算器４では、受信信号１と、搬送波発生器２から発生さ
れた搬送波信号とを乗算し、該受信信号１をベースバン
ド帯域（ＰＮコード帯域）のＩ相信号Ｒｉに変換する。
他方の乗算器５では、受信信号１と、π／２位相回転器
３でπ／２ずらされた搬送波信号とを乗算し、該受信信
号１をベースバンド帯域（ＰＮコード帯域）のＱ相信号
Ｒｑに変換する。相関演算を開始する前に、先ず、図２
のステップＳＴ１において蓄積器１０，１１及びカウン
タ７をリセットする。そしてステップＳＴ２で相関演算
を開始し、受信ベースバンド信号のうちのＩ相信号Ｒｉ
とＰＮコード発生器６より発生されるＰＮコードとを乗
算器８で乗算し、その乗算結果を蓄積器１０に蓄積す
る。更に、受信ベースバンド信号のうちのＱ相信号Ｒｑ
とＰＮコードとを乗算器９で乗算し、その乗算結果を蓄
積器１１によって累積する。カウンタ７は、ＰＮコード
が発生される度にカウントアップを行い、相関数（相関
チップ数）をカウントする。ステップＳＴ３において、
カウンタ７のカウント値が試行相関数に達した時、該カ
ウンタ７が各蓄積器１０，１１に通知する。蓄積器１
０，１１では、乗算器８，９の蓄積結果を２乗器１２，
１４へ送出する。２乗器１２，１４では、蓄積器１０，
１１の蓄積結果をそれぞれ２乗し、その２乗値が加算器
１６で加算され、試行相関パワーを得る。FIG. 2 is a flow chart showing a processing procedure of a synchronization acquisition method using the synchronization acquisition circuit of FIG. 1. The synchronization acquisition method of the present embodiment will be described with reference to FIG.
The flowchart in FIG. 2 shows the operation after conversion to the baseband band. Received signal 1 received from the antenna is sent to each of multipliers 4 and 5. On the other hand, the multiplier 4 multiplies the received signal 1 by the carrier signal generated by the carrier generator 2 to convert the received signal 1 into an I-phase signal Ri in the baseband (PN code band).
The other multiplier 5 multiplies the received signal 1 by the carrier signal shifted by π / 2 by the π / 2 phase rotator 3, and the received signal 1 is a Q-phase signal in the baseband (PN code band). Convert to Rq. Before starting the correlation calculation, first, as shown in FIG.
In step ST1 of, the accumulators 10 and 11 and the counter 7 are reset. Then, in step ST2, the correlation calculation is started, and the I-phase signal Ri of the received baseband signal is
And the PN code generated by the PN code generator 6 are multiplied by the multiplier 8, and the multiplication result is accumulated in the accumulator 10. Furthermore, the Q-phase signal Rq of the received baseband signal
And the PN code are multiplied by the multiplier 9, and the multiplication result is accumulated by the accumulator 11. The counter 7 counts up each time a PN code is generated and counts the number of correlations (correlation chip number). In step ST3,
When the count value of the counter 7 reaches the trial correlation number, the counter 7 notifies each of the accumulators 10 and 11. Accumulator 1
In 0 and 11, the accumulation results of the multipliers 8 and 9 are converted to the squarer 12,
Send to 14. In the squarers 12 and 14, the accumulator 10,
The accumulated results of 11 are squared, and the squared values are added by the adder 16 to obtain the trial correlation power.
【００１３】ステップＳＴ４において、算出された試行
相関パワーが試行相関判定器１８によって試行相関しき
い値と比較される。もし、試行相関パワーがしきい値以
下であれば、その位置での同期の可能性はないものとし
て、ステップＳＴ１へ戻り、蓄積器１０，１１及びカウ
ンタ７がリセットされて次の相関位置に移行する。この
移行方法としては、例えば、図３に示すように、ＰＮコ
ード発生器６で発生されるＰＮコードを１つ遅らせるよ
うな方法がとられる。相関判定等に１チップ区間とられ
たとすると、受信信号１は１チップ進むため、発生され
るＰＮコードはそのままとなる。一方、ステップＳＴ４
において、試行相関パワーがしきい値以上であれば、ス
テップＳＴ５へ進み、更に相関演算を続行する。蓄積器
１０，１１では、そのまま累積を続行する。ステップＳ
Ｔ６において、カウンタ７のカウント値が相関数に達し
た時、該カウンタ７が各蓄積器１０，１１へ通知する。
蓄積器１０，１１は該蓄積結果を２乗器１３，１５へ送
出し、その２乗結果が加算器１７で加算され、相関パワ
ーを得る。ステップＳＴ７において、算出された相関パ
ワーが同期判定器１９によって相関しきい値と比較され
る。もし、相関パワーがしきい値以上であれば、ステッ
プＳＴ８においてその位置で同期がとれたものとする。
これに対し、相関パワーがしきい値以下であれば、その
位置での同期はないものとしてステップＳＴ１へ戻り、
蓄積器１０，１１及びカウンタ７をリセットし、次の相
関位置へ移行する。なお、同期判定の方法としては、前
記のようにしきい値以上の相関パワーが得られたら、即
同期とみなす場合の他、相関結果を記録しておき、全範
囲に渡る同期調査が終わった時点で、最も相関パワーの
高い位置を同期位置とする方法等もある。以上のよう
に、この第１の実施例では、受信信号１をレジスタに蓄
積することなく、１相関区間の受信信号１で１つの相関
結果を得るため、回路規模が小さく、演算速度も高速を
要求されないという利点がある。しかも、試行相関（短
区間相関）を行うことで、同期捕捉にかかる時間を短縮
できる。In step ST4, the calculated trial correlation power is compared with the trial correlation threshold value by the trial correlation determiner 18. If the trial correlation power is less than or equal to the threshold value, it is considered that there is no possibility of synchronization at that position, the process returns to step ST1, the accumulators 10 and 11 and the counter 7 are reset and the next correlation position is entered. To do. As this transfer method, for example, as shown in FIG. 3, a method of delaying one PN code generated by the PN code generator 6 is used. If it is assumed that a 1-chip interval is set for correlation determination or the like, the received signal 1 advances by 1 chip, so the PN code generated remains unchanged. On the other hand, step ST4
In, if the trial correlation power is equal to or more than the threshold value, the process proceeds to step ST5, and the correlation calculation is further continued. The accumulators 10 and 11 continue the accumulation as it is. Step S
At T6, when the count value of the counter 7 reaches the correlation number, the counter 7 notifies each of the accumulators 10 and 11.
The accumulators 10 and 11 send the accumulated results to the squarers 13 and 15, and the squared results are added by the adder 17 to obtain the correlation power. In step ST7, the calculated correlation power is compared with the correlation threshold value by the synchronization determiner 19. If the correlation power is greater than or equal to the threshold value, it is determined that synchronization has been achieved at that position in step ST8.
On the other hand, if the correlation power is less than or equal to the threshold value, it is determined that there is no synchronization at that position, and the process returns to step ST1.
The accumulators 10 and 11 and the counter 7 are reset, and the operation moves to the next correlation position. As a method for determining the synchronization, when the correlation power equal to or more than the threshold value is obtained as described above, the correlation result is recorded in addition to the case where it is regarded as the immediate synchronization, and when the synchronization investigation is completed over the entire range. Then, there is also a method of setting the position having the highest correlation power as the synchronization position. As described above, in this first embodiment, one correlation result is obtained with the received signal 1 in one correlation section without accumulating the received signal 1 in the register, so that the circuit scale is small and the operation speed is high. It has the advantage that it is not required. Moreover, the time required for synchronization acquisition can be shortened by performing trial correlation (short section correlation).
【００１４】第２の実施例 図４は、本発明の第２の実施例の同期捕捉方法に用いら
れる並列方式の同期捕捉回路の機能ブロック図である。
この並列方式の同期捕捉回路では、相関器を並列に設け
たもので、この例では並列数が３である。なお、第１の
実施例の図１中の要素と共通の要素には共通の符号が付
されている。この同期捕捉回路では、第１の実施例と同
様の搬送波発生器２、π／２位相回転器３、及び乗算器
４，５を有し、その出力側に３個のパワー算出手段であ
るパワー算出器２０−１，２０−２，２０−３が接続さ
れている。各パワー算出器２０−１，２０−２，２０−
３は、第１の実施例のカウンタ７，乗算器８，９、蓄積
器１０，１１、２乗器１２，１３，１４，１５、及び加
算器１６，１７でそれぞれ構成されている。但し、ＰＮ
コード発生器６から発生するＰＮコードは、パワー算出
器２０−１には直接供給されるが、パワー算出器２０−
２には遅延器２１によって１チップ分遅延させられたＰ
Ｎコードが入力され、更にパワー算出器２０−３には遅
延器２２によって更に１チップ分遅延させられたＰＮコ
ード（即ち、２チップ分遅延させられたＰＮコード）が
入力されるようになっている。３個のパワー算出器２０
−１〜２０−３の出力側には、試行相関判定手段である
試行相関判定器１８Ａと、同期判定手段である同期判定
器１９Ａが接続されている。そして、各パワー算出器２
０−１〜２０−３で算出された試行相関パワーが全て試
行相関判定器１８Ａへ送出され、全ての試行相関パワー
がしきい値以下の場合のみ次セットの相関位置に移行
し、１つでもしきい値以上の値があれば、全てのパワー
算出器２０−１〜２０−３での相関を続行するようにな
っている。全てのパワー算出器２０−１〜２０−３で続
行された相関パワーは、全て同期判定器１９Ａへ送出さ
れ、相関パワーがしきい値以上のものがあれば即同期捕
捉される。あるいは、全範囲より最も強い位置を選択し
て同期位置とするようになっている。 Second Embodiment FIG. 4 is a functional block diagram of a parallel-type synchronization acquisition circuit used in the synchronization acquisition method according to the second embodiment of the present invention.
In this parallel type synchronization acquisition circuit, correlators are provided in parallel, and the number of parallels is three in this example. Elements common to those in the first embodiment shown in FIG. 1 are designated by common reference numerals. This synchronization acquisition circuit has a carrier wave generator 2, a π / 2 phase rotator 3, and multipliers 4 and 5 similar to those of the first embodiment, and the output side thereof has three power calculation means, ie, power. The calculators 20-1, 20-2, 20-3 are connected. Each power calculator 20-1, 20-2, 20-
3 is composed of the counter 7, the multipliers 8 and 9, the accumulators 10 and 11, the squarers 12, 13, 14 and 15, and the adders 16 and 17 of the first embodiment, respectively. However, PN
The PN code generated from the code generator 6 is directly supplied to the power calculator 20-1, but the power calculator 20-
2 has P delayed by one chip by the delay device 21.
The N code is input, and further, the PN code delayed by one chip by the delay unit 22 (that is, the PN code delayed by two chips) is input to the power calculator 20-3. There is. 3 power calculators 20
The output side of -1 to 20-3 is connected to a trial correlation determiner 18A which is a trial correlation determining means and a synchronization determiner 19A which is a synchronization determining means. And each power calculator 2
All the trial correlation powers calculated in 0-1 to 20-3 are sent to the trial correlation determiner 18A, and only when all the trial correlation powers are equal to or less than the threshold value, the correlation position moves to the next set, and even one is set. If there is a value equal to or larger than the threshold value, the correlations in all the power calculators 20-1 to 20-3 are continued. All the correlation powers continued by all the power calculators 20-1 to 20-3 are sent to the synchronization determiner 19A, and if there is a correlation power equal to or larger than the threshold value, the synchronization is immediately captured. Alternatively, the position that is the strongest in the entire range is selected as the synchronization position.
【００１５】図５は、図４の同期捕捉回路における並列
処理方式の説明図であり、この図を参照しつつ本実施例
の同期捕捉方法を説明する。アンテナより受信された受
信信号１は、第１の実施例と同様に、搬送波発生器２、
π／２位相回転器２、及び乗算器４，５によってベース
バンド帯域に変換され、Ｉ相信号Ｒｉ及びＱ相信号Ｒｑ
が各パワー算出器２０−１〜２０−３へ送られる。ＰＮ
コード発生器６から発生したＰＮコードは、パワー算出
器２０−１に入力されると共に、遅延器２１によって１
チップ分遅延させられたＰＮコードがパワー算出器２０
−２に入力され、更に遅延器２２によって２チップ分遅
延させられたＰＮコードがパワー算出器２０−３に入力
される。各パワー算出器２０−１〜２０−３では、１チ
ップづつずれた相関ＰＮ値１，２，３を用いて相関をと
る。試行相関判定器１８Ａにおいて、３つの試行相関パ
ワーの全てがしきい値以下であれば、このセットでの試
行相関を終わらせ、次のセットに移る。次のセットの相
関ＰＮ値は、３つ遅らせた値で行う。相関ＰＮ値１にお
いてＰＮ６３で終わったとすると、次のセットはＰＮ６
１からとなる。次のセットにおいて、３つの試行相関パ
ワーのうち１つでもしきい値以上のものがあれば、パワ
ー算出器２０−１〜２０−３において３つとも相関演算
を続行させ、同期判定器１９Ａで同期の判定を行う。FIG. 5 is an explanatory diagram of a parallel processing system in the synchronization acquisition circuit of FIG. 4, and the synchronization acquisition method of this embodiment will be described with reference to this figure. The received signal 1 received from the antenna is the carrier wave generator 2, as in the first embodiment.
The I-phase signal Ri and the Q-phase signal Rq are converted into a baseband band by the π / 2 phase rotator 2 and the multipliers 4 and 5.
Is sent to each of the power calculators 20-1 to 20-3. PN
The PN code generated from the code generator 6 is input to the power calculator 20-1 and also set to 1 by the delay unit 21.
The PN code delayed by the chip is the power calculator 20.
-2, and the PN code delayed by two chips by the delay unit 22 is input to the power calculator 20-3. In each of the power calculators 20-1 to 20-3, the correlation is obtained by using the correlation PN values 1, 2, and 3 which are shifted by one chip. If all of the three trial correlation powers are equal to or less than the threshold value in the trial correlation determiner 18A, the trial correlation in this set is terminated and the process proceeds to the next set. The next set of correlation PN values are delayed by three. If the correlation PN value 1 ends with PN63, the next set is PN6.
It starts from 1. In the next set, if at least one of the three trial correlation powers is equal to or higher than the threshold value, the power calculators 20-1 to 20-3 continue the correlation calculation for all three, and the synchronization determiner 19A Determine the synchronization.
【００１６】以上のように、この第２の実施例では、３
個のパワー算出器２０−１〜２０−３によって並列に相
関処理を行うので、並列数分の相関が同時に可能となっ
て同期捕捉にかかる時間を短くできる。本実施例のよう
に並列数を３とすると、同期捕捉時間は、およそ３分の
１となる。なお、本発明は上記実施例に限定されず、種
々の変形が可能である。その変形例としては、例えば次
のようなものがある。 （ａ） 図１及び図４の同期捕捉回路は、個別回路で構
成されているが、プロセッサを用いたプログラム制御等
によって同期捕捉処理を実行するようにしてもよい。 （ｂ） 図１では、試行相関判定を行った後に同期判定
を行うようにしているが、試行相関判定を行わずに同期
判定処理のみを行うようにしてもよい。これにより、よ
り簡単な同期捕捉回路を用いた同期捕捉処理が可能とな
る。As described above, in the second embodiment, 3
Since the correlation processing is performed in parallel by the power calculators 20-1 to 20-3, it is possible to perform the correlation for the parallel number at the same time and shorten the time required for the synchronization acquisition. If the number of parallel connections is 3 as in this embodiment, the synchronization acquisition time will be about one third. The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (A) Although the synchronization acquisition circuit of FIGS. 1 and 4 is configured by an individual circuit, the synchronization acquisition process may be executed by program control using a processor or the like. (B) In FIG. 1, the synchronization determination is performed after the trial correlation determination is performed, but only the synchronization determination process may be performed without performing the trial correlation determination. As a result, it becomes possible to perform the synchronization acquisition processing using a simpler synchronization acquisition circuit.
【００１７】[0017]
【発明の効果】以上詳細に説明したように、第１の発明
によれば、受信信号をレジスタに蓄積することなく、１
相関区間の受信信号で１つの相関結果を得るようにして
いるので、同期捕捉回路において短時間に膨大な計算を
必要とせず、回路規模の小さなハードを用いることがで
き、更に演算速度も高速を要求されない同期捕捉処理が
可能となる。第２の発明によれば、試行相関（短区間相
関）演算を行った後に相関演算を行うようにしたので、
同期捕捉時間を短縮できる。第３の発明によれば、パワ
ー算出手段を並列に動作させて相関演算を並列処理する
ようにしたので、同期捕捉時間を短縮できる。As described in detail above, according to the first aspect of the invention, the received signal can be stored in the register without being accumulated.
Since one correlation result is obtained from the received signal in the correlation section, the synchronization acquisition circuit does not require a huge amount of calculation in a short time, hardware with a small circuit scale can be used, and the calculation speed is high. Unnecessary synchronization acquisition processing becomes possible. According to the second invention, since the correlation calculation is performed after the trial correlation (short section correlation) calculation is performed,
The synchronization acquisition time can be shortened. According to the third invention, the power calculation means is operated in parallel to perform the parallel processing of the correlation calculation, so that the synchronization acquisition time can be shortened.
【図１】本発明の第１の実施例の同期捕捉方法に用いら
れる同期捕捉回路の機能ブロック図である。FIG. 1 is a functional block diagram of a synchronization acquisition circuit used in a synchronization acquisition method according to a first embodiment of the present invention.
【図２】図１の同期捕捉回路を用いた同期捕捉方法の処
理手順を示すフローチャートである。FIG. 2 is a flowchart showing a processing procedure of a synchronization acquisition method using the synchronization acquisition circuit of FIG.
【図３】本発明の第１の実施例の原理説明図である。FIG. 3 is an explanatory view of the principle of the first embodiment of the present invention.
【図４】本発明の第２の実施例の同期捕捉方法に用いら
れる並列方式の同期捕捉回路の機能ブロック図である。FIG. 4 is a functional block diagram of a parallel-type synchronization acquisition circuit used in the synchronization acquisition method according to the second embodiment of the present invention.
【図５】図４の同期捕捉回路を用いた同期捕捉の並列処
理方式の説明図である。5 is an explanatory diagram of a parallel processing system of synchronization acquisition using the synchronization acquisition circuit of FIG.
１ 受信信号 ２ 搬送波発生器 ３ π／２位相回転器 ４，５ 乗算器 ６ ＰＮコード発生器 ７ カウンタ ８，９ 乗算器 １０，１１ 蓄積器 １２，１３，１４，１５ ２乗器 １６，１７ 加算器 １８，１８Ａ 試行相関判定器 １９，１９Ａ 同期判定器 ２０−１，２０−２，２０−３ パワー算出器 ２１，２２ 遅延器 1 Received Signal 2 Carrier Wave Generator 3 π / 2 Phase Rotator 4,5 Multiplier 6 PN Code Generator 7 Counter 8,9 Multiplier 10,11 Accumulator 12,13,14,15 Squarer 16,17 Addition Unit 18, 18A Trial correlation determiner 19, 19A Synchronization determiner 20-1, 20-2, 20-3 Power calculator 21, 22 Delay device
Claims (3)
を同一周波数帯域内に多重化して通信を行うコード分割
多元接続通信方式に基づく移動通信システムにおいて、 受信信号をベースバンド帯域に変換してベースバンド受
信信号を出力するベースバンド帯域変換手段と、所望局
の所望位置での擬似コードを発生させる擬似コード発生
手段と、前記ベースバンド受信信号と前記擬似コードと
を掛け合わせてその乗算結果を累積する乗算・累積手段
と、前記乗算・累積手段での累積数をカウントするカウ
ント手段と、前記乗算・累積手段における同相成分の累
積結果と直交成分の累積結果とをそれぞれ２乗し、それ
らの２乗結果を加算して相関パワーを算出する２乗加算
手段と、前記相関パワーより同期判定を行う同期判定手
段とを用い、 ある相関位置において前記乗算・累積手段によって相関
演算を行い、前記カウント手段のカウント値が相関数に
達した時点で、前記２乗加算手段によって相関パワーを
算出し、更に１チップずれた相関位置において相関パワ
ーを算出し、同様の動作を繰り返し行うことで、前記同
期判定手段によって同期位置を判定させることを特徴と
する同期捕捉方法。1. In a mobile communication system based on a code division multiple access communication system in which signals modulated by spread spectrum are multiplexed in the same frequency band for communication, a received signal is converted into a baseband band and baseband reception is performed. Baseband band converting means for outputting a signal, pseudocode generating means for generating a pseudocode at a desired position of a desired station, and multiplication for multiplying the baseband received signal and the pseudocode and accumulating the multiplication result. -Cumulative means, counting means for counting the cumulative number in the multiplying / accumulating means, squared cumulative result of in-phase component and cumulative result of quadrature component in the multiplying / accumulating means, and squaring results thereof Is used to calculate the correlation power, and a synchronization determination means for performing synchronization determination based on the correlation power is used. Correlation calculation is performed by the multiplication / accumulation unit at the relation position, and when the count value of the counting unit reaches the correlation number, the correlation power is calculated by the square addition unit, and the correlation power is further shifted by one chip. A synchronization acquisition method characterized in that the synchronization determination means determines the synchronization position by calculating power and repeating the same operation.
擬似コード発生手段、乗算・累積手段、カウント手段、
２乗加算手段及び同期判定手段と、 前記乗算・累積手段によって求めた同相成分の試行相関
累積結果と直交成分の試行相関累積結果とをそれぞれ２
乗し、それらの２乗結果を加算して試行相関パワーを算
出する試行２乗加算手段と、 前記試行相関パワーより試行相関判定を行う試行相関判
定手段とを用い、 ある相関位置において前記乗算・累積手段によって相関
演算を行い、前記カウント手段によって相関数より短い
試行相関数をカウントさせ、そのカウント値が試行相関
数に達した時点で、前記試行２乗加算手段によって試行
相関パワーを算出し、その算出結果を前記試行相関判定
手段で判定して該算出結果がしきい値以上の場合のみ請
求項１の相関演算を行わせることを特徴とする同期捕捉
方法。2. The baseband band conversion means according to claim 1,
Pseudo code generation means, multiplication / accumulation means, counting means,
The square addition means and the synchronization determination means, and the trial correlation accumulation result of the in-phase component and the trial correlation accumulation result of the orthogonal component, which are obtained by the multiplication / accumulation means, are 2 respectively.
A trial square addition means for multiplying the squared results and adding the squared results to calculate trial correlation power, and a trial correlation determination means for performing trial correlation determination from the trial correlation power are used. Correlation calculation is performed by the accumulating unit, the trial correlation number shorter than the correlation number is counted by the counting unit, and when the count value reaches the trial correlation number, the trial square power is calculated by the trial square addition unit, The synchronization acquisition method, wherein the trial correlation determining means determines the calculation result, and the correlation calculation according to claim 1 is performed only when the calculation result is equal to or larger than a threshold value.
び擬似コード発生手段と、 請求項１の乗算・累積手段、２乗加算手段及びカウント
手段と請求項２の試行２乗加算手段とでそれぞれ構成さ
れる複数のパワー算出手段と、 前記複数のパワー算出手段から出力される複数の相関パ
ワーより同期判定を行う同期判定手段と、 前記複数のパワー算出手段から出力される複数の試行相
関パワーより試行相関判定を行う試行相関判定手段とを
用い、 前記擬似コード発生手段から発生する擬似コードを１チ
ップづつずらして前記複数のパワー算出手段に与え、そ
れらのパワー算出手段を並列に動作させることを特徴と
する同期捕捉方法。3. A baseband band conversion means and a pseudo code generation means according to claim 1, a multiplication / accumulation means, a square addition means and a counting means according to claim 1, and a trial square addition means according to claim 2. A plurality of configured power calculation means, a synchronization determination means for performing synchronization determination based on a plurality of correlation powers output from the plurality of power calculation means, and a plurality of trial correlation powers output from the plurality of power calculation means Using trial correlation determining means for performing trial correlation determination, the pseudo code generated from the pseudo code generating means is shifted by one chip and given to the plurality of power calculating means, and the power calculating means are operated in parallel. Characteristic synchronization acquisition method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16726894A JP2895398B2 (en) | 1994-07-20 | 1994-07-20 | Synchronous acquisition method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16726894A JP2895398B2 (en) | 1994-07-20 | 1994-07-20 | Synchronous acquisition method |
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| Publication Number | Publication Date |
|---|---|
| JPH0832547A true JPH0832547A (en) | 1996-02-02 |
| JP2895398B2 JP2895398B2 (en) | 1999-05-24 |
Family
ID=15846594
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16726894A Expired - Fee Related JP2895398B2 (en) | 1994-07-20 | 1994-07-20 | Synchronous acquisition method |
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| Country | Link |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6487237B1 (en) | 1998-01-28 | 2002-11-26 | Matsushita Electric Industrial Co., Ltd. | Spreading code estimating apparatus and spreading code estimating method |
| WO2003036836A1 (en) * | 2001-10-18 | 2003-05-01 | Linkair Communications,Inc. | Method and device for the capturing of down synchronization in the cdma communication system |
| JP2006523970A (en) * | 2003-04-15 | 2006-10-19 | ノヴァテル・インコーポレイテッド | Apparatus and method for performing pulse waveform measurement |
| US7233613B2 (en) | 2000-04-28 | 2007-06-19 | Fujitsu Limited | Synchronization establishing device, method of establishing synchronization, and receiver |
| JP2011525729A (en) * | 2008-06-02 | 2011-09-22 | ハリス コーポレイション | Adaptive correlation |
| CN109633711A (en) * | 2018-12-24 | 2019-04-16 | 长沙北斗产业安全技术研究院有限公司 | A kind of super large dynamic, highly sensitive Spread Spectrum TT&C baseband receiving method and device |
-
1994
- 1994-07-20 JP JP16726894A patent/JP2895398B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6487237B1 (en) | 1998-01-28 | 2002-11-26 | Matsushita Electric Industrial Co., Ltd. | Spreading code estimating apparatus and spreading code estimating method |
| US7233613B2 (en) | 2000-04-28 | 2007-06-19 | Fujitsu Limited | Synchronization establishing device, method of establishing synchronization, and receiver |
| WO2003036836A1 (en) * | 2001-10-18 | 2003-05-01 | Linkair Communications,Inc. | Method and device for the capturing of down synchronization in the cdma communication system |
| JP2006523970A (en) * | 2003-04-15 | 2006-10-19 | ノヴァテル・インコーポレイテッド | Apparatus and method for performing pulse waveform measurement |
| US8442097B2 (en) | 2003-04-15 | 2013-05-14 | Novatel Inc. | Apparatus for and method of making pulse-shape measurements |
| US8467433B2 (en) | 2003-04-15 | 2013-06-18 | Novatel Inc. | Apparatus for and method of making pulse-shape measurements |
| JP2011525729A (en) * | 2008-06-02 | 2011-09-22 | ハリス コーポレイション | Adaptive correlation |
| CN109633711A (en) * | 2018-12-24 | 2019-04-16 | 长沙北斗产业安全技术研究院有限公司 | A kind of super large dynamic, highly sensitive Spread Spectrum TT&C baseband receiving method and device |
| CN109633711B (en) * | 2018-12-24 | 2020-12-11 | 长沙北斗产业安全技术研究院有限公司 | Ultra-large dynamic and high-sensitivity spread spectrum measurement and control baseband receiving method and device |
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