JPH08293671A - Connection of circuit board - Google Patents
Connection of circuit boardInfo
- Publication number
- JPH08293671A JPH08293671A JP7120690A JP12069095A JPH08293671A JP H08293671 A JPH08293671 A JP H08293671A JP 7120690 A JP7120690 A JP 7120690A JP 12069095 A JP12069095 A JP 12069095A JP H08293671 A JPH08293671 A JP H08293671A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- electrodes
- positioning
- electrode
- mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Landscapes
- Structure Of Printed Boards (AREA)
- Combinations Of Printed Boards (AREA)
- Supply And Installment Of Electrical Components (AREA)
- Multi-Conductor Connections (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、回路基板の接続方法に
関し、特に、ハイブリッドＩＣ等の厚膜回路基板を回路
基板にフェイスダウンボンディング法により電気的に接
続する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting circuit boards, and more particularly to a method for electrically connecting a thick film circuit board such as a hybrid IC to a circuit board by face down bonding.
【０００２】[0002]
【従来の技術】近年、車載用電子制御製品は、高機能小
型化が求められている。特に、マイクロコンピュータを
搭載した製品では、機能が向上するに伴い、回路基板が
大型化する傾向にある。この回路基板の小型化のため
に、多層基板が用いられているが、従来の単層基板に比
べてコストが非常に高く、周辺回路を含めた大型基板で
は製品のコストアップを招いてしまう。そこで、低コス
ト化のために、多層配線の必要な部分のみ多層基板と
し、周辺回路部はコストの低い単層基板で回路基板を構
成する方法が用いられている。2. Description of the Related Art In recent years, in-vehicle electronic control products have been required to have high functionality and miniaturization. In particular, in a product equipped with a microcomputer, the circuit board tends to increase in size as the function is improved. A multilayer board is used to reduce the size of the circuit board, but the cost is much higher than that of a conventional single-layer board, and a large board including peripheral circuits causes an increase in product cost. Therefore, in order to reduce the cost, a method is used in which only a portion where multilayer wiring is required is a multilayer substrate and the peripheral circuit section is a single-layer substrate having a low cost.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記方
法では、基板間の位置決めを行う手段が確立されていな
いために、多層基板の多数の電気的接続箇所を正確に接
続することができず、電気的接続箇所に接続不良が発生
したり、また、その位置決めのために多くの時間を要す
るという問題がある。However, in the above method, since a means for positioning between the substrates is not established, it is not possible to accurately connect a large number of electrical connection points of the multilayer substrate, and the electrical There is a problem that a connection failure occurs at a dynamic connection point, and it takes a lot of time to position it.
【０００４】従って、本発明の目的は、目視にて容易に
基板間の位置決めを行うことのできる回路基板の接続方
法を提供することである。Therefore, it is an object of the present invention to provide a method of connecting circuit boards, which enables easy visual positioning of the boards.
【０００５】[0005]
【課題を解決するための手段】上記の課題を解決するた
め、本発明の構成は、第一の回路基板上に、該第一の回
路基板より小さい第二の回路基板を電気的に接続する回
路基板の接続方法であって、第一の回路基板と第二の回
路基板のうち少なくとも第一の回路基板の所定の位置に
マークを設け、第一の回路基板のマークと、第二の回路
基板の縁部或いはマークとを位置合わせすることによ
り、第一の回路基板と第二の回路基板との位置決めを行
い、第一の回路基板の上面に形成された接続ランドと、
第二の回路基板の下面に形成された接続電極とを電気的
に接続することを特徴とする。In order to solve the above problems, according to the structure of the present invention, a second circuit board smaller than the first circuit board is electrically connected to the first circuit board. A circuit board connecting method, wherein a mark is provided at a predetermined position of at least the first circuit board of the first circuit board and the second circuit board, and the mark of the first circuit board and the second circuit board are provided. Positioning the first circuit board and the second circuit board by aligning the edge portion or the mark of the board, and the connection land formed on the upper surface of the first circuit board,
It is characterized in that it is electrically connected to a connection electrode formed on the lower surface of the second circuit board.
【０００６】また、第二の発明の構成は、第一の回路基
板のマーク及び第二の回路基板のマークは電極で構成さ
れ、互いにはんだ付けされて電気的に接続されたことを
特徴とする。Further, the structure of the second invention is characterized in that the mark of the first circuit board and the mark of the second circuit board are composed of electrodes, which are soldered to each other and electrically connected. .
【０００７】第三の発明の構成は、第二の回路基板の接
続電極の厚さは、１０μｍ以上１００μｍ以下であるこ
とを特徴とする。A third aspect of the invention is characterized in that the thickness of the connection electrode of the second circuit board is 10 μm or more and 100 μm or less.
【０００８】第四の発明の構成は、第二の回路基板の電
極から成るマークの厚さは、１０μｍ以上１００μｍ以
下であることを特徴とする。The structure of the fourth invention is characterized in that the thickness of the mark composed of the electrode of the second circuit board is 10 μm or more and 100 μm or less.
【０００９】[0009]
【作用及び効果】上記構成から成る本発明の第一の作用
は、第一の回路基板のマークと第二の回路基板の縁部或
いはマークとを位置合わせすることにより、第一の回路
基板と第二の回路基板との位置決めを行うことであり、
その効果は、第一の回路基板と第二の回路基板とを容易
に位置決めすることができ、第一の回路基板の接続ラン
ドと第二の回路基板の接続電極との電気的接続を良好に
行えることである。（請求項１）The first function of the present invention having the above-described structure is that the mark of the first circuit board and the edge or mark of the second circuit board are aligned to form the first circuit board. Is to position with the second circuit board,
The effect is that the first circuit board and the second circuit board can be easily positioned, and the electrical connection between the connection lands of the first circuit board and the connection electrodes of the second circuit board is improved. It is possible. (Claim 1)
【００１０】また、第二の作用は、第一の回路基板のマ
ーク及び第二の回路基板のマークを電極で構成し、互い
にはんだ付けにより電気的に接続することであり、その
効果は、はんだ付けの際のセルフアライメント性が高ま
り、回路基板間のより正確な電気的接続を行うことがで
きると共に、その電極で構成されたマークを電気的接続
箇所として用いれば回路基板の高密度実装も実現できる
ことである。（請求項２）The second action is to form the mark on the first circuit board and the mark on the second circuit board with electrodes and electrically connect them by soldering. Self-alignment at the time of attachment is improved, more accurate electrical connection between circuit boards can be made, and high density mounting of circuit boards can be realized by using the marks made up of the electrodes as electrical connection points. It is possible. (Claim 2)
【００１１】第三の作用は、第二の回路基板の接続電極
の厚さを１０μｍ以上１００μｍ以下とすることであ
り、その効果は、回路基板間に空隙を形成することがで
きるため、その空隙に洗浄液を浸入させて空隙内を洗浄
し、回路基板間の残渣フラックスを確実に除去すること
ができ、隣接する電極間の短絡や耐電圧の低下を防止で
きることである。（請求項３）A third action is to make the thickness of the connection electrode of the second circuit board 10 μm or more and 100 μm or less. The effect thereof is that a gap can be formed between the circuit boards, so that the gap can be formed. That is, the cleaning liquid is allowed to infiltrate into the space to clean the inside of the voids, the residual flux between the circuit boards can be reliably removed, and a short circuit between adjacent electrodes and a decrease in withstand voltage can be prevented. (Claim 3)
【００１２】第四の作用は、第二の回路基板の電極から
成るマークの厚さを１０μｍ以上１００μｍ以下とする
ことであり、その効果は、接続電極及びマークの厚さを
均一にすることができるため、第一の回路基板と第二の
回路基板との電気的接続を良好に行えることである。
（請求項４）A fourth action is to make the thickness of the mark made of the electrode of the second circuit board 10 μm or more and 100 μm or less. The effect is to make the thickness of the connection electrode and the mark uniform. Therefore, good electrical connection between the first circuit board and the second circuit board can be achieved.
(Claim 4)
【００１３】[0013]
【実施例】以下、本発明を具体的な実施例に基づいて説
明する。図１は、本発明の第一実施例に用いられる上側
基板１０（第二の回路基板に相当）の構成を示したもの
であり、（ａ）はその表面１０ａ（上面に相当）の構成
を、（ｂ）はその裏面１０ｂ（下面に相当）の構成を、
（ｃ）はそのＡ−Ａ断面の構成をそれぞれ示している。
上側基板１０は、矩形状を成し、その組成は白色不透明
のセラミックから構成されている。上側基板１０の表面
１０ａには、ワイヤボンディングされた複数（図１では
４個）のＩＣ１１が搭載されており、また、表面１０ａ
の四辺に沿って、複数（図１では７個）の矩形状の位置
合わせマーク１２（第二の回路基板のマークに相当）が
設けられている。上側基板１０の裏面１０ｂには、０．
３ｍｍ角で厚さが約１００μｍの銅或いは銀から成る接
続電極１３（接続電極に相当）が所定の個数だけ設けら
れており、位置合わせマーク１２の位置に該当する裏面
１０ｂの位置に矩形状で厚さが約１００μｍの位置決め
電極１４（電極から成るマークに相当）が設けられてい
る。この位置決め電極１４の表面積は、接続電極１３の
表面積より大きく形成されている。EXAMPLES The present invention will be described below based on specific examples. FIG. 1 shows a structure of an upper substrate 10 (corresponding to a second circuit board) used in the first embodiment of the present invention, and (a) shows a structure of a surface 10a (corresponding to an upper surface) thereof. , (B) shows the structure of the back surface 10b (corresponding to the lower surface),
(C) has each shown the structure of the AA cross section.
The upper substrate 10 has a rectangular shape and its composition is composed of white opaque ceramic. A plurality of (four in FIG. 1) ICs 11 that are wire-bonded are mounted on the front surface 10a of the upper substrate 10.
A plurality of (seven in FIG. 1) rectangular alignment marks 12 (corresponding to the marks on the second circuit board) are provided along the four sides. On the back surface 10b of the upper substrate 10, 0.
A predetermined number of connection electrodes 13 (corresponding to connection electrodes) made of copper or silver having a size of 3 mm square and a thickness of about 100 μm are provided, and a rectangular shape is formed on the back surface 10 b corresponding to the position of the alignment mark 12. Positioning electrodes 14 (corresponding to marks made of electrodes) having a thickness of about 100 μm are provided. The surface area of the positioning electrode 14 is larger than that of the connection electrode 13.
【００１４】図２は、第一実施例に用いられる下側基板
２０の表面の構成を示した構造図である。下側基板２０
には、複数の搭載部品２１が組み付けられ、その右側と
左側には複数の接続電極２４ｂが形成されている。下側
基板２０の中央部には、接続電極２４ａ（接続ランドに
相当）が所定の個数だけ形成されている。接続電極２４
ａの周囲の一点鎖線は、上側基板１０の形状を示してお
り、その一点鎖線を挟んで、矩形状の位置合わせ電極２
２と位置決め電極２５とが、所定の位置に所定の個数だ
け対向して設けられている。ここで、接続電極２４ａの
表面積は、ほぼ上側基板１０の接続電極１３の表面積に
等しく、また、位置決め電極２５の表面積は、ほぼ上側
基板１０の位置決め電極１４の表面積に等しく構成され
ている。FIG. 2 is a structural diagram showing the structure of the surface of the lower substrate 20 used in the first embodiment. Lower substrate 20
, A plurality of mounting components 21 are assembled, and a plurality of connecting electrodes 24b are formed on the right and left sides thereof. A predetermined number of connection electrodes 24a (corresponding to connection lands) are formed in the central portion of the lower substrate 20. Connection electrode 24
A dashed-dotted line around a indicates the shape of the upper substrate 10, and the rectangular alignment electrode 2 is sandwiched by the dashed-dotted line.
2 and the positioning electrode 25 are provided at a predetermined position so as to face each other by a predetermined number. Here, the surface area of the connection electrode 24 a is substantially equal to the surface area of the connection electrode 13 of the upper substrate 10, and the surface area of the positioning electrode 25 is substantially equal to the surface area of the positioning electrode 14 of the upper substrate 10.
【００１５】ここで、上側基板１０と下側基板２０との
位置決め方法について説明する。まず、表面を上にして
下側基板２０を配置し、表面１０ａを上にして上側基板
１０を下側基板２０のほぼ表面中央に配置する。この
時、下側基板２０の位置合わせ電極２２は上側基板１０
の外形形状の外側に形成されているため、上側基板１０
を下側基板２０のほぼ中央に配置しても、位置合わせ電
極２２は上側基板１０の下に隠れることがなく、目視に
て十分に確認することができる。よって、下側基板２０
の位置合わせ電極２２と上側基板１０の位置合わせマー
ク１２とを合わせることにより、下側基板２０の接続電
極２４ａと上側基板１０の接続電極１３とを容易に位置
決めできると共に、下側基板２０の位置決め電極２５と
上側基板１０の位置決め電極１４とを位置決めすること
ができる。Here, a method of positioning the upper substrate 10 and the lower substrate 20 will be described. First, the lower substrate 20 is arranged with the surface thereof facing upward, and the upper substrate 10 is arranged with the surface 10a facing upward substantially at the center of the surface of the lower substrate 20. At this time, the alignment electrodes 22 on the lower substrate 20 are not aligned with the upper substrate 10.
Since it is formed outside the outer shape of the upper substrate 10,
Even if is disposed substantially in the center of the lower substrate 20, the alignment electrode 22 is not hidden under the upper substrate 10 and can be sufficiently confirmed visually. Therefore, the lower substrate 20
By aligning the alignment electrode 22 of FIG. 3 with the alignment mark 12 of the upper substrate 10, the connection electrode 24a of the lower substrate 20 and the connection electrode 13 of the upper substrate 10 can be easily positioned, and the lower substrate 20 can be positioned. The electrode 25 and the positioning electrode 14 of the upper substrate 10 can be positioned.
【００１６】上記のように上側基板１０と下側基板２０
とを位置決めした後に、接続電極２４ａと接続電極１３
及び位置決め電極２５と位置決め電極１４とをはんだ付
けを行うと、はんだが溶融している状態では、セルフア
ライメント作用がはたらき、溶融はんだの表面張力がそ
の表面積が小さくなる方向に作用する。この溶融はんだ
の表面積が最も小さくなる時は、位置決め電極２５と位
置決め電極１４とが正確に位置決めしている時である。
従って、仮に位置決め電極２５と位置決め電極１４とが
微小量でもずれていたとしても、溶融はんだの表面張力
により、位置決め電極２５と位置決め電極１４とは正し
く位置決めされる。このように、位置決め電極１４、２
５間に作用する溶融はんだの表面張力により、上側基板
１０と下側基板２０とをより正確に位置決めして電気的
に接続することができると共に、位置決め電極１４、２
５を電気的接続箇所として用いれば上側基板１０及び下
側基板２０の高密度実装を実現できる。図３は、上側基
板１０と下側基板２０とを電気的に接続した状態を示し
た図である。As described above, the upper substrate 10 and the lower substrate 20
After positioning and, the connection electrode 24a and the connection electrode 13
When the positioning electrode 25 and the positioning electrode 14 are soldered, the self-alignment action works in a state where the solder is melted, and the surface tension of the molten solder acts so that the surface area thereof becomes smaller. The surface area of the molten solder becomes the smallest when the positioning electrode 25 and the positioning electrode 14 are accurately positioned.
Therefore, even if the positioning electrode 25 and the positioning electrode 14 are deviated by a small amount, the positioning electrode 25 and the positioning electrode 14 are correctly positioned by the surface tension of the molten solder. In this way, the positioning electrodes 14, 2
The upper substrate 10 and the lower substrate 20 can be more accurately positioned and electrically connected by the surface tension of the molten solder acting between the positioning electrodes 14, 2
If 5 is used as an electrical connection point, high-density mounting of the upper substrate 10 and the lower substrate 20 can be realized. FIG. 3 is a diagram showing a state where the upper substrate 10 and the lower substrate 20 are electrically connected.
【００１７】また、上側基板１０の位置決め電極１４及
び接続電極１３の厚さを約１００μｍとしているため
に、上側基板１０と下側基板２０とを電気的に接続すれ
ば、上側基板１０と下側基板２０との間に空隙を形成す
ることができる。この空隙に洗浄液を浸入させて洗浄す
ることにより、基板間の残渣フラックスを確実に除去す
ることができ、隣接する電極間の短絡や耐電圧の低下を
防止することができる。Further, since the thickness of the positioning electrode 14 and the connecting electrode 13 of the upper substrate 10 is about 100 μm, if the upper substrate 10 and the lower substrate 20 are electrically connected, the upper substrate 10 and the lower substrate 10 can be connected. A void can be formed between the substrate 20 and the substrate 20. By infiltrating the cleaning liquid into this space for cleaning, the residual flux between the substrates can be reliably removed, and a short circuit between adjacent electrodes and a decrease in withstand voltage can be prevented.
【００１８】尚、本実施例では、上側基板１０の位置合
わせマーク１２と位置決め電極１４、下側基板２０の位
置合わせ電極２２と位置決め電極２５を矩形状で統一し
た構成としたが、それら形状は位置決めするに足る形状
であれば、円形形状や三角形形状など他の形状でもよ
く、それぞれ異なる形状でもよい。また、本実施例で
は、位置合わせ電極２２と位置決め電極２５とを分離し
て設ける構成としたが、位置合わせ電極２２と位置決め
電極２５とは連続した構成としてもよい。In this embodiment, the alignment mark 12 and the positioning electrode 14 on the upper substrate 10 and the alignment electrode 22 and the positioning electrode 25 on the lower substrate 20 are formed in a rectangular shape. Other shapes such as a circular shape and a triangular shape may be used as long as the shapes are sufficient for positioning, and different shapes may be used. Further, in this embodiment, the positioning electrode 22 and the positioning electrode 25 are separately provided, but the positioning electrode 22 and the positioning electrode 25 may be continuous.
【００１９】続いて、本発明に係わる第二実施例につい
て説明する。図４は、本発明の第二実施例に用いられる
上側基板１０の構成を示したものであり、（ａ）はその
表面１０ａの構成を、（ｂ）はその裏面１０ｂの構成
を、（ｃ）はそのＢ−Ｂ断面の構成をそれぞれ示してい
る。第一実施例と本実施例との相違は、第一実施例では
上側基板１０に位置合わせマーク１２及び位置決め電極
１４が設けられているが、第二実施例ではそのいずれも
上側基板１０に設けられていない点が特徴である。第二
実施例における上側基板１０のその他の構成は、第一実
施例と同様の構成である。Next, a second embodiment according to the present invention will be described. 4A and 4B show the structure of the upper substrate 10 used in the second embodiment of the present invention. FIG. 4A shows the structure of the front surface 10a, FIG. 4B shows the structure of the rear surface 10b, and FIG. ) Indicates the configuration of the BB cross section, respectively. The difference between the first embodiment and this embodiment is that the alignment mark 12 and the positioning electrode 14 are provided on the upper substrate 10 in the first embodiment, but both are provided on the upper substrate 10 in the second embodiment. The feature is that it is not. Other configurations of the upper substrate 10 in the second embodiment are the same as those in the first embodiment.
【００２０】図５は、第二実施例で用いられる下側基板
２０の表面の構成を示した構造図である。第一実施例と
本実施例との相違は、第一実施例では下側基板２０に位
置合わせ電極２２及び位置決め電極２５が設けられてい
るが、第二実施例ではそのいずれも上側基板１０に設け
られてなく、新たに位置合わせマーク２３が設けられて
いる点が特徴である。この位置合わせマーク２３は、上
側基板１０の外形形状とほぼ等しく、或いはやや大きめ
に四隅にカギ型に形成されている。第二実施例における
下側基板２０のその他の構成は、第一実施例と同様の構
成である。FIG. 5 is a structural view showing the structure of the surface of the lower substrate 20 used in the second embodiment. The difference between the first embodiment and this embodiment is that the lower substrate 20 is provided with the alignment electrode 22 and the positioning electrode 25 in the first embodiment, but in the second embodiment, both are provided on the upper substrate 10. The feature is that the alignment mark 23 is newly provided instead of being provided. The alignment mark 23 is formed in a key shape at the four corners, which is almost the same as the outer shape of the upper substrate 10 or slightly larger. Other configurations of the lower substrate 20 in the second embodiment are the same as those in the first embodiment.
【００２１】ここで、第二実施例における上側基板１０
と下側基板２０との位置決め方法について説明する。ま
ず、表面を上にして下側基板２０を配置し、表面１０ａ
を上にして上側基板１０を下側基板２０のほぼ表面中央
に配置する。この時、下側基板２０の位置合わせマーク
２３は上側基板１０の外形形状とほぼ等しく、或いはや
や大きめに形成されているため、上側基板１０の四隅の
縁部を位置合わせマーク２３に位置合わせする際に、目
視にて十分に確認することができる。よって、下側基板
２０の位置合わせマーク２３と上側基板１０の四隅の縁
部とを合わせることにより、下側基板２０の接続電極２
４ａと上側基板１０の接続電極１３とを容易に位置決め
することができる。Now, the upper substrate 10 in the second embodiment.
A method of positioning the lower substrate 20 with the substrate will be described. First, the lower substrate 20 is placed with the surface facing upward, and the surface 10a
The upper substrate 10 is arranged with the upper side facing upwards at approximately the center of the surface of the lower substrate 20. At this time, since the alignment marks 23 of the lower substrate 20 are formed to be substantially the same as or slightly larger than the outer shape of the upper substrate 10, the four corners of the upper substrate 10 are aligned with the alignment marks 23. At this time, it can be sufficiently confirmed visually. Therefore, by aligning the alignment marks 23 of the lower substrate 20 and the four corners of the upper substrate 10, the connection electrodes 2 of the lower substrate 20 are aligned.
4a and the connection electrode 13 of the upper substrate 10 can be easily positioned.
【００２２】上記のように上側基板１０と下側基板２０
とを位置決めした後に、接続電極２４ａと接続電極１３
とのはんだ付けを行うことにより、上側基板１０と下側
基板２０とを正確に位置決めして電気的に接続すること
ができる。図６は、上側基板１０と下側基板２０とを電
気的に接続した状態を示した図である。As described above, the upper substrate 10 and the lower substrate 20
After positioning and, the connection electrode 24a and the connection electrode 13
By soldering with, the upper substrate 10 and the lower substrate 20 can be accurately positioned and electrically connected. FIG. 6 is a diagram showing a state in which the upper substrate 10 and the lower substrate 20 are electrically connected.
【００２３】尚、上記実施例において、下側基板２０の
位置合わせマーク２３は、上側基板１０の形状の四隅に
カギ型に形成する構成としたが、必ずしも位置合わせマ
ーク２３を四隅にカギ型に形成する必要はなく、各辺に
沿って線状にマーキングする構成としてもよく、或い
は、下側基板２０に形成された配線パターンを位置合わ
せマーク２３として用いてもよい。また、本実施例で
は、上側基板１０の四隅の縁部を下側基板２０の位置合
わせマーク２３に合わせる構成としたが、必ずしも上側
基板１０の四隅の縁部を位置合わせマーク２３に合わせ
る必要はなく、例えば、上側基板１０の所定の位置に所
定のマークを設け、そのマークを下側基板２０の位置合
わせマーク２３に合わせる構成としてもよい。本実施例
では、上側基板１０及び下側基板２０に位置決め電極を
設けていないが、上側基板１０及び下側基板２０に位置
決め電極を設けて、溶融はんだによるセルフアライメン
ト作用がはたらく構成としてもよく、その位置決め電極
を電気的接続箇所として用いる構成としてもよい。In the above embodiment, the alignment marks 23 on the lower substrate 20 are formed in a key shape at the four corners of the upper substrate 10, but the alignment marks 23 are not necessarily in the four corners. It does not need to be formed, and may be configured to mark linearly along each side, or the wiring pattern formed on the lower substrate 20 may be used as the alignment mark 23. In addition, in the present embodiment, the four corners of the upper substrate 10 are aligned with the alignment marks 23 of the lower substrate 20, but the four corners of the upper substrate 10 need not necessarily be aligned with the alignment marks 23. Instead, for example, a predetermined mark may be provided at a predetermined position on the upper substrate 10 and the mark may be aligned with the alignment mark 23 on the lower substrate 20. In this embodiment, the upper substrate 10 and the lower substrate 20 are not provided with the positioning electrodes, but the upper substrate 10 and the lower substrate 20 may be provided with the positioning electrodes so that the self-alignment action by the molten solder works. The positioning electrode may be used as an electrical connection point.
【００２４】上記に示されるように、本発明によれば、
第一の回路基板のマークと第二の回路基板の縁部或いは
マークとを位置合わせし、第一の回路基板と第二の回路
基板との位置決めを行うことにより、第一の回路基板と
第二の回路基板とを容易に位置決めすることができると
共に、第一の回路基板の接続ランドと第二の回路基板の
接続電極との電気的接続を良好に行える。また、第一の
回路基板のマーク及び第二の回路基板の下面に形成され
たマークを電極で構成し、互いにはんだ付けにより電気
的に接続することにより、はんだ付けの際のセルフアラ
イメント性が高まり、回路基板間のより正確な電気的接
続を行うことができると共に、その電極で構成されたマ
ークを電気的接続箇所として用いれば回路基板の高密度
実装を実現できる。さらに、第二の回路基板の接続電極
の厚さを、１０μｍ以上１００μｍ以下とすることによ
り、回路基板間に空隙を形成することができるため、そ
の空隙に洗浄液を浸入させて空隙内を洗浄し、回路基板
間の残渣フラックスを確実に除去することができ、隣接
する電極間の短絡や耐電圧の低下を防止できる。第二の
回路基板の下面に形成された電極から成るマークの厚さ
を１０μｍ以上１００μｍ以下とすれば、接続電極及び
マークの厚さを均一にすることができるため、第一の回
路基板と第二の回路基板との電気的接続を良好に行え
る。As indicated above, according to the present invention,
By aligning the mark of the first circuit board and the edge or mark of the second circuit board and positioning the first circuit board and the second circuit board, the first circuit board and the second circuit board are aligned. The second circuit board can be easily positioned, and the electrical connection between the connection land of the first circuit board and the connection electrode of the second circuit board can be performed well. In addition, the marks on the first circuit board and the marks formed on the lower surface of the second circuit board are composed of electrodes and are electrically connected to each other by soldering, which improves self-alignment during soldering. Further, more accurate electrical connection between the circuit boards can be performed, and high density mounting of the circuit boards can be realized by using the marks formed by the electrodes as electrical connection points. Furthermore, by setting the thickness of the connection electrode of the second circuit board to be 10 μm or more and 100 μm or less, a void can be formed between the circuit boards. Therefore, a cleaning liquid can be introduced into the void to clean the inside of the void. The residual flux between the circuit boards can be surely removed, and a short circuit between adjacent electrodes and a decrease in withstand voltage can be prevented. If the thickness of the mark formed of the electrode formed on the lower surface of the second circuit board is 10 μm or more and 100 μm or less, the thickness of the connection electrode and the mark can be made uniform, so Good electrical connection with the second circuit board can be achieved.
【図１】本発明に係わる第一実施例の表面（ａ）、裏面
（ｂ）及びＡ−Ａ断面（ｃ）を示した構造図。FIG. 1 is a structural diagram showing a front surface (a), a back surface (b) and an AA cross section (c) of a first embodiment according to the present invention.
【図２】本発明に係わる第一実施例の下側基板の表面の
構成を示した構造図。FIG. 2 is a structural diagram showing the configuration of the surface of the lower substrate of the first embodiment according to the present invention.
【図３】本発明に係わる第一実施例の上側基板と下側基
板とを電気的に接続した状態を示した構造図。FIG. 3 is a structural diagram showing a state in which an upper substrate and a lower substrate of a first embodiment according to the present invention are electrically connected.
【図４】本発明に係わる第二実施例の表面（ａ）、裏面
（ｂ）及びＢ−Ｂ断面（ｃ）を示した構造図。FIG. 4 is a structural diagram showing a front surface (a), a back surface (b) and a BB cross section (c) of a second embodiment according to the present invention.
【図５】本発明に係わる第二実施例の下側基板の表面の
構成を示した構造図。FIG. 5 is a structural diagram showing a configuration of a surface of a lower substrate of a second embodiment according to the present invention.
【図６】本発明に係わる第二実施例の上側基板と下側基
板とを電気的に接続した状態を示した構造図。FIG. 6 is a structural diagram showing a state in which an upper substrate and a lower substrate of a second embodiment according to the present invention are electrically connected.
１０ 上側基板 １１ 上側基板搭載ＩＣ １２ 位置合わせマーク １３ 接続電極 １４ 裏面位置決め電極 ２０ 下側基板 ２１ 下側基板搭載部品 ２２ 下側基板位置合わせ電極 ２３ 下側基板位置合わせマーク ２４ 下側基板接続電極 ２５ 下側基板位置決め電極 10 Upper Substrate 11 Upper Substrate Mounted IC 12 Alignment Mark 13 Connection Electrode 14 Back Positioning Electrode 20 Lower Substrate 21 Lower Substrate Mounted Component 22 Lower Substrate Alignment Electrode 23 Lower Substrate Alignment Mark 24 Lower Substrate Connection Electrode 25 Lower substrate positioning electrode
Claims (4)
り小さい第二の回路基板を電気的に接続する回路基板の
接続方法であって、 前記第一の回路基板と前記第二の回路基板のうち少なく
とも前記第一の回路基板の所定の位置にマークを設け、 前記第一の回路基板の前記マークと、前記第二の回路基
板の縁部或いはマークとを位置合わせすることにより、
前記第一の回路基板と前記第二の回路基板との位置決め
を行い、 前記第一の回路基板の上面に形成された接続ランドと、
前記第二の回路基板の下面に形成された接続電極とを電
気的に接続することを特徴とする回路基板の接続方法。1. A method of connecting a circuit board, wherein a second circuit board smaller than the first circuit board is electrically connected onto the first circuit board, the method comprising: connecting the first circuit board to the first circuit board; A mark is provided at a predetermined position of at least the first circuit board of the two circuit boards, and the mark of the first circuit board and the edge portion or mark of the second circuit board are aligned with each other. Due to
Positioning the first circuit board and the second circuit board, the connection land formed on the upper surface of the first circuit board,
A method of connecting a circuit board, comprising electrically connecting to a connection electrode formed on a lower surface of the second circuit board.
第二の回路基板の前記マークは電極で構成され、互いに
はんだ付けされて電気的に接続されたことを特徴とする
請求項１に記載の回路基板の接続方法。2. The mark on the first circuit board and the mark on the second circuit board are electrodes, which are soldered to each other and electrically connected to each other. A method for connecting the described circuit board.
は、１０μｍ以上１００μｍ以下であることを特徴とす
る請求項１または請求項２に記載の回路基板の接続方
法。3. The method for connecting a circuit board according to claim 1, wherein the thickness of the connection electrode of the second circuit board is 10 μm or more and 100 μm or less.
ークの厚さは、１０μｍ以上１００μｍ以下であること
を特徴とする請求項３に記載の回路基板の接続方法。4. The circuit board connecting method according to claim 3, wherein the thickness of the mark formed of the electrodes of the second circuit board is 10 μm or more and 100 μm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7120690A JPH08293671A (en) | 1995-04-21 | 1995-04-21 | Connection of circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7120690A JPH08293671A (en) | 1995-04-21 | 1995-04-21 | Connection of circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08293671A true JPH08293671A (en) | 1996-11-05 |
Family
ID=14792555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7120690A Pending JPH08293671A (en) | 1995-04-21 | 1995-04-21 | Connection of circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08293671A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6938335B2 (en) | 1996-12-13 | 2005-09-06 | Matsushita Electric Industrial Co., Ltd. | Electronic component mounting method |
| JP2009099915A (en) * | 2007-10-19 | 2009-05-07 | Yazaki Corp | Printed circuit board unit |
-
1995
- 1995-04-21 JP JP7120690A patent/JPH08293671A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6938335B2 (en) | 1996-12-13 | 2005-09-06 | Matsushita Electric Industrial Co., Ltd. | Electronic component mounting method |
| JP2009099915A (en) * | 2007-10-19 | 2009-05-07 | Yazaki Corp | Printed circuit board unit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6760227B2 (en) | Multilayer ceramic electronic component and manufacturing method thereof | |
| US4697204A (en) | Leadless chip carrier and process for fabrication of same | |
| KR100483403B1 (en) | Pad Patterns on Printed Circuit Boards for Display Devices | |
| JPH04216589A (en) | Connecting structure of electronic circuit | |
| JPH08236914A (en) | Solder mask for bonding pad on surface of printed wiring board | |
| JPH08293671A (en) | Connection of circuit board | |
| JP2642922B2 (en) | Printed wiring board | |
| JPH08298362A (en) | Circuit board for surface mount | |
| JP2002016330A (en) | Substrate for mounting component and its manufacturing method | |
| JPH08130361A (en) | Printed wiring board | |
| JPH02301725A (en) | Soldered terminal | |
| JPS63283051A (en) | Substrate for hybrid integrated circuit device | |
| JPH04243187A (en) | Printed circuit board | |
| JPH07114315B2 (en) | Printed circuit board for mounting electronic components with narrow pitch electrodes | |
| JPH03225890A (en) | Printed wiring board | |
| JP2003197676A (en) | Flexible wiring substrate | |
| JPH0527252A (en) | Liquid crystal display device | |
| KR0135036Y1 (en) | Thin film type chip parts of double structure with double resistors | |
| JPH10163587A (en) | Printed board | |
| JPH06204652A (en) | Printed circuit board | |
| JP2528436B2 (en) | Manufacturing method of circuit board device | |
| JPH0548257A (en) | Manufacture of printed board | |
| JPH01297882A (en) | Printed board | |
| JPH02143491A (en) | Mounting of surface mounting component | |
| JPS63192291A (en) | Thick film wiring board |