JPH08286391A - Photomask with vernier for alignment and resolution measurement of stepper - Google Patents

Photomask with vernier for alignment and resolution measurement of stepper

Info

Publication number
JPH08286391A
JPH08286391A JP6817495A JP6817495A JPH08286391A JP H08286391 A JPH08286391 A JP H08286391A JP 6817495 A JP6817495 A JP 6817495A JP 6817495 A JP6817495 A JP 6817495A JP H08286391 A JPH08286391 A JP H08286391A
Authority
JP
Japan
Prior art keywords
pattern
resolution
vernier
measurement
photomask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6817495A
Other languages
Japanese (ja)
Inventor
Joon Hwang
ジュン ホワング
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of JPH08286391A publication Critical patent/JPH08286391A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70641—Focus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE: To secure a sufficient space to form relatively different various patterns and a vernier by reducing the size of an area occupied by it in the vernier to measure accuracy of positioning, resolution, a focus or the like at stepper using time in manufacture of a semiconductor element. CONSTITUTION: In manufacture of a semiconductor element using a stepper, a photomask having a vernier to measure prescribed accuracy at positioning time at exposure time, is intensively arranged and formed by gathering a prescribed automatic positioning measuring pattern 5, a resolution and focus measuring pattern 6 and naked eye positioning measuring patterns 7 in a prescribed part in a scribe lane 2 of a wafer so that the size of an area occupied by itself becomes minimum.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は、半導体素子の製造時
に、ステッパ使用において、ホトマスクの投影パターン
の位置合せのために、マスクパターンの位置合せ精度、
解像度、焦点具合（ピント）などを測定するためのバー
ニアを有するホトマスクに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask pattern alignment accuracy for aligning a projection pattern of a photomask when a semiconductor device is manufactured and a stepper is used.
The present invention relates to a photomask having a vernier for measuring resolution, focus, and the like.

【０００２】[0002]

【従来の技術】一般的に、半導体素子の製造におけるホ
トリソグラフィ工程において、マスクパターンを半導体
ウエハの感光膜に露光する方法のうち、ホトマスクを感
光膜に直接重ね合わせる密着露光法では、接触転写（co
ntact printing）を行うため、数回の継続的使用後には
ホトマスクが毀損される欠点があった。この問題を避け
るために、投影転写（projection printing）を行う投
影露光法が主に用いられて来ており、この方法に用いる
マスク（またはレチクル）は、試料と直接に接触しない
ため、擦傷などの機械的劣化現象がないので、繰り返し
て用いることができる。ここで、上記の投影露光方法に
おいて、マスクは個別的な回路配置を含む場合もある
し、回路配置の一部分に対するものである場合もあり、
後者の場合、マスクのパターンは縮小されてウエハ上の
小区域に順次焦点が合わせられて露光転写され、精密な
ステップアンドリピート（step-and-repeat）工程によ
ってウエハ上に回路配置が形成される。この縮小投影露
光方法の場合、ステッパにおけるウエハの移動、パター
ンの位置合せ、露光器の焦点合せ、および感光膜の解像
度などの精密さは、高集積度の素子を製造するに当たり
非常に重要な事項である。2. Description of the Related Art Generally, in a photolithography process for manufacturing a semiconductor device, among the methods for exposing a mask pattern on a photosensitive film of a semiconductor wafer, a contact transfer (contact transfer) method in which a photomask is directly superposed on the photosensitive film is used. co
ntact printing) is performed, so that the photomask is damaged after continuous use several times. In order to avoid this problem, a projection exposure method for performing projection printing has been mainly used. Since the mask (or reticle) used in this method does not come into direct contact with the sample, scratches, etc. Since it has no mechanical deterioration phenomenon, it can be used repeatedly. Here, in the above projection exposure method, the mask may include an individual circuit arrangement, or may be a part of the circuit arrangement,
In the latter case, the pattern of the mask is reduced and sequentially exposed and transferred to small areas on the wafer, and a circuit arrangement is formed on the wafer by a precise step-and-repeat process. . In this reduction projection exposure method, precision such as wafer movement in a stepper, pattern alignment, exposure tool focusing, and photosensitive film resolution is a very important factor in manufacturing highly integrated devices. Is.

【０００３】図２は、従来のバーニア（精度測定用微細
パターン）を有するレチクルの平面図であって、これを
参照して従来の技術を考察する。レチクル１は、大きい
セル領域（作動素子領域）３とその周辺にあるスクライ
ブレイン（scribe lane 切りしろ）２で構成され、解像
度および焦点測定用のパターン４、自動位置合せ測定用
のバーニア４、肉眼測定用のバーニア４等が上記スクラ
イブレイン２内の予定された部位にそれぞれ形成されて
いる。FIG. 2 is a plan view of a reticle having a conventional vernier (fine pattern for accuracy measurement), and the conventional technique will be considered with reference to this. The reticle 1 is composed of a large cell area (actuator area) 3 and a scribe lane 2 around the cell area, and has a pattern 4 for resolution and focus measurement, a vernier 4 for automatic alignment measurement, and a naked eye. Measuring verniers 4 and the like are formed at predetermined sites in the scribe rain 2.

【０００４】[0004]

【発明が解決しようとする課題】すなわち、上記のとお
り測定用のバーニアパターン、特に解像度および焦点測
定用のパターン、自動位置合せ測定用のバーニア、肉眼
位置合せ測定用のバーニアがスクライブレイン内でそれ
ぞれ固有の領域を有しており、これは素子の高集積化に
当たって各種のパターンおよびバーニアを形成すべき十
分な空間の確保を難しくする問題点をもたらす。That is, as described above, a vernier pattern for measurement, particularly a pattern for resolution and focus measurement, a vernier for automatic alignment measurement, and a vernier for naked eye alignment measurement are respectively provided in the scriberain. It has its own region, which poses a problem that it is difficult to secure a sufficient space for forming various patterns and vernier in high integration of the device.

【０００５】したがって、上記問題点を解決するために
案出したこの発明は、従来のバーニアの長所をそのまま
維持しながらも、ステッパにおける位置合せ精度および
解像度と焦点の測定が可能でありながら同時に自らが占
める領域の大きさを減少させることにより、相対的に異
なるいろいろなパターンおよびバーニアを形成すべき十
分な空間の確保を容易にしたバーニア配置のホトマスク
を提供することを目的とする。Therefore, the present invention devised to solve the above-mentioned problems is capable of measuring the positioning accuracy, resolution and focus of a stepper while maintaining the advantages of the conventional vernier as it is. It is an object of the present invention to provide a photomask having a vernier arrangement in which it is possible to easily secure a sufficient space for forming various relatively different patterns and vernier by reducing the size of the area occupied by the vernier.

【０００６】[0006]

【課題を解決するための手段】この発明のホトマスク
は、上記の目的を達成するために、半導体素子の製造時
に所定の寸法精度を測定するためのバーニアを、ウエハ
のスクライブレイン内の所定部位に自らが占める領域の
大きさが最小になるように、所定の自動位置合せ測定用
のパターン、解像度および焦点測定用のパターン、肉眼
位置合せ測定用のパターンを集めて集中配置した構造に
形成したものである。In order to achieve the above-mentioned object, the photomask of the present invention has a vernier for measuring a predetermined dimensional accuracy at the time of manufacturing a semiconductor device at a predetermined portion in a scribe rain of a wafer. Formed in a structure in which a predetermined pattern for automatic alignment measurement, a pattern for resolution and focus measurement, and a pattern for naked eye alignment measurement are collected and concentrated so that the size of the area occupied by itself is minimized. Is.

【０００７】[0007]

【実施例】以下、添付した図面の図２を参照しながら、
この発明に係る一実施例を詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 2 of the accompanying drawings,
An embodiment according to the present invention will be described in detail.

【０００８】図２は、ホトマスクにおけるこの発明の一
実施例によるバーニア部分の平面図であって、図面に示
すとおり、この発明は、四角形の内部ボックス（子パタ
ーン）と四角形の外部ボックス（母パターン）の二重ボ
ックスから成る自動位置合せ測定用のパターン５と、四
角形のボックスからなる解像度バー(resolution bar)の
ような解像度および焦点測定用のパターン６を最大限近
接させて集めて構成した後、多数の微細パターンの配列
から成る肉眼位置合せ測定用のパターン７を、上記自動
位置合せ測定用のパターン５と解像度および焦点測定用
のパターン６の外郭部分に、スクライブレインの横軸お
よび縦軸に沿って配列位置させて構成する。ここで、上
記のパターン５、６、７は、幅が１００μｍ以下の範囲
内に集めて設けるのがよい。FIG. 2 is a plan view of a vernier portion in a photomask according to an embodiment of the present invention. As shown in the drawing, the present invention is a rectangular inner box (child pattern) and a rectangular outer box (mother pattern). ) Double-box automatic alignment measurement pattern 5 and square box resolution bar-like resolution and focus measurement pattern 6 are assembled as close together as possible. , A macroscopic alignment measurement pattern 7 consisting of an array of a large number of fine patterns is provided on the outer portion of the automatic alignment measurement pattern 5 and the resolution and focus measurement pattern 6 on the horizontal and vertical axes of the scribe rain. Are arranged along the line. Here, it is preferable that the above-mentioned patterns 5, 6 and 7 are collectively provided within a range of a width of 100 μm or less.

【０００９】次いで、上述したこの発明のバーニアを利
用する半導体の製造工程の一実施例について考察する。Next, an example of a semiconductor manufacturing process using the above-described vernier of the present invention will be considered.

【００１０】Ｎチャンネル・フィールドストップイオン
注入工程、Ｐチャンネル・フィールドストップイオン注
入工程、ゲート領域形成工程、低ドープドレイン（ＬＤ
Ｄ）用のイオン注入工程、Ｎ+ 領域のイオン注入工程、
Ｐ+ 領域のイオン注入工程のように、主にイオン注入工
程を具備するスタック型ＤＲＡＭの製造工程では、上記
各素子の分離(isolation)工程で母パターンを含むバー
ニアを使用し、Ｎチャンネル・フィールドストップイオ
ン注入工程、Ｐチャンネル・フィールドストップイオン
注入工程、Ｎ+ 領域のイオン注入工程、Ｐ+ 領域のイオ
ン注入工程では、子パターンを予定された位置に形成さ
せて使用する。N-channel field stop ion implantation process, P-channel field stop ion implantation process, gate region formation process, low-doped drain (LD
D) ion implantation process, N + region ion implantation process,
In the manufacturing process of the stack type DRAM mainly including the ion implantation process like the ion implantation process of the P + region, the vernier including the mother pattern is used in the isolation process of each element, and the N channel field is used. In the stop ion implantation process, the P channel / field stop ion implantation process, the N + region ion implantation process, and the P + region ion implantation process, the child patterns are formed at predetermined positions and used.

【００１１】[0011]

【発明の効果】上記のとおり成るこの発明は、いろいろ
なパターンおよびバーニアを形成すべき十分な空間の確
保を容易にして、スクライブレインを効率的に活用でき
るようにし、これに従って素子の集積度を向上させるこ
とができる特有の効果がある。According to the present invention as described above, it is easy to secure a sufficient space for forming various patterns and vernier, and the scribe rain can be effectively utilized, and accordingly, the degree of integration of the device can be improved. There is a unique effect that can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】 この発明の一実施例のバーニアを有するレチ
クルの部分平面図である。FIG. 1 is a partial plan view of a reticle having a vernier according to an embodiment of the present invention.

【図２】 従来のバーニアを有するレチクルの平面図で
ある。FIG. 2 is a plan view of a reticle having a conventional vernier.

【符号の説明】[Explanation of symbols]

１…レチクル、２…スクライブレイン、３…セル領域、
４…バーニア、５…自動位置合せ測定用のパターン、６
…解像度および焦点測定用のパターン、７…肉眼位置合
せ測定用のパターン1 ... reticle, 2 ... scriberain, 3 ... cell area,
4 ... Vernier, 5 ... Pattern for automatic alignment measurement, 6
... Pattern for resolution and focus measurement, 7 ... Pattern for naked eye alignment measurement

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 半導体素子の製造時にステッパの位置合
せおよび解像度測定用のバーニアを有するホトマスクに
おいて、 ウエハのスクライブレイン内の所定の部位に、自ら占め
る領域の大きさが最小になるように、所定の自動位置合
せ測定用のパターンと、解像度および焦点測定用のパタ
ーンと、および肉眼位置合せ測定用のパターンとを集め
て配置した構造を有することを特徴とするホトマスク。1. A photomask having a vernier for aligning a stepper and measuring a resolution during manufacturing of a semiconductor device, wherein a predetermined area within a scriberain of a wafer is designed to have a minimum size of an area occupied by the predetermined area. 2. A photomask having a structure in which a pattern for automatic alignment measurement, a pattern for resolution and focus measurement, and a pattern for naked eye alignment measurement are collected and arranged. 【請求項２】 請求項１に記載のホトマスクにおいて、 上記自動位置合せ測定用のパターンと、上記解像度およ
び焦点測定用のパターンと、上記肉眼位置合せ測定用の
パターンを、幅が１００μｍ以下の範囲内に集めて設け
たことを特徴とするホトマスク。2. The photomask according to claim 1, wherein the pattern for automatic alignment measurement, the pattern for resolution and focus measurement, and the pattern for macroscopic alignment measurement have a width of 100 μm or less. A photo mask characterized by being installed inside. 【請求項３】 請求項１に記載のホトマスクにおいて、 上記肉眼位置合せ測定用のパターンは、スクライブレイ
ンの横軸および縦軸に沿って配列させた多数の微細パタ
ーンを具備することを特徴とするホトマスク。3. The photomask according to claim 1, wherein the pattern for measuring the naked eye alignment comprises a large number of fine patterns arranged along the horizontal axis and the vertical axis of the scriberain. Photo mask. 【請求項４】 請求項２に記載のホトマスクにおいて、 上記肉眼位置合せ測定用のパターンを上記自動オーバー
レイ測定用のパターンと解像度および焦点測定用のパタ
ーンの外側部分に配置させて構成したことを特徴とする
ホトマスク。4. The photomask according to claim 2, wherein the pattern for macroscopic alignment measurement is arranged outside the pattern for automatic overlay measurement and the pattern for resolution and focus measurement. And a photo mask. 【請求項５】 請求項１に記載のホトマスクにおいて、 上記自動位置合せ測定用のパターンは、四角形の内部ボ
ックスと四角形の外部ボックスの二重ボックスで成るこ
とを特徴とするホトマスク。5. The photomask according to claim 1, wherein the pattern for automatic alignment measurement is a double box including a rectangular inner box and a rectangular outer box. 【請求項６】 請求項１に記載のホトマスクにおいて、 上記解像度および焦点測定用のパターンは、四角形ボッ
クスで成る解像度バーであることを特徴とするホトマス
ク。6. The photomask according to claim 1, wherein the pattern for resolution and focus measurement is a resolution bar formed by a rectangular box.
JP6817495A 1994-03-31 1995-03-27 Photomask with vernier for alignment and resolution measurement of stepper Pending JPH08286391A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1994-6858 1994-03-31
KR1019940006858A KR0144081B1 (en) 1994-03-31 1994-03-31 Vernier

Publications (1)

Publication Number Publication Date
JPH08286391A true JPH08286391A (en) 1996-11-01

Family

ID=19380276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6817495A Pending JPH08286391A (en) 1994-03-31 1995-03-27 Photomask with vernier for alignment and resolution measurement of stepper

Country Status (4)

Country Link
JP (1) JPH08286391A (en)
KR (1) KR0144081B1 (en)
CN (1) CN1074165C (en)
DE (1) DE19511533A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7432021B2 (en) 2003-07-18 2008-10-07 Kabushiki Kaisha Toshiba Reticle, apparatus for monitoring optical system, method for monitoring optical system, and method for manufacturing reticle
US7482102B2 (en) 2003-08-27 2009-01-27 Kabushiki Kaisha Toshiba Photomask having a monitoring pattern with an asymmetrical diffraction grating that includes semi-transparent probing-phase shifters

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100442058B1 (en) * 2001-12-22 2004-07-30 동부전자 주식회사 Overlay mark and measuring method of resolution using the overlay mark

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7432021B2 (en) 2003-07-18 2008-10-07 Kabushiki Kaisha Toshiba Reticle, apparatus for monitoring optical system, method for monitoring optical system, and method for manufacturing reticle
US7812972B2 (en) 2003-07-18 2010-10-12 Kabushiki Kaisha Toshiba Reticle, apparatus for monitoring optical system, method for monitoring optical system, and method for manufacturing reticle
US7482102B2 (en) 2003-08-27 2009-01-27 Kabushiki Kaisha Toshiba Photomask having a monitoring pattern with an asymmetrical diffraction grating that includes semi-transparent probing-phase shifters
US8068213B2 (en) 2003-08-27 2011-11-29 Kabushiki Kaisha Toshiba Photomask, method of lithography, and method for manufacturing the photomask

Also Published As

Publication number Publication date
KR950027940A (en) 1995-10-18
CN1074165C (en) 2001-10-31
KR0144081B1 (en) 1998-08-17
DE19511533A1 (en) 1995-10-05
CN1117652A (en) 1996-02-28

Similar Documents

Publication Publication Date Title
US5902703A (en) Method for measuring dimensional anomalies in photolithographed integrated circuits using overlay metrology, and masks therefor
KR100831445B1 (en) Fabrication method of semiconductor integrated circuit device
US20110091797A1 (en) Superimpose photomask and method of patterning
US20090246891A1 (en) Mark forming method and method for manufacturing semiconductor device
CN110892331B (en) Method for aligning a photolithographic mask and corresponding process for manufacturing integrated circuits in a wafer of semiconductor material
CN103913960A (en) System and method for lithography alignment
US8138089B2 (en) Method and apparatus for measurement and control of photomask to substrate alignment
KR20010111048A (en) Alignment method, test method for matching, and photomask
TW464946B (en) Method and apparatus for measuring positional shift/distortion by aberration
JPH09148222A (en) Exposure method and monitor pattern
US20050042529A1 (en) Box-in-box field-to-field alignment structure
JPH11102061A (en) Photomask pattern for projection exposure, photomask for projection exposure, focusing position detecting method, focusing position control method, and manufacture of semiconductor device
KR20000047483A (en) Exposure method and device manufacturing method using the same
US4613230A (en) Wafer exposure apparatus
JP3511552B2 (en) Superposition measurement mark and measurement method
JPH08286391A (en) Photomask with vernier for alignment and resolution measurement of stepper
US5237393A (en) Reticle for a reduced projection exposure apparatus
US6841307B2 (en) Photomask making method and alignment method
CN1833205B (en) Measuring the effect of flare on line width
US6893806B2 (en) Multiple purpose reticle layout for selective printing of test circuits
US5552251A (en) Reticle and method for measuring rotation error of reticle by use of the reticle
KR20050111821A (en) Overlay mark
JPH0845810A (en) Formation of resist pattern
JP2002062635A (en) Reticle and method for producing semiconductor device
JPH05216209A (en) Photomask

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19990706