JPH08255998A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH08255998A JPH08255998A JP7058647A JP5864795A JPH08255998A JP H08255998 A JPH08255998 A JP H08255998A JP 7058647 A JP7058647 A JP 7058647A JP 5864795 A JP5864795 A JP 5864795A JP H08255998 A JPH08255998 A JP H08255998A
- Authority
- JP
- Japan
- Prior art keywords
- package
- mounting
- pad
- pin
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Supply And Installment Of Electrical Components (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、パッケージ底面から延
出されたピンを実装基板のパッドに表面実装して実装を
行うＰＧＡ等のパッケージの実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package mounting method such as PGA for mounting pins extending from the bottom surface of a package on a pad of a mounting substrate.
【０００２】近年の半導体装置は、ＱＦＰに代表される
表面実装方法が主流となっている。In recent semiconductor devices, a surface mounting method represented by QFP has become mainstream.
【０００３】[0003]
【従来の技術】図３、図４は従来例の説明図である。図
において、11はパッケージ、12はリード、13ははんだパ
ッド、14はパッド、15は実装基板、16はパッド、17はは
んだバンプである。2. Description of the Related Art FIGS. 3 and 4 are explanatory views of a conventional example. In the figure, 11 is a package, 12 is a lead, 13 is a solder pad, 14 is a pad, 15 is a mounting substrate, 16 is a pad, and 17 is a solder bump.
【０００４】従来のＱＦＰタイプ等の、リードの形状が
鳥が羽根を伸ばしたような形状のガルウィング方式のリ
ードを用いた半導体のパッケージにおいて、リードピッ
チの縮小化により、多ピン化・小型化を図って来たが、
０．５ｍｍ以下のピッチ、例えば０．３ｍｍのピッチに
なると、リードの曲がり、平坦性などの確保が非常に困
難となってきている。In a semiconductor package using a gull-wing type lead having a shape such that a bird has extended wings, such as the conventional QFP type, the lead pitch is reduced to increase the number of pins and downsize. I've been trying,
When the pitch is 0.5 mm or less, for example, 0.3 mm, it becomes very difficult to secure the bending and flatness of the leads.
【０００５】これに代わる形態として、ＰＧＡをより小
型化、縮小化したＳＰＧＡ(ShurinkPin Grid Array)タ
イプのパッケージを用い、パッケージに垂直にバットを
取り付けたような形状のピンを有するバットリード方式
が用いられようとしているが、細い径のピンがパッケー
ジに垂直に取付けられているため、ＱＦＰタイプのパッ
ケージとガルウョングリードの接合エリアに比べて、Ｓ
ＰＧＡタイプのパッケージでは、パッケージとピンの接
合エリアが極端に小さくなる。As an alternative form, a SPGA (ShurinkPin Grid Array) type package in which the PGA is made more compact and downsized is used, and a butt lead system having pins shaped like bats vertically attached to the package is used. However, since a pin with a small diameter is attached vertically to the package, S is smaller than the joining area between the QFP type package and the gallon greed.
In the PGA type package, the joint area between the package and the pin is extremely small.
【０００６】いずれにしても、リードやバンプを実装基
板のパッドにはんだ付けする際、従来はリードやパンプ
とパッドのはんだ付着面積が比較的大きかったので、リ
ードやパッドとはんだとの位置合わせが多少ずれても、
ＱＦＰの場合を図３に平面図で示すように、図３（ａ）
でパッケージ11のリード12と実装基板15上のはんだパッ
ド13の位置合わせがΔの値ずれていても、はんだパッド
13のリフローにより図３（ｂ）に示すように、セルフア
ラインでリード12とはんだパッド13の位置が修正されて
いた。In any case, when the leads or bumps are soldered to the pads of the mounting board, the lead or the bumps and the pads have a relatively large solder attachment area, so that the alignment of the leads or the pads with the solder has been relatively difficult. Even if it shifts a little,
As shown in the plan view of FIG. 3 in the case of QFP, as shown in FIG.
Even if the lead 12 of the package 11 and the solder pad 13 on the mounting substrate 15 are misaligned by Δ,
By the reflow of 13, the positions of the lead 12 and the solder pad 13 were corrected by self-alignment as shown in FIG.
【０００７】また、図４（ａ）に示すような、ＢＧＡ
（Ball Grid Array)のパッケージ11の場合には、はんだ
バンプ17が使用され、そのはんだ量が多いので、実装基
板15上のパッド16とパッケージ11のはんだバンプ17の位
置合わせずれΔがＱＦＰの場合より大きくても、図４
（ｂ）に示すようにはんだバンプ17のリフローにより実
装基板15上のパッド16とパッケージ11のはんだバンプ17
の位置がセルフアラインにより、ＱＦＰの場合よりもよ
り容易に修正することが出来る。In addition, as shown in FIG. 4 (a), a BGA
In the case of the (Ball Grid Array) package 11, since the solder bumps 17 are used and the solder amount is large, when the positional deviation Δ between the pads 16 on the mounting substrate 15 and the solder bumps 17 of the package 11 is QFP. Even larger,
As shown in (b), by reflowing the solder bumps 17, the pads 16 on the mounting substrate 15 and the solder bumps 17 of the package 11 are soldered.
The position of is self-aligned and can be corrected more easily than in the case of QFP.
【０００８】このように、パッドとはんだバンプとの場
合は、リフローによりリードとはんだバンプ以上に位置
合わせのずれが最も自然な形になろうとして、セルフア
ラインにより修正されていた。As described above, in the case of the pad and the solder bump, the misalignment of the lead and the solder bump tends to be more natural than that of the lead and the solder bump due to the reflow, and it is corrected by the self-alignment.
【０００９】[0009]
【発明が解決しようとする課題】しかし、上述のよう
に、リードピッチの縮小化により、ガルウィングリード
においても、更にＰＧＡのピンにおいても尚更、接合に
用いるはんだ量が少なくなるため、はんだ付けのリフロ
ーで生じていたセルフアライメント効果が期待できなく
なり、リードやピンの位置ずれ等による実装不良の多発
が問題となっている。However, as described above, due to the reduction of the lead pitch, the amount of solder used for joining is further reduced in the gull wing lead and the pin of PGA. The self-alignment effect that occurred in step 2 cannot be expected, and the occurrence of mounting defects due to misalignment of leads and pins has become a problem.
【００１０】本発明は、以上の点を鑑み、ＰＧＡタイプ
のパッケージによるバットリード方式を用いたピンと実
装基板のパッドとの接合において、ダミーの接合部分、
すなわちダミーとなるリード或いはダミーのばんだバン
プをパッケージ上に設け、その部分のはんだのセルフア
ライメントにより、パッドと入出力リードであるピンと
の位置ずれを制御する方法を提供することを目的とす
る。In view of the above points, the present invention provides a dummy joint portion in the joint between the pin and the pad of the mounting board using the butt-lead method in the PGA type package.
That is, it is an object of the present invention to provide a method of providing a dummy lead or a dummy bump on a package, and controlling a positional deviation between a pad and a pin which is an input / output lead by self-alignment of solder at that portion.
【００１１】[0011]
【課題を解決するための手段】図１は本発明の原理説明
図、図２は本発明の実施例の説明図である。図におい
て、１はパッケージ、２はピン、３はバンプ、４ははん
だ、５は実装基板、６は第１のパッド、７は第２のパッ
ド、８はガルウイングリードである。FIG. 1 is an explanatory view of the principle of the present invention, and FIG. 2 is an explanatory view of an embodiment of the present invention. In the figure, 1 is a package, 2 is a pin, 3 is a bump, 4 is a solder, 5 is a mounting substrate, 6 is a first pad, 7 is a second pad, and 8 is a gull wing lead.
【００１２】上記の問題点を解決する手段として、図１
（ａ）に平面図で、図１（ｂ）に断面図で、図１（ｃ）
にピン２の接合部を拡大図で示すように、本発明のダミ
ーのはんだバンプ３と実装基板５上のダミー用の第２の
パッド７のリフローによるセルフアライメントにより、
図１（ｄ）に示すように、パッケージ１の入出力リード
であるピン２と実装基板５上の正規のパッドである第１
のパッド６との設置の際の位置ずれが補正される。As a means for solving the above problems, FIG.
1A is a plan view, FIG. 1B is a sectional view, and FIG.
As shown in an enlarged view of the joint portion of the pin 2, by the self-alignment by reflow of the dummy solder bump 3 of the present invention and the dummy second pad 7 on the mounting substrate 5,
As shown in FIG. 1D, the pin 2 which is an input / output lead of the package 1 and the first pad which is a regular pad on the mounting substrate 5
The positional deviation at the time of installation with the pad 6 is corrected.
【００１３】すなわち、本発明の問題点は、図１、また
は後述の図２（ａ）に示すように、パッケージ１の底面
から延出されたピン２を実装基板５の第１のパッド６に
表面実装して実装を行う半導体のパッケージ１におい
て、パッケージ１にバンプ３を、実装基板５に第１のパ
ッド６より大きい第２のパッド７をそれぞれ設け、バン
プ３を実装基板５上の第２のパッド７に接合して実装す
るとともに、パッケージ１のピン２を実装基板５に実装
することにより、或いは、後述の図２（ｂ）に示すよう
に、パッケージ１にガルウイングリード８を、実装基板
５に第１のパッド６より大きい第２のパッド７をそれぞ
れ設け、ガルウィングリード４と第２のパッド７とを実
装基板５上で接合するとともに、パッケージ１のピン２
を実装基板５に実装することにより、更に、後述の図２
（ｃ）に示すように、パッケージ１のピン２の長さを、
ピン２の径の１０倍以上にし、ピン２の根元を軟質樹脂
９で被覆することにより達成される。That is, the problem of the present invention is that, as shown in FIG. 1 or FIG. 2A described later, the pin 2 extending from the bottom surface of the package 1 is attached to the first pad 6 of the mounting substrate 5. In a semiconductor package 1 that is surface-mounted and mounted, bumps 3 are provided on the package 1 and second pads 7 that are larger than the first pads 6 are provided on the mounting substrate 5, and the bumps 3 are mounted on the mounting substrate 5 on the second side. Of the package 1 and the pins 2 of the package 1 are mounted on the mounting substrate 5, or as shown in FIG. 2B described later, the gull wing leads 8 are mounted on the mounting substrate. 5 are provided with second pads 7 larger than the first pads 6, the gull wing leads 4 and the second pads 7 are bonded on the mounting substrate 5, and the pins 2 of the package 1 are provided.
2 is mounted on the mounting substrate 5 to further provide the structure shown in FIG.
As shown in (c), the length of the pin 2 of the package 1 is
This is achieved by making the diameter of the pin 2 10 times or more and coating the base of the pin 2 with the soft resin 9.
【００１４】[0014]
【作用】以上説明したように、本発明では、バットリー
ド方式のＰＧＡパッケージの入出力用のピンのみによる
接合では接合面積が狭く、セルフアライメントが起きに
くいため、その周辺にセルフアライメント効果を持たせ
るために十分な面積を持つダミーのはんだバンプを設置
することにより、入出力用のピンだけでは困難であった
実装後のパッケージ上のピンと実装基板上のパッドとの
位置ずれを防止することが可能となる。また、はんだ接
合部の応力緩和にも効果がある。As described above, according to the present invention, since the joint area is small and the self-alignment is hard to occur in the joint using only the input / output pins of the bat-lead type PGA package, the self-alignment effect is provided around the joint area. Therefore, by installing dummy solder bumps with a sufficient area, it is possible to prevent misalignment between the pins on the package after mounting and the pads on the mounting board, which was difficult with just the I / O pins. Becomes It is also effective in relaxing the stress at the solder joint.
【００１５】また、本発明の他の方法であるピンの長さ
を長くし、ピンの根元を軟質樹脂で被覆することによ
り、ビンの形状曲がり等の破損を防止することができ
る。In another method of the present invention, the length of the pin is increased and the base of the pin is covered with a soft resin, so that the bottle can be prevented from being bent or broken.
【００１６】[0016]
【実施例】図１は本発明の原理説明図兼第１の実施例の
説明図、図２は本発明の第２〜第４の実施例の説明図で
ある。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of the principle of the present invention and an explanatory view of the first embodiment, and FIG. 2 is an explanatory view of the second to fourth embodiments of the present invention.
【００１７】図において、１はパッケージ、２はピン、
３はバンプ、４ははんだ、５は実装基板、６は第１のパ
ッド、７は第２のパッド、８はガルウイングリード、９
は軟質樹脂（シリコーンゴム）である。In the figure, 1 is a package, 2 is a pin,
3 is a bump, 4 is a solder, 5 is a mounting substrate, 6 is a first pad, 7 is a second pad, 8 is a gull wing lead, 9
Is a soft resin (silicone rubber).
【００１８】図１にＰＧＡのパッケージにダミー用のは
んだからなるバンプを用いた本発明の第１の実施例を示
す。ＰＧＡの本発明のパッケージ１は図１（ａ）に平面
図で示すように、２８８本のピン２を有し、この入出力
リード用のピン２の寸法が０．２φ×１．５ｍｍの場
合、鉛（Ｐｂ）３７−錫（Ｓｎ）６３のはんだバンプ３
の大きさを、０．７φｍｍとし、その設置領域をストレ
スの小さな中央部に限定し、図１（ｂ）に断面図で示す
ように、ピッチ１．２７ｍｍ でパッケージ１のセラミ
ック基板に高さ０．８ｍｍの凸部を設けてダミー用のは
んだバンプ３を併設する。そして２００℃のはんだリフ
ローにより、ピン２と実装基板５上の第１のパッド６の
位置合わせずれがあっても、ダミー用のはんだのバンプ
３のリフローによるダミー用の第２のパッド７とのセル
フアラインにより位置合わせずれが自動的に修正され、
実装基板５にＰＧＡのパッケージ１が正規の位置で実装
出来る。FIG. 1 shows a first embodiment of the present invention in which a bump made of dummy solder is used in a PGA package. As shown in the plan view of FIG. 1A, the PGA package 1 of the present invention has 288 pins 2, and the size of the pins 2 for input / output leads is 0.2φ × 1.5 mm. , Lead (Pb) 37-tin (Sn) 63 solder bump 3
Is 0.7 mm, and its installation area is limited to the central part where stress is small. As shown in the sectional view in FIG. 1 (b), the pitch is 1.27 mm and the height of the ceramic substrate of the package 1 is 0 mm. A 8 mm convex portion is provided and a dummy solder bump 3 is provided. Even if the pins 2 and the first pads 6 on the mounting board 5 are misaligned by the solder reflow at 200 ° C., the dummy second pads 7 are reflowed by the reflow of the dummy solder bumps 3. Misalignment is automatically corrected by self-alignment,
The PGA package 1 can be mounted on the mounting substrate 5 at a regular position.
【００１９】更に、そのバンプ３をグランドピンに併用
することにより、例えピン２の中の正規のグランドピン
の接続部分に一部クラックが生じても冗長性を持たせて
グランド接続を確保することができる。Further, by using the bump 3 together with the ground pin, the ground connection can be secured by providing redundancy even if some cracks occur in the connection part of the regular ground pin in the pin 2. You can
【００２０】図２（ａ）は、同じＰＧＡのパッケージ１
において、ダミーのはんだバンプ３をパッケージ１の周
辺に設け、実装時の実装基板５とパッケージ１の位置の
安定性を持たせた本発明の第２の実施例である。FIG. 2A shows a package 1 of the same PGA.
2 is a second embodiment of the present invention in which dummy solder bumps 3 are provided around the package 1 to provide stability of the positions of the mounting substrate 5 and the package 1 during mounting.
【００２１】図２（ｂ）は、同じＰＧＡパッケージ１に
おいて、ダミーのはんだバンプ３の代わりにダミーのガ
ルウィングリード８を用い、ピン２とガルウイングリー
ド８の取付けを同一工程で行えるようにした本発明の第
３の実施例である。FIG. 2B shows the present invention in which dummy gull wing leads 8 are used instead of dummy solder bumps 3 in the same PGA package 1 so that pins 2 and gull wing leads 8 can be attached in the same step. 3 is a third embodiment of the present invention.
【００２２】図２（ｃ）はパッケージ１のピン２の破損
を防止する他の方法として、ピン２の径が０．２８φの
場合、通常ピンの長さが３ｍｍであるのを倍以上の７ｍ
ｍとし、軟質樹脂９としてシリコーンゴムをピン２の根
元に被覆して、ピン２の曲がりや折損を防止した本発明
の第４の実施例である。このコンプライアント（柔軟
性）のあるシリコーンゴムは長いピン２の曲がりを防ぐ
のに大きな効果がある。また、この時、シリコーンゴム
の被覆高さをコントロールすることで、ピン２先端のメ
ニスカス部のはんだ量をコントロールすることも出来る
ようになる。FIG. 2C shows another method for preventing damage to the pin 2 of the package 1. When the diameter of the pin 2 is 0.28φ, the length of the normal pin is 3 mm, which is more than double the length of 7 m.
In the fourth embodiment of the present invention, the base of the pin 2 is coated with silicone rubber as the soft resin 9 to prevent bending and breakage of the pin 2. This compliant (flexible) silicone rubber is very effective in preventing the long pin 2 from bending. Also, at this time, by controlling the coating height of the silicone rubber, it becomes possible to control the amount of solder in the meniscus portion at the tip of the pin 2.
【００２３】[0023]
【発明の効果】以上説明したように、本発明によれば、
バットリード方式によるＩＣパッケージと実装基板との
接合において、ダミーの接合部分を設けてはんだ接合の
面積を広げることにより、はんだのセルフアライメント
効果を利用して、従来困難であった位置合わせを容易に
行うことが可能となる。また、入出力ピンに集中してい
たストレスを緩和することも可能となる。As described above, according to the present invention,
When the IC package and the mounting board are joined by the butt lead method, a dummy joint portion is provided to widen the area of solder joint, thereby utilizing the self-alignment effect of the solder and facilitating the alignment which has been difficult in the past. It becomes possible to do. It is also possible to relieve the stress concentrated on the input / output pins.
【図１】 本発明の原理説明図FIG. 1 is a diagram illustrating the principle of the present invention.
【図２】 本発明の実施例の説明図FIG. 2 is an explanatory diagram of an embodiment of the present invention.
【図３】 従来例の説明図（その１）FIG. 3 is an explanatory diagram of a conventional example (No. 1)
【図４】 従来例の説明図（その２）FIG. 4 is an explanatory diagram of a conventional example (No. 2)
図において １ パッケージ ２ ピン ３ バンプ ４ はんだ ５ 実装基板 ６ 第１のパッド ７ 第２のパッド ８ ガルウイングリード ９ 軟質樹脂（シリコーンゴム） In the figure, 1 package 2 pins 3 bumps 4 solder 5 mounting board 6 first pad 7 second pad 8 gull wing lead 9 soft resin (silicone rubber)
Claims (4)
装基板の第１のパッドに表面実装して実装を行う半導体
のパッケージにおいて、パッケージにバンプを、実装基
板に該第１のパッドより大きい第２のパッドをそれぞれ
設け、該バンプと該第２のパッドとを該実装基板に実装
するとともに、該パッケージのピンを該実装基板に実装
することを特徴とする半導体装置の製造方法。1. A semiconductor package for mounting by mounting pins extending from a bottom surface of a package on a first pad of a mounting substrate, wherein bumps are mounted on the package and mounting pins on the mounting substrate are larger than the first pads. A method of manufacturing a semiconductor device, comprising providing two pads, mounting the bump and the second pad on the mounting board, and mounting pins of the package on the mounting board.
装基板の第１のパッドに表面実装して実装を行う半導体
のパッケージにおいて、パッケージにガルウイングリー
ドを、実装基板に該第１のパッドより大きい第２のパッ
ドをそれぞれ設け、該ガルウィングリードと該第２のパ
ッドとを該実装基板に実装するとともに、該パッケージ
のピンを該実装基板に実装することを特徴とする半導体
装置の製造方法。2. A semiconductor package for mounting by mounting a pin extending from a bottom surface of a package on a first pad of a mounting board, wherein a gull wing lead is mounted on the package, and the mounting board is larger than the first pad. A method of manufacturing a semiconductor device, comprising: providing second pads respectively, mounting the gull wing leads and the second pads on the mounting board, and mounting pins of the package on the mounting board.
装基板の第１のパッドに表面実装して実装を行う半導体
のパッケージにおいて、該ピンと別個に設けたバンプ或
いはガルウィングリードをグランドピンに併用すること
を特徴とする請求項１〜２記載の半導体装置の製造方
法。3. In a semiconductor package for mounting by mounting a pin extending from a bottom surface of a package on a first pad of a mounting board, a bump or a gull wing lead provided separately from the pin is also used as a ground pin. 3. The method of manufacturing a semiconductor device according to claim 1, wherein
装基板の第１のパッドに表面実装して実装を行う半導体
のパッケージにおいて、該パッケージのピンの長さを、
該ピンの径の１０倍以上にし、該ピンの根元を軟質樹脂
で被覆することを特徴とする半導体装置の製造方法。4. In a semiconductor package for mounting by mounting a pin extending from the bottom surface of a package on a first pad of a mounting substrate, the length of the pin of the package is
A method of manufacturing a semiconductor device, comprising making the diameter of the pin 10 times or more and coating the base of the pin with a soft resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7058647A JPH08255998A (en) | 1995-03-17 | 1995-03-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7058647A JPH08255998A (en) | 1995-03-17 | 1995-03-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08255998A true JPH08255998A (en) | 1996-10-01 |
Family
ID=13090385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7058647A Withdrawn JPH08255998A (en) | 1995-03-17 | 1995-03-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08255998A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100464400C (en) * | 2006-05-08 | 2009-02-25 | 矽品精密工业股份有限公司 | Semiconductor package stacking structure and its preparing method |
-
1995
- 1995-03-17 JP JP7058647A patent/JPH08255998A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100464400C (en) * | 2006-05-08 | 2009-02-25 | 矽品精密工业股份有限公司 | Semiconductor package stacking structure and its preparing method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20020604 |