JPH08213202A - Resistor - Google Patents
ResistorInfo
- Publication number
- JPH08213202A JPH08213202A JP7014649A JP1464995A JPH08213202A JP H08213202 A JPH08213202 A JP H08213202A JP 7014649 A JP7014649 A JP 7014649A JP 1464995 A JP1464995 A JP 1464995A JP H08213202 A JPH08213202 A JP H08213202A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- layer
- resistor layer
- trimming groove
- cross
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Details Of Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、抵抗器に関し、詳しく
は抵抗器の抵抗体層の形状に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistor, and more particularly to the shape of a resistor layer of a resistor.
【０００２】[0002]
【従来の技術】従来の抵抗器のうちで、チップ型抵抗器
の一般的な構成は図１０の平面図及び図１１の断面図に
示すように、絶縁基板２１の表面の両端部に表面電極２
２が形成され、この表面電極２２間に跨って抵抗体層２
３が形成されている。この抵抗体層２３の表面の一部に
第１保護層２４が形成され、抵抗体層２３と共に第１保
護層２４の一部を除去して抵抗値調整の為の切り欠き状
のトリミング溝２５が形成されている。そして、抵抗体
層２３とこれらに接続された表面電極２２の部分を覆う
ように第２保護層２６が形成されている。尚、表面電極
２２にメッキ層２７が一部重なっている。更に、絶縁基
板２１の裏面の両端部に裏面電極２８が形成されてお
り、この裏面電極２８と表面電極２２を接続するように
側面電極２９が形成されている。この裏面電極２８及び
側面電極２９がメッキ層２７で覆われて、チップ型抵抗
器は構成されている。2. Description of the Related Art Among conventional resistors, a chip type resistor generally has a structure in which surface electrodes are provided on both ends of an insulating substrate 21 as shown in a plan view of FIG. 10 and a sectional view of FIG. Two
2 are formed, and the resistor layer 2 is formed across the surface electrodes 22.
3 are formed. The first protective layer 24 is formed on a part of the surface of the resistor layer 23, and a part of the first protective layer 24 is removed together with the resistor layer 23 to form a notch-shaped trimming groove 25 for adjusting the resistance value. Are formed. Then, the second protective layer 26 is formed so as to cover the resistor layer 23 and the portion of the surface electrode 22 connected thereto. The plating layer 27 partially overlaps the surface electrode 22. Further, back surface electrodes 28 are formed on both ends of the back surface of the insulating substrate 21, and side surface electrodes 29 are formed so as to connect the back surface electrodes 28 and the surface electrodes 22. The back surface electrode 28 and the side surface electrode 29 are covered with the plating layer 27 to form a chip resistor.
【０００３】[0003]
【発明が解決しようとする課題】一般的に上述したよう
な従来のチップ型抵抗器では、電極２２、２２間に形成
される抵抗体層２３はほぼ均一な厚みで形成されてお
り、又、抵抗値調整の為のトリミング溝２５は抵抗体層
２３の任意の位置に形成されている。そのため、抵抗値
を調整するためにトリミング溝２５を抵抗体層２３を切
除して形成した部分の抵抗体層２３の断面積が、抵抗体
層２３が形成された時の断面積のままで残っている部分
より、過剰に小さくなってしまう。Generally, in the conventional chip-type resistor as described above, the resistor layer 23 formed between the electrodes 22 and 22 is formed to have a substantially uniform thickness. The trimming groove 25 for adjusting the resistance value is formed at an arbitrary position on the resistor layer 23. Therefore, the cross-sectional area of the resistor layer 23 at the portion where the trimming groove 25 is formed by cutting the resistor layer 23 to adjust the resistance value remains as the cross-sectional area when the resistor layer 23 is formed. It becomes too small compared to the part where it is.
【０００４】そのため、トリミング溝２５が形成された
抵抗体層２３の部分の抵抗値が高くなってしまい、この
部分の電流密度が高くなり熱が発生しやくなる。そし
て、チップ型抵抗器の電極２２、２２間に過負荷が加わ
ると、トリミング溝２５が形成された抵抗体層２３の部
分で発生した熱が拡散する余裕もなく急激に発熱し、著
しい場合はチップ型抵抗器が破壊されてしまうという問
題点があった。Therefore, the resistance value of the portion of the resistor layer 23 where the trimming groove 25 is formed becomes high, and the current density at this portion becomes high, and heat is easily generated. Then, when an overload is applied between the electrodes 22 of the chip-type resistor, the heat generated in the portion of the resistor layer 23 in which the trimming groove 25 is formed rapidly generates heat without any margin, and There is a problem that the chip resistor is destroyed.
【０００５】本発明は、上述の問題点に鑑み、抵抗体層
で発生する熱が少なく、過負荷が加わった際にも抵抗体
層の破壊されることのない抵抗器の構造を提供すること
を目的とする。In view of the above problems, the present invention provides a resistor structure in which the heat generated in the resistor layer is small and the resistor layer is not destroyed even when an overload is applied. With the goal.
【０００６】[0006]
【課題を解決するための手段】上述の問題点を解決する
ために、本願の請求項１に記載した発明は、絶縁基板上
に形成された対向する電極と、これら電極間に形成され
た抵抗体層と、この抵抗体層に形成されたトリミング溝
とを有する抵抗器であって、前記抵抗体層は前記電極間
で厚さの異なる領域を有し、且つ、前記トリミング溝が
前記抵抗体層の厚さの最小の領域よりも大きな領域に形
成されていることを特徴とする。In order to solve the above-mentioned problems, the invention described in claim 1 of the present application is directed to electrodes facing each other formed on an insulating substrate and resistors formed between these electrodes. A resistor having a body layer and a trimming groove formed in the resistor layer, wherein the resistor layer has regions having different thicknesses between the electrodes, and the trimming groove is the resistor body. It is characterized in that it is formed in a region larger than the region of minimum layer thickness.
【０００７】[0007]
【発明の作用及び効果】本発明では抵抗器において、抵
抗体層に形成された部分的に厚い領域にトリミング溝を
形成することにより、適正な抵抗値を得てもトリミング
溝の形成された抵抗体層の断面積が過剰に小さくなるこ
とがない。それにより、抵抗器の抵抗体層で発生する熱
が少なくなるだけでなく、たとえ抵抗器に過負荷が加わ
った際であっても、抵抗体層のトリミング溝が形成され
た部分で発生していた熱が減少し、抵抗器が破壊される
のを防止できるだけでなく、抵抗器の耐過負荷特性が向
上するという効果を有する。According to the present invention, in the resistor, the trimming groove is formed in the partly thick region formed in the resistor layer, so that the resistance having the trimming groove is formed even if an appropriate resistance value is obtained. The cross-sectional area of the body layer does not become excessively small. This not only reduces the heat generated in the resistor layer of the resistor, but also occurs in the part where the trimming groove is formed in the resistor layer, even when the resistor is overloaded. In addition to preventing the heat from being reduced and damaging the resistor, it also has the effect of improving the overload resistance of the resistor.
【０００８】[0008]
【実施例】以下本発明の抵抗器を図面を用いて説明す
る。図１は本発明の一実施例のチップ型抵抗器を示す平
面図で、アルミナセラミックよりなる絶縁性の基板１の
表面の両端部に表面電極２が形成されている。この表面
電極２は銀を含むメタルグレーズ系導電ペーストを印刷
しこれを焼成することにより形成されている。対向する
表面電極２間は両端が表面電極２に重なるように抵抗体
層３が形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A resistor according to the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a chip resistor according to an embodiment of the present invention, in which surface electrodes 2 are formed on both ends of a surface of an insulating substrate 1 made of alumina ceramic. The surface electrode 2 is formed by printing a metal glaze-based conductive paste containing silver and firing it. A resistor layer 3 is formed so that both ends of the surface electrodes 2 facing each other overlap the surface electrodes 2.
【０００９】この抵抗体層３は酸化ルテニウムを含むペ
ーストを基板１上に印刷しこれを焼成することで形成さ
れており、均一な厚みで対向する両表面電極２間に形成
された平坦部３ａと、平坦部より厚みが厚く表面電極２
と重ならない位置に形成さた凸部３ｂとからなる。この
抵抗体層３の凸部３ｂの表面の一部又は全部を覆うよう
に、第１保護層４が硼硅酸鉛ガラスを含むガラスグレー
ズ系ペーストを印刷しこれを焼成することにより形成さ
れている。この第１保護層４と抵抗体層３の凸部３ｂを
周知のレーザートリミング方法により切除して抵抗値調
整のトリミング溝５が形成されている。そして、抵抗体
層３とこれに接続された表面電極２の一部を覆うように
エポキシ系樹脂をこれらの上に印刷しこれを硬化させる
ことにより第２保護層６が形成されている。尚、表面電
極２には、一体的にニッケル、半田よりなるメッキ層７
が一部重なっている。更に、図１のＡ−Ａ’部分の断面
を図２に示すように、絶縁基板１の裏面の両端部には裏
面電極８が銀を含むメタルグレーズ系の導電ペーストを
印刷しこれを焼成することにより形成されている。そし
て、表面電極２と裏面電極８を接続する側面電極９が基
板１の両側面にメタルレジン系ペーストを印刷しこれを
硬化させることにより形成されている。この裏面電極８
及び側面電極９がメッキ層７で覆われて、チップ型抵抗
器は構成されている。The resistor layer 3 is formed by printing a paste containing ruthenium oxide on the substrate 1 and baking the paste, and a flat portion 3a formed between the two surface electrodes 2 facing each other with a uniform thickness. And the surface electrode 2 which is thicker than the flat portion
And a convex portion 3b formed at a position not overlapping with. The first protective layer 4 is formed by printing a glass glaze paste containing lead borosilicate glass and burning it so as to cover a part or all of the surface of the convex portion 3b of the resistor layer 3. There is. The first protective layer 4 and the convex portion 3b of the resistor layer 3 are cut off by a known laser trimming method to form a trimming groove 5 for adjusting the resistance value. Then, the second protective layer 6 is formed by printing an epoxy resin on the resistor layer 3 and a part of the front surface electrode 2 connected to the resistor layer 3 and then curing the epoxy resin to cure the resin. The surface electrode 2 is integrally formed with a plating layer 7 made of nickel and solder.
Are partially overlapped. Further, as shown in FIG. 2 which is a cross section taken along the line AA ′ in FIG. 1, a metal glaze-based conductive paste whose back electrode 8 contains silver is printed on both ends of the back surface of the insulating substrate 1 and baked. It is formed by Then, side surface electrodes 9 connecting the front surface electrode 2 and the back surface electrode 8 are formed by printing a metal resin paste on both side surfaces of the substrate 1 and curing it. This back electrode 8
The side surface electrode 9 and the side surface electrode 9 are covered with the plated layer 7 to form the chip resistor.
【００１０】この実施例において抵抗体層３は、平坦部
３ａを形成するパターンを有するスクリーンを用いて抵
抗用ペーストを印刷しこれを乾燥させ、その上に凸部３
ｂを形成するパターンを有するスクリーンを用いて抵抗
用ペーストを印刷しこれを乾燥させ、この後一緒に焼成
することで平坦部３ａに凸部３ｂを有する形状に形成さ
れる。In this embodiment, the resistor layer 3 is formed by printing a resistor paste using a screen having a pattern for forming the flat portion 3a, drying the paste, and then projecting the protrusion 3 thereon.
The resistance paste is printed using a screen having a pattern for forming b, dried, and then fired together to form a shape having a convex portion 3b in the flat portion 3a.
【００１１】尚、この実施例において、抵抗体層の平坦
部３ａの断面（図１のＢ−Ｂ’部分の断面）を示す図３
と、抵抗体層３の凸部３ｂにトリミング溝が形成された
部分の断面（図１のＣ−Ｃ’部分の断面）を示す図４
で、抵抗体層の断面積を比較すると、トリミング溝が形
成された部分の幅は平坦部に対して約半分程度の幅であ
り、一方トリミング溝が形成された部分の厚みは平坦部
に対して約３倍程度である。よって、トリミング溝が形
成された部分の断面積は平坦部の抵抗体層の断面積の約
１．５倍程度となり、トリミング溝が形成された抵抗体
層部分で発生する熱はほとんど無く、チップ型抵抗器に
短時間に過負荷が加わっても、チップ型抵抗器が破壊さ
れることが防止できる。It should be noted that, in this embodiment, a cross section of the flat portion 3a of the resistor layer (a cross section taken along the line BB 'in FIG. 1) is shown in FIG.
4 is a cross-sectional view of a portion where a trimming groove is formed in the convex portion 3b of the resistor layer 3 (cross-section of CC ′ portion in FIG. 1).
Comparing the cross-sectional areas of the resistor layers, the width of the portion where the trimming groove is formed is about half the width of the flat portion, while the thickness of the portion where the trimming groove is formed is about the flat portion. It is about 3 times. Therefore, the cross-sectional area of the part where the trimming groove is formed is about 1.5 times the cross-sectional area of the resistor layer in the flat part, and there is almost no heat generated in the part of the resistor layer where the trimming groove is formed. Even if an overload is applied to the die resistor for a short time, the chip resistor can be prevented from being broken.
【００１２】一方、図５は本発明の他の実施例のチップ
型抵抗器を示す平面図で、その抵抗体層３は図５のａ−
ａ’部分の断面を図６に示すように、略くさび型に形成
されている点を除き、第１実施例と同様の構成を有す
る。図６の図面視右側の表面電極２ａ近傍部分が抵抗体
層３の厚みが最小の領域で、図面視左側の表面電極２ｂ
に近傍部分に向かうに従って厚みが増加しており、後述
のトリミング溝は表面電極２ｂ近傍の領域に形成され
る。そしてトリミング溝が形成される領域の抵抗体層３
の表面の一部を覆うように、第１保護層４が硼硅酸鉛ガ
ラスを含むガラスグレーズ系ペーストを印刷しこれを焼
成することにより形成されている。この第１保護層４と
抵抗体層３の一部を周知のレーザートリミング方法によ
り切除して抵抗値調整のトリミング溝５が形成されてい
る。On the other hand, FIG. 5 is a plan view showing a chip resistor according to another embodiment of the present invention, in which the resistor layer 3 is a- of FIG.
As shown in FIG. 6, the cross section of the a'portion has the same configuration as that of the first embodiment except that it is formed in a substantially wedge shape. A portion near the surface electrode 2a on the right side in the drawing of FIG. 6 is a region where the thickness of the resistor layer 3 is minimum, and a surface electrode 2b on the left side in the drawing is viewed.
The thickness increases as it goes to the vicinity thereof, and a trimming groove described later is formed in a region near the surface electrode 2b. The resistor layer 3 in the region where the trimming groove is formed
The first protective layer 4 is formed by printing a glass glaze paste containing lead borosilicate glass and firing it so as to cover a part of the surface of the. A part of the first protective layer 4 and the resistor layer 3 is cut off by a known laser trimming method to form a trimming groove 5 for adjusting a resistance value.
【００１３】この実施例の抵抗体層３は、図７に断面を
模式的に示す方法で形成されている。この方法は前述の
実施例とは異なり、基板１にスクリーンを載せて、抵抗
ペーストの一度の印刷で抵抗体層３が形成される。この
方法に用いられるスクリーンは、金属性のメッシュ１０
の表面に紫外線硬化型の樹脂を硬化させこれをエッチン
グにて除去して抵抗体層３の形状にパターン形成された
マスク１１よりなる。このマスク１１は抵抗体層３の平
面視の形状にパターン形成された平面部１１ａと、抵抗
体層３に傾斜面が形成されるように平面部１１ａに一列
おきに形成されている、縦部１１ｂとからなっている。The resistor layer 3 of this embodiment is formed by a method whose cross section is schematically shown in FIG. This method is different from the above-described embodiment, in which the screen is placed on the substrate 1 and the resistor layer 3 is formed by printing the resistor paste once. The screen used in this method is a metal mesh 10.
An ultraviolet curable resin is hardened on the surface of and the resist is removed by etching to form a mask 11 patterned in the shape of the resistor layer 3. The mask 11 has a plane portion 11a patterned in the shape of the resistor layer 3 in a plan view, and vertical portions formed on the plane portion 11a every other row so that inclined surfaces are formed on the resistor layer 3. It consists of 11b.
【００１４】尚、この実施例において、抵抗体層３の厚
さの最も小さい領域の断面（図５のｂ−ｂ’部分の断
面）を示す図８と、トリミング溝が形成された領域の断
面（図５のｃ−ｃ’部分の断面）を示す図９で、抵抗体
層３の断面積を比較すると、トリミング溝が形成された
部分の幅は平坦部に対して約半分程度の幅であり、一方
トリミング溝が形成された部分の厚みは平坦部に対して
約１．７倍程度である。よって、平坦部の抵抗体層の断
面積はトリミング溝が形成された部分の断面積の約８０
％程度の大きさで、トリミング溝が形成された抵抗体層
部分で熱が発生しにくく、チップ型抵抗器に短時間に過
負荷が加わっても、チップ型抵抗器が破壊されることが
防止できる。In this embodiment, FIG. 8 showing the cross section of the region of the resistor layer 3 having the smallest thickness (cross section of bb 'portion in FIG. 5) and the cross section of the region where the trimming groove is formed. In FIG. 9 showing (cc 'section of FIG. 5), comparing the sectional areas of the resistor layers 3, the width of the portion where the trimming groove is formed is about half the width of the flat portion. On the other hand, the thickness of the portion where the trimming groove is formed is about 1.7 times that of the flat portion. Therefore, the cross-sectional area of the resistor layer in the flat portion is about 80 of the cross-sectional area of the portion where the trimming groove is formed.
%, It is difficult to generate heat in the resistor layer part where the trimming groove is formed, and it is possible to prevent the chip resistor from being destroyed even if the chip resistor is overloaded in a short time. it can.
【００１５】本発明は上述の実施例に記載のチップ型抵
抗器に特に限定されるものではなく、チップ型ネットワ
ーク抵抗器に用いられても良く、又、抵抗体層の保護層
が２層のチップ抵抗器を示したが、保護層が３層からな
る抵抗器に用いても良い。そして、抵抗体層の形成方法
は抵抗体層に部分的に厚みの異なる領域が形成可能な方
法で有れば、特に厚膜に限定されるものではなく、薄膜
等の手段で形成されても良く、又、トリミング溝の形成
方法は特にレーザートリミング限定されるものではな
く、サンドブラスト等の他の方法で形成しても良い。The present invention is not particularly limited to the chip type resistor described in the above embodiment, but may be used in a chip type network resistor, and the resistor layer has two protective layers. Although the chip resistor is shown, it may be used as a resistor having three protective layers. The method for forming the resistor layer is not particularly limited to a thick film as long as it is a method capable of forming regions having different thicknesses in the resistor layer, and the resistor layer may be formed by a means such as a thin film. Also, the method of forming the trimming groove is not particularly limited to laser trimming, and it may be formed by another method such as sandblasting.
【００１６】尚、本発明の抵抗器は上述の実施例に記載
の形状及び材料、方法等に特に限定されるものではな
い。The resistor of the present invention is not particularly limited to the shape, material, method and the like described in the above embodiments.
【図１】本発明のチップ型抵抗器の一実施例を示す平面
図FIG. 1 is a plan view showing an embodiment of a chip resistor of the present invention.
【図２】図１に示す本発明の一実施例のチップ型抵抗器
のＡ−Ａ’断面図FIG. 2 is a cross-sectional view taken along the line AA ′ of the chip resistor of the embodiment of the present invention shown in FIG.
【図３】図１に示す本発明の一実施例のチップ型抵抗器
のＢ−Ｂ’断面図FIG. 3 is a cross-sectional view taken along the line BB ′ of the chip resistor of the embodiment of the present invention shown in FIG.
【図４】図１に示す本発明の一実施例のチップ型抵抗器
のＣ−Ｃ’断面図FIG. 4 is a sectional view taken along the line CC ′ of the chip resistor of the embodiment of the present invention shown in FIG.
【図５】本発明のチップ型抵抗器の他の実施例を示す平
面図FIG. 5 is a plan view showing another embodiment of the chip resistor of the present invention.
【図６】図５に示す本発明の他の実施例のチップ型抵抗
器のａ−ａ’断面図FIG. 6 is a cross-sectional view taken along the line aa ′ of the chip resistor of another embodiment of the present invention shown in FIG.
【図７】図５に示す本発明の他の実施例のチップ型抵抗
器の抵抗体層の製造を模式的に示す断面図FIG. 7 is a cross-sectional view schematically showing manufacturing of a resistor layer of a chip resistor according to another embodiment of the present invention shown in FIG.
【図８】図５に示す本発明の他の実施例のチップ型抵抗
器のｂ−ｂ’断面図FIG. 8 is a cross-sectional view taken along the line bb ′ of the chip resistor according to another embodiment of the present invention shown in FIG.
【図９】図５に示す本発明の他の実施例のチップ型抵抗
器のｃ−ｃ’断面図9 is a cross-sectional view taken along the line cc 'of the chip resistor of another embodiment of the present invention shown in FIG.
【図１０】従来のチップ型抵抗器を示す平面図FIG. 10 is a plan view showing a conventional chip resistor.
【図１１】図１０に示す従来のチップ型抵抗器のＸ−
Ｘ’断面図11 is a schematic cross-sectional view of the conventional chip resistor shown in FIG.
X'cross section
【符号の説明】 １・・・・基板 ２・・・・表面電極 ３・・・・抵抗体層 ４・・・・第１保護層 ５・・・・トリミング溝 ６・・・・第２保護層 ７・・・・メッキ層 ８・・・・裏面電極 ９・・・・側面電極 １０・・・メッシュ １１・・・マスク[Explanation of reference numerals] 1 ... substrate 2 ... surface electrode 3 ... resistor layer 4 ... first protective layer 5 ... trimming groove 6 ... second protection Layer 7 ... Plating layer 8 ... Back surface electrode 9 ... Side electrode 10 ... Mesh 11 ... Mask
Claims (1)
と、これら電極間に形成された抵抗体層と、この抵抗体
層に形成されたトリミング溝とを有する抵抗器であっ
て、 前記抵抗体層は前記電極間で厚さの異なる領域を有し、
且つ、前記トリミング溝が前記抵抗体層の厚さの最小の
領域よりも大きな領域に形成されていることを特徴とす
る抵抗器。1. A resistor having opposing electrodes formed on an insulating substrate, a resistor layer formed between the electrodes, and a trimming groove formed in the resistor layer, the resistor comprising: The body layer has regions of different thickness between the electrodes,
A resistor, wherein the trimming groove is formed in a region larger than a region where the thickness of the resistor layer is minimum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7014649A JPH08213202A (en) | 1995-01-31 | 1995-01-31 | Resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7014649A JPH08213202A (en) | 1995-01-31 | 1995-01-31 | Resistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08213202A true JPH08213202A (en) | 1996-08-20 |
Family
ID=11867057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7014649A Pending JPH08213202A (en) | 1995-01-31 | 1995-01-31 | Resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08213202A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7132628B2 (en) * | 2004-03-10 | 2006-11-07 | Watlow Electric Manufacturing Company | Variable watt density layered heater |
| US7158718B2 (en) * | 2000-06-14 | 2007-01-02 | Watlow Electric Manufacturing Company | Electric heating device |
| US7755467B2 (en) | 2005-08-18 | 2010-07-13 | Rohm Co., Ltd. | Chip resistor |
-
1995
- 1995-01-31 JP JP7014649A patent/JPH08213202A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7158718B2 (en) * | 2000-06-14 | 2007-01-02 | Watlow Electric Manufacturing Company | Electric heating device |
| US7132628B2 (en) * | 2004-03-10 | 2006-11-07 | Watlow Electric Manufacturing Company | Variable watt density layered heater |
| US7755467B2 (en) | 2005-08-18 | 2010-07-13 | Rohm Co., Ltd. | Chip resistor |
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