JPH08204045A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH08204045A
JPH08204045A JP7011555A JP1155595A JPH08204045A JP H08204045 A JPH08204045 A JP H08204045A JP 7011555 A JP7011555 A JP 7011555A JP 1155595 A JP1155595 A JP 1155595A JP H08204045 A JPH08204045 A JP H08204045A
Authority
JP
Japan
Prior art keywords
convex
hole
mounting table
base
thermal expansion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7011555A
Other languages
Japanese (ja)
Inventor
Isamu Kaminaga
勇 神永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7011555A priority Critical patent/JPH08204045A/en
Publication of JPH08204045A publication Critical patent/JPH08204045A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE: To obtain a semiconductor package which reduces a stress to be applied to a mounting base and a package board due to the difference in a coefficient of thermal expansion between both and which prevents a gap from being generated when the bonded face of the mounting base to the package board is stripped. CONSTITUTION: A mounting base 3A is constituted of a protruding part 31A which is inserted into a through hole 15A in a state that a semiconductor integrated circuit 1 is mounted and of a base part 32A which is wider than the protruding part 31A. The protruding part 31A is inserted into the through hole 15A, the base part 32A is housed inside a first stepped part G1, and an adhesive 4 does not exist between the protruding part 31A and the inner wall of the through hole 15A so as to form a gap. Thereby, when the mounting base is thermally expanded, it is possible to prevent a stress in the plane direction form being applied to the protruding part and to the inner wall surface of the through hole, it is possible to suppress the stress from being applied to a coated adhesive, and it is possible to prevent the adhesive from being stripped so as to generate a gap.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体集積回路を収容す
る半導体パッケージに関し、特に熱サイクルによる接着
剤の剥離を防止した半導体パッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package containing a semiconductor integrated circuit, and more particularly to a semiconductor package in which peeling of an adhesive due to thermal cycles is prevented.

【０００２】[0002]

【従来の技術】図２１に従来の半導体パッケージの平面
図を示し、図２１のＡ−Ａ線の矢視断面図を図２２に示
す。図２１において略矩形形状のパッケージ基板５の中
央部分に半導体集積回路１が配置され、半導体集積回路
１に設けられた図示されない電極パッドと、パッケージ
基板５上に設けられた図示されない電極とが導線２で接
続されている。なお、パッケージ基板５上に設けられた
電極は外部の回路との接続を行う外部端子６に接続され
ており、半導体集積回路１と外部の回路とは外部端子６
を介して接続されることになる。21 is a plan view of a conventional semiconductor package, and FIG. 22 is a sectional view taken along line AA of FIG. In FIG. 21, the semiconductor integrated circuit 1 is arranged in the central portion of a substantially rectangular package substrate 5, and an electrode pad (not shown) provided on the semiconductor integrated circuit 1 and an electrode (not shown) provided on the package substrate 5 are conducting wires. Connected with 2. The electrodes provided on the package substrate 5 are connected to the external terminals 6 that connect to an external circuit, and the semiconductor integrated circuit 1 and the external circuit are connected to the external terminals 6
Will be connected via.

【０００３】図２２を用いて構成をさらに詳細に説明す
る。図２２に示すように、パッケージ基板５は、その中
央部に貫通孔１５を備えている。貫通孔１５の平面視形
状は略矩形であり、外部端子６が設けられた側の主面と
は反対側の主面（以後第１主面と呼称）から、外部端子
６が設けられた側の主面（以後第２主面と呼称）にかけ
て貫通している。第２主面側の開口部には段差部を有
し、段差部の開口寸法は貫通孔１５の開口部よりも大き
く形成されている。The structure will be described in more detail with reference to FIG. As shown in FIG. 22, the package substrate 5 has a through hole 15 in the center thereof. The through-hole 15 has a substantially rectangular shape in a plan view, and the side on which the external terminal 6 is provided is from a main surface (hereinafter referred to as a first main surface) opposite to the main surface on which the external terminal 6 is provided. Through the main surface (hereinafter referred to as the second main surface). The opening portion on the second main surface side has a step portion, and the opening dimension of the step portion is formed larger than that of the through hole 15.

【０００４】半導体集積回路１は平面視形状が略矩形の
金属製の載置台３に接着された状態でパッケージ基板５
の第１主面側から貫通孔１５内に挿入され、パッケージ
基板５と載置台３の間の隙間を埋めるように接着剤４が
塗布され、載置台３がパッケージ基板５に接着されてい
る。The semiconductor integrated circuit 1 is bonded to a mounting table 3 made of metal, which has a substantially rectangular shape in plan view, and a package substrate 5
Is inserted into the through hole 15 from the side of the first main surface thereof, the adhesive 4 is applied so as to fill the gap between the package substrate 5 and the mounting table 3, and the mounting table 3 is bonded to the package substrate 5.

【０００５】半導体集積回路１は貫通孔１５内に挿入さ
れた状態で、導線２を介してパッケージ基板５上に設け
られた図示されない電極に接続され、第２主面側の開口
部に蓋７をかぶせることで密閉され、外部と遮断され保
護される。なお、図２１において蓋７は示されていない
が、破線よって示される部分に蓋７が配置されることに
なる。The semiconductor integrated circuit 1 is inserted into the through hole 15 and connected to an electrode (not shown) provided on the package substrate 5 through the conductor 2 and the lid 7 is provided at the opening on the second main surface side. It is sealed by covering with, and is protected by being shielded from the outside. It should be noted that although the lid 7 is not shown in FIG. 21, the lid 7 is arranged at the portion indicated by the broken line.

【０００６】ここで、図２３に半導体集積回路１が接着
された状態の載置台３の斜視図を示す。図２３に示すよ
うに、載置台３はその主面上に半導体集積回路１を載置
した状態で貫通孔１５内に挿入される凸部３１と、凸部
３１よりも広い基部３２とで構成され、基部３２は凸部
３１が貫通孔１５内に挿入された状態でパッケージ基板
５の第１主面表面に係合し、載置台３の位置を規制す
る。なお、凸部３１および基部３２は一体で形成されて
いる。FIG. 23 is a perspective view of the mounting table 3 with the semiconductor integrated circuit 1 bonded thereto. As shown in FIG. 23, the mounting table 3 includes a convex portion 31 that is inserted into the through hole 15 with the semiconductor integrated circuit 1 mounted on the main surface thereof, and a base portion 32 that is wider than the convex portion 31. The base portion 32 engages with the surface of the first main surface of the package substrate 5 with the convex portion 31 inserted into the through hole 15, and regulates the position of the mounting table 3. The convex portion 31 and the base portion 32 are integrally formed.

【０００７】[0007]

【発明が解決しようとする課題】以上説明したように従
来の半導体パッケージは、半導体集積回路１を載置する
載置台３が放熱性を考慮して金属で形成され、凸部３１
と貫通孔１５の内壁面との間、および基部３２とパッケ
ージ基板５の第１主面表面との間に接着剤を塗布して、
貫通孔１５に凸部３１を挿入し、固着する構成となって
いる。ここで、貫通孔１５の平面方向の寸法は凸部３１
が挿入できる程度、凸部３１の平面方向の寸法よりわず
かに大きく形成されているにすぎない。As described above, in the conventional semiconductor package, the mounting table 3 on which the semiconductor integrated circuit 1 is mounted is made of metal in consideration of heat dissipation, and the convex portion 31 is formed.
And an inner wall surface of the through hole 15, and between the base 32 and the first main surface of the package substrate 5, an adhesive is applied,
The convex portion 31 is inserted into the through hole 15 and fixed. Here, the dimension of the through hole 15 in the plane direction is the convex portion
Is only slightly larger than the dimension of the convex portion 31 in the plane direction so that the can be inserted.

【０００８】従って、半導体パッケージに温度変化等に
より熱サイクルが加わると、載置台３（材質はアルミニ
ウムあるいは銅などの熱伝導性の良好な金属）とパッケ
ージ基板５（材質はガラスエポキシなどの高分子材料で
あり一般的にプラスチック基板と呼称される）の熱膨張
係数の差により両者に応力が加わって載置台３とパッケ
ージ基板５の接着面が剥離し、隙間が生じることにな
る。この現象は平面方向の接着面において特に顕著であ
り、隙間が生じると載置台３と蓋７により密閉されてい
るはずの半導体集積回路１の気密性が悪くなり、隙間か
ら侵入した空気および水分により半導体集積回路１が腐
食したり、載置台３の接着力が低下して、載置台３が脱
落することがある。Therefore, when a heat cycle is applied to the semiconductor package due to temperature change or the like, the mounting table 3 (material is a metal having good thermal conductivity such as aluminum or copper) and the package substrate 5 (material is a polymer such as glass epoxy). Due to the difference in the thermal expansion coefficient of the material (generally called a plastic substrate), stress is applied to the two, and the adhesive surface between the mounting table 3 and the package substrate 5 separates, resulting in a gap. This phenomenon is particularly remarkable on the bonding surface in the plane direction, and if a gap is formed, the airtightness of the semiconductor integrated circuit 1 which should be sealed by the mounting table 3 and the lid 7 is deteriorated, and air and moisture intruding through the gap cause the phenomenon. The semiconductor integrated circuit 1 may be corroded, or the adhesive force of the mounting table 3 may be reduced, so that the mounting table 3 may drop off.

【０００９】このような問題を解決するために、載置台
３の材質をパッケージ基板５と同様のプラスチックにす
るか、あるいはパッケージ基板５に直接半導体集積回路
１を載置する構成にすれば気密性の問題は解消される
が、プラスチックは放熱性の点で金属に劣るので、消費
電力の大きい半導体集積回路を載置することができない
という問題があった。In order to solve such a problem, if the mounting base 3 is made of the same plastic as the package substrate 5 or the semiconductor integrated circuit 1 is mounted directly on the package substrate 5, the airtightness is improved. However, since plastic is inferior to metal in terms of heat dissipation, there is a problem that a semiconductor integrated circuit with high power consumption cannot be mounted.

【００１０】本発明は上記のような問題点を解消するた
めになされたもので、載置台とパッケージ基板の熱膨張
係数の差により両者に加わる応力を低減し、載置台とパ
ッケージ基板の接着面が剥離して、隙間が生じることを
防止した半導体パッケージを提供することを目的とす
る。The present invention has been made to solve the above problems, and reduces the stress applied to both the mounting table and the package substrate due to the difference in the thermal expansion coefficient between the mounting table and the package substrate, so that the bonding surface between the mounting table and the package substrate is reduced. It is an object of the present invention to provide a semiconductor package that prevents peeling of the resin and creates a gap.

【００１１】[0011]

【課題を解決するための手段】本発明に係る請求項１記
載の半導体パッケージは、半導体集積回路を載置する載
置台と、主面に垂直な方向に貫通孔を有し、前記半導体
集積回路を前記載置台に載置した状態で一方の主面側か
ら前記貫通孔内に挿入することで前記半導体集積回路を
収容するパッケージ基板とを備え、前記パッケージ基板
は前記載置台よりも熱膨張係数の小さい材質で形成され
た半導体パッケージであって、前記載置台は、前記貫通
孔内に挿入される凸部と、前記凸部よりも広い基部とを
有し、前記凸部と前記貫通孔の内壁面との間には、前記
凸部が熱膨張により膨張した場合に、前記凸部が前記貫
通孔の内壁面に接触することを防ぐ隙間を有し、前記載
置台の前記基部のみが接着剤によって前記パッケージ基
板の一方の主面に固着されていることを特徴とする。According to another aspect of the present invention, there is provided a semiconductor package having a mounting table on which a semiconductor integrated circuit is mounted and a through hole in a direction perpendicular to a main surface. And a package substrate that accommodates the semiconductor integrated circuit by being inserted into the through hole from one main surface side in a state where the package substrate is mounted on the mounting table, and the package substrate has a thermal expansion coefficient more than that of the mounting table. Is a semiconductor package formed of a small material, the mounting table has a convex portion to be inserted into the through hole, and a base portion wider than the convex portion, of the convex portion and the through hole. There is a gap between the inner wall surface and the inner wall of the through hole when the protrusion expands due to thermal expansion, and only the base of the mounting table is bonded. Agent on one main surface of the package substrate Characterized in that it is deposited.

【００１２】本発明に係る請求項２記載の半導体パッケ
ージは、前記パッケージ基板の前記一方の主面は、前記
貫通孔を取り囲むように設けられた溝を有し、前記載置
台の前記基部は、前記溝に対応して前記凸部を取り囲む
ように設けられ、前記貫通孔に前記凸部を挿入すること
で、前記溝内に挿入される突出部を有し、前記接着剤
は、前記溝内および前記溝の両側に塗布されている。According to a second aspect of the present invention, in the semiconductor package according to the second aspect, the one main surface of the package substrate has a groove provided so as to surround the through hole, and the base portion of the mounting table is The protrusion is provided so as to surround the protrusion corresponding to the groove, and has a protrusion that is inserted into the groove by inserting the protrusion into the through hole. And coated on both sides of the groove.

【００１３】本発明に係る請求項３記載の半導体パッケ
ージは、前記パッケージ基板の前記一方の主面は、前記
貫通孔を取り囲むように設けられた溝を有し、前記溝内
に粘性樹脂が塗布され、前記載置台の前記基部は、前記
溝に対応して前記凸部を取り囲むように設けられ、前記
貫通孔に前記凸部を挿入することで、前記粘性樹脂に接
触する突出部を有し、前記接着剤は、前記溝の両側に塗
布されている。In the semiconductor package according to a third aspect of the present invention, the one main surface of the package substrate has a groove provided so as to surround the through hole, and a viscous resin is applied in the groove. The base of the mounting table is provided so as to surround the protrusion corresponding to the groove, and has a protrusion that comes into contact with the viscous resin by inserting the protrusion into the through hole. The adhesive is applied to both sides of the groove.

【００１４】本発明に係る請求項４記載の半導体パッケ
ージは、前記パッケージ基板の前記一方の主面は、前記
貫通孔を取り囲むように設けられた第１の溝を有し、前
記載置台の前記基部は、前記第１の溝に対応して前記凸
部を取り囲むように設けられた第２の溝を有し、前記貫
通孔に前記凸部を挿入することで、前記第１の溝および
前記第２の溝によって規制される空間内に、弾力性を有
し圧縮されることで気密を保つ気密リングが設けられ、
前記接着剤は、前記第１の溝の両側に塗布されている。According to a fourth aspect of the present invention, in the semiconductor package according to the fourth aspect, the one main surface of the package substrate has a first groove provided so as to surround the through hole, The base portion has a second groove provided so as to surround the convex portion corresponding to the first groove, and by inserting the convex portion into the through hole, the first groove and the An airtight ring that has elasticity and is kept compressed by being compressed is provided in the space regulated by the second groove,
The adhesive is applied to both sides of the first groove.

【００１５】本発明に係る請求項５記載の半導体パッケ
ージは、前記載置台の前記基部は、前記凸部を取り囲む
ように設けられた溝を有し、前記パッケージ基板の前記
一方の主面は、前記溝に対応して前記貫通孔を取り囲む
ように設けられ、前記貫通孔に前記凸部を挿入すること
で、前記溝内に挿入される突出部を有し、前記接着剤
は、前記溝内および前記溝の両側に塗布されている。A semiconductor package according to a fifth aspect of the present invention is characterized in that the base portion of the mounting table has a groove provided so as to surround the convex portion, and the one main surface of the package substrate is Corresponding to the groove, the through hole is provided so as to surround the through hole, and the protrusion is inserted into the through hole to have a protruding portion that is inserted into the groove. And coated on both sides of the groove.

【００１６】本発明に係る請求項６記載の半導体パッケ
ージは、前記載置台の前記基部は、前記凸部を取り囲む
ように設けられた溝を有し、前記溝内に粘性樹脂が塗布
され、前記パッケージ基板の前記一方の主面は、前記溝
に対応して前記貫通孔を取り囲むように設けられ、前記
貫通孔に前記凸部を挿入することで、前記粘性樹脂に接
触する突出部を有し、前記接着剤は、前記溝の両側に塗
布されている。According to a sixth aspect of the present invention, in the semiconductor package according to the sixth aspect, the base portion of the mounting table has a groove provided so as to surround the convex portion, and a viscous resin is applied to the groove, The one main surface of the package substrate is provided so as to surround the through hole corresponding to the groove, and has a protruding portion that comes into contact with the viscous resin by inserting the convex portion into the through hole. The adhesive is applied to both sides of the groove.

【００１７】本発明に係る請求項７記載の半導体パッケ
ージは、前記載置台の前記凸部は、凸部外枠体および凸
部内部体を備え、前記凸部外枠体は、無底かつ無蓋で前
記凸部内部体が挿入される箱型形状であって、その外形
形状および外形寸法は、前記凸部の外形形状および外形
寸法を規定し、その一方の端面側には端縁部に沿った鍔
部を有し、前記凸部内部体は前記基部と一体で形成さ
れ、その外形形状および外形寸法は、前記凸部外枠体の
内形形状および内形寸法に応じて形成され、前記凸部内
部体の周囲の前記基部の表面は前記凸部外枠体の鍔部の
外形形状および外形寸法に合わせて座ぐりを施された座
ぐり部を有し、前記凸部内部体を前記凸部外枠体に挿入
することで、前記座ぐり部に前記鍔部が係合して前記載
置台の形をなし、前記凸部外枠体の材質は、その熱膨張
係数が前記基部および前記凸部内部体の熱膨張係数と、
前記パッケージ基板の熱膨張係数とのほぼ中間の値とな
るような材質であり、前記接着剤は、前記鍔部に接触す
るように塗布されている。According to a seventh aspect of the present invention, in the semiconductor package according to the seventh aspect, the convex portion of the mounting table includes a convex outer frame body and a convex inner body, and the convex outer frame body has no bottom and no lid. In the box shape into which the convex inner body is inserted, the outer shape and the outer dimension thereof define the outer shape and the outer dimension of the convex section, and one of the end faces is along the edge portion. And a flange portion, the convex inner body is formed integrally with the base, the outer shape and outer dimensions thereof are formed according to the inner shape and inner dimension of the outer frame of the convex portion, The surface of the base portion around the convex inner body has a counterbore portion which is counterbored in accordance with the outer shape and outer dimension of the flange portion of the convex outer frame body, the convex inner body By inserting into the outer frame of the convex portion, the collar portion engages with the spot facing portion to form the mounting table described above. The material of the convex outer frame body, its thermal expansion coefficient of the thermal expansion coefficient of the base and the convex portion inner member,
The material is a material having an intermediate value of the thermal expansion coefficient of the package substrate, and the adhesive is applied so as to come into contact with the flange portion.

【００１８】本発明に係る請求項８記載の半導体パッケ
ージは、前記載置台の前記凸部および前記基部は熱膨張
係数の異なる材質で形成され、前記凸部の材質は、その
熱膨張係数が前記基部の熱膨張係数と、前記パッケージ
基板の熱膨張係数とのほぼ中間の値となるような材質で
ある。In the semiconductor package according to claim 8 of the present invention, the convex portion and the base portion of the mounting table are formed of materials having different thermal expansion coefficients, and the material of the convex portion has the thermal expansion coefficient The material is such that the coefficient of thermal expansion of the base portion and the coefficient of thermal expansion of the package substrate are approximately intermediate values.

【００１９】本発明に係る請求項９記載の半導体パッケ
ージは、前記載置台の前記凸部は、前記半導体集積回路
を載置する載置部および、前記載置部と前記基部との間
に設けられた中間部を備え、前記中間部の材質は、その
熱膨張係数が前記基部の熱膨張係数と、前記パッケージ
基板の熱膨張係数とのほぼ中間の値となるような材質で
あり、前記載置部の材質は、その熱膨張係数が前記基部
の熱膨張係数と、前記半導体集積回路の基板の熱膨張係
数とのほぼ中間の値となるような材質である。According to a ninth aspect of the present invention, in the semiconductor package according to the ninth aspect, the convex portion of the mounting table is provided between the mounting portion on which the semiconductor integrated circuit is mounted and between the mounting portion and the base portion. The material of the intermediate portion is such that the coefficient of thermal expansion of the intermediate portion is approximately intermediate between the coefficient of thermal expansion of the base portion and the coefficient of thermal expansion of the package substrate. The material of the mounting portion is such that the coefficient of thermal expansion thereof is approximately the intermediate value between the coefficient of thermal expansion of the base and the coefficient of thermal expansion of the substrate of the semiconductor integrated circuit.

【００２０】本発明に係る請求項１０記載の半導体パッ
ケージは、前記載置台の前記凸部は、凸部外枠体および
凸部内部体と前記半導体集積回路を載置する載置部を備
え、前記凸部外枠体は、無底かつ無蓋で前記凸部内部体
が挿入される箱型形状であって、その外形形状および外
形寸法は、前記凸部の外形形状および外形寸法を規定
し、前記凸部内部体は前記基部と一体で形成され、その
外形形状および外形寸法は、前記凸部外枠体の内形形状
および内形寸法に応じて形成され、前記凸部内部体を前
記凸部外枠体に挿入し、前記凸部内部体および前記凸部
外枠体上に接するように前記載置部を接合することで前
記載置台の形をなし、前記凸部外枠体の材質は、その熱
膨張係数が前記基部および前記凸部内部体の熱膨張係数
と、前記パッケージ基板の熱膨張係数とのほぼ中間の値
となるような材質であり、前記載置部の材質は、その熱
膨張係数が前記基部および前記凸部内部体の熱膨張係数
と、前記半導体集積回路の基板の熱膨張係数とのほぼ中
間の値となるような材質である。According to a tenth aspect of the present invention, in the semiconductor package according to the tenth aspect, the convex portion of the mounting table includes a convex outer frame body, a convex inner body, and a mounting portion on which the semiconductor integrated circuit is mounted. The convex outer frame body is a box shape in which the convex inner body is inserted without a bottom and a lid, and the outer shape and outer dimension thereof define the outer shape and outer dimension of the convex portion, The convex inner body is formed integrally with the base, and the outer shape and outer dimension of the convex inner body are formed according to the inner shape and inner dimension of the outer frame of the convex portion. It is inserted into the outer frame body, and the above-mentioned mounting portion is formed by joining the above-mentioned mounting portion so as to contact the above-mentioned convex inner body and the above-mentioned convex outer frame body, and the material of the above-mentioned convex outer frame body is formed. The thermal expansion coefficient of the package is the same as that of the base and the convex inner body. The material of the mounting portion is a material having an approximately intermediate value with the thermal expansion coefficient of the plate, and the thermal expansion coefficient of the material of the mounting portion is the thermal expansion coefficient of the base portion and the convex internal body, and the semiconductor integrated circuit. The material is a material having a value substantially in the middle of the coefficient of thermal expansion of the substrate.

【００２１】本発明に係る請求項１１記載の半導体パッ
ケージは、半導体集積回路を載置する載置台と、主面に
垂直な方向に貫通孔を有し、前記半導体集積回路を前記
載置台に載置した状態で一方の主面側から前記貫通孔内
に挿入することで前記半導体集積回路を収容するパッケ
ージ基板とを備え、前記パッケージ基板は前記載置台よ
りも熱膨張係数の小さい材質で形成された半導体パッケ
ージであって、前記載置台は、前記貫通孔内に挿入され
る凸部と、前記凸部よりも広い基部とを有し、前記載置
台の前記凸部の縦断面形状は台形形状であり、前記貫通
孔の縦断面形状は前記凸部の縦断面形状に合わせたテー
パを有する形状であり、前記凸部と前記貫通孔の内壁面
との間には、前記凸部が熱膨張により膨張した場合に、
前記凸部が前記貫通孔の内壁面に接触するような隙間を
有し、前記載置台の前記基部のみが接着剤によって前記
パッケージ基板の一方の主面に固着されていることを特
徴とする。A semiconductor package according to an eleventh aspect of the present invention has a mounting table on which a semiconductor integrated circuit is mounted and a through hole in a direction perpendicular to the main surface, and the semiconductor integrated circuit is mounted on the mounting table. And a package substrate that accommodates the semiconductor integrated circuit by being inserted into the through hole from one main surface side in a mounted state, the package substrate being formed of a material having a thermal expansion coefficient smaller than that of the mounting table. In the semiconductor package described above, the mounting table has a convex portion that is inserted into the through hole and a base portion that is wider than the convex portion, and the vertical cross-sectional shape of the convex portion of the mounting table is trapezoidal. The vertical cross-sectional shape of the through-hole is a shape having a taper that matches the vertical cross-sectional shape of the convex portion, and the convex portion is thermally expanded between the convex portion and the inner wall surface of the through-hole. When expanded by
The convex portion has a gap so as to contact the inner wall surface of the through hole, and only the base portion of the mounting table is fixed to one main surface of the package substrate with an adhesive.

【００２２】本発明に係る請求項１２記載の半導体パッ
ケージは、前記パッケージ基板は、前記一方の主面側の
前記貫通孔の周囲に、前記基部を収容する段差部を有
し、前記段差部の平面方向の長さは、前記基部が熱膨張
により膨張した場合に、前記基部の端縁部が前記段差部
の内壁面に接触しないような長さである。According to a twelfth aspect of the present invention, in the semiconductor package according to the present invention, the package substrate has a stepped portion for accommodating the base portion around the through hole on the one main surface side. The length in the plane direction is such that the edge portion of the base portion does not contact the inner wall surface of the step portion when the base portion expands due to thermal expansion.

【００２３】[0023]

【作用】本発明に係る請求項１記載の半導体パッケージ
によれば、凸部と貫通孔の内壁面との間に、凸部が熱膨
張により膨張した場合に、凸部が貫通孔の内壁面に接触
することを防ぐ隙間を有し、載置台の基部のみを接着剤
によって固着することで、載置台が熱膨張した場合に、
平面方向の応力が凸部および貫通孔の内壁面に加わるこ
とが防止され、塗布された接着剤に応力が加わることが
抑制され、接着剤が剥離して隙間が生じることが防止さ
れる。According to the semiconductor package of the first aspect of the present invention, when the convex portion expands due to thermal expansion between the convex portion and the inner wall surface of the through hole, the convex portion has the inner wall surface of the through hole. When there is a thermal expansion of the mounting table, by fixing only the base of the mounting table with an adhesive,
The stress in the plane direction is prevented from being applied to the inner wall surfaces of the convex portion and the through hole, the stress is suppressed from being applied to the applied adhesive agent, and the adhesive agent is prevented from peeling off to form a gap.

【００２４】本発明に係る請求項２記載の半導体パッケ
ージによれば、貫通孔に凸部を挿入することで溝内に突
出部が挿入され、溝内に塗布された接着剤に突出部が接
触することになるので、載置台とパッケージ基板との接
触部分が入り組んだ構造となり、空気および水分の侵入
が阻止され半導体集積回路の気密性を高めることができ
る。According to the semiconductor package of the second aspect of the present invention, the protrusion is inserted into the groove by inserting the protrusion into the through hole, and the protrusion contacts the adhesive applied in the groove. Therefore, the contact portion between the mounting table and the package substrate is complicated, and the invasion of air and moisture is prevented, and the airtightness of the semiconductor integrated circuit can be improved.

【００２５】本発明に係る請求項３記載の半導体パッケ
ージによれば、貫通孔に凸部を挿入することで、溝内に
塗布された粘性樹脂に突出部が接触することになるの
で、載置台とパッケージ基板との接触部分が入り組んだ
構造になると共に、粘性樹脂により空気および水分の侵
入が阻止され半導体集積回路の気密性を一層高めること
ができる。According to the semiconductor package of the third aspect of the present invention, by inserting the protrusion into the through hole, the protrusion comes into contact with the viscous resin applied in the groove. The contact portion with the package substrate is intricate, and the viscous resin prevents the invasion of air and moisture to further enhance the airtightness of the semiconductor integrated circuit.

【００２６】本発明に係る請求項４記載の半導体パッケ
ージによれば、貫通孔に凸部を挿入することで第１の溝
および第２の溝によって規制される空間内に、弾力性を
有し圧縮されることで気密を保つ気密リングを備えてい
るので、気密リングにより空気および水分の侵入が阻止
され半導体集積回路の気密性を高めることができる。According to the semiconductor package of the fourth aspect of the present invention, by inserting the convex portion into the through hole, the semiconductor package has elasticity in the space regulated by the first groove and the second groove. Since the airtight ring that keeps the airtightness by being compressed is provided, the airtight ring can prevent the invasion of air and moisture and enhance the airtightness of the semiconductor integrated circuit.

【００２７】本発明に係る請求項５記載の半導体パッケ
ージによれば、貫通孔に凸部を挿入することで溝内に突
出部が挿入され、溝内に塗布された接着剤に突出部が接
触することになるので、載置台とパッケージ基板との接
触部分が入り組んだ構造となり、空気および水分の侵入
が阻止され半導体集積回路の気密性を高めることができ
る。According to the semiconductor package of the fifth aspect of the present invention, the protrusion is inserted into the groove by inserting the protrusion into the through hole, and the protrusion contacts the adhesive applied in the groove. Therefore, the contact portion between the mounting table and the package substrate is complicated, and the invasion of air and moisture is prevented, and the airtightness of the semiconductor integrated circuit can be improved.

【００２８】本発明に係る請求項６記載の半導体パッケ
ージによれば、貫通孔に凸部を挿入することで溝内に塗
布された粘性樹脂に突出部が接触することになるので、
載置台とパッケージ基板との接触部分が入り組んだ構造
になると共に、粘性樹脂により空気および水分の侵入が
阻止され半導体集積回路の気密性を一層高めることがで
きる。According to the semiconductor package of the sixth aspect of the present invention, the protrusion contacts the viscous resin applied in the groove by inserting the protrusion into the through hole.
The contact part between the mounting table and the package substrate is intricately structured, and the viscous resin prevents the invasion of air and moisture, thereby further enhancing the airtightness of the semiconductor integrated circuit.

【００２９】本発明に係る請求項７記載の半導体パッケ
ージによれば、凸部外枠体が、無底かつ無蓋で凸部内部
体が挿入される箱型形状であり、一方の端面側には端縁
部に沿った鍔部を有し、材質は、その熱膨張係数が基部
および凸部内部体の熱膨張係数と、パッケージ基板の熱
膨張係数とのほぼ中間の値となるような材質であるの
で、凸部と貫通孔の内壁との間隔を狭くすることがで
き、凸部と貫通孔の内壁との間隔を広くした場合に生じ
る、載置台の位置決めのばらつきを抑制することができ
ると共に、鍔部に接触するように塗布された接着剤に加
わる応力がさらに減少し、接着剤が剥離して隙間が生じ
ることが防止される。According to the semiconductor package of claim 7 of the present invention, the convex outer frame has a box shape in which the convex inner body is inserted without a bottom and without a lid, and one end face side is provided. It has a collar along the edge, and its material is such that its coefficient of thermal expansion is approximately the intermediate value between the coefficient of thermal expansion of the base and the convex inner body and the coefficient of thermal expansion of the package board. Therefore, the distance between the convex portion and the inner wall of the through hole can be narrowed, and it is possible to suppress the variation in the positioning of the mounting table, which occurs when the distance between the convex portion and the inner wall of the through hole is increased. Further, the stress applied to the adhesive applied so as to come into contact with the collar portion is further reduced, and the adhesive is prevented from peeling off to form a gap.

【００３０】本発明に係る請求項８記載の半導体パッケ
ージによれば、凸部の材質は、その熱膨張係数が基部の
熱膨張係数と、パッケージ基板の熱膨張係数とのほぼ中
間の値となるような材質であるので、凸部と貫通孔の内
壁との間隔を狭くすることができ、凸部と貫通孔の内壁
との間隔を広くした場合に生じる、載置台の位置決めの
ばらつきを抑制することができる。According to the semiconductor package of claim 8 of the present invention, the material of the convex portion has a coefficient of thermal expansion that is approximately an intermediate value between the coefficient of thermal expansion of the base and the coefficient of thermal expansion of the package substrate. With such a material, it is possible to narrow the gap between the convex portion and the inner wall of the through hole, and suppress the variation in the positioning of the mounting table that occurs when the gap between the convex portion and the inner wall of the through hole is widened. be able to.

【００３１】本発明に係る請求項９記載の半導体パッケ
ージによれば、中間部の材質は、その熱膨張係数が基部
の熱膨張係数と、パッケージ基板の熱膨張係数とのほぼ
中間の値となるような材質であるので、凸部と貫通孔の
内壁との間隔を狭くすることができ、凸部と貫通孔の内
壁との間隔を広くした場合に生じる、載置台の位置決め
のばらつきを抑制することができると共に、載置部の材
質が、その熱膨張係数が基部の熱膨張係数と、半導体集
積回路の基板の熱膨張係数とのほぼ中間の値となるよう
な材質であるので、半導体集積回路の基板が熱膨張係数
の違いにより載置台から剥離することが防止される。According to a ninth aspect of the semiconductor package of the present invention, the material of the intermediate portion has a coefficient of thermal expansion approximately between the coefficient of thermal expansion of the base and the coefficient of thermal expansion of the package substrate. With such a material, it is possible to narrow the gap between the convex portion and the inner wall of the through hole, and suppress the variation in the positioning of the mounting table that occurs when the gap between the convex portion and the inner wall of the through hole is widened. In addition, the material of the mounting portion is such that the coefficient of thermal expansion of the mounting portion is a value approximately intermediate between the coefficient of thermal expansion of the base and the coefficient of thermal expansion of the substrate of the semiconductor integrated circuit. It is possible to prevent the circuit board from peeling off from the mounting table due to the difference in thermal expansion coefficient.

【００３２】本発明に係る請求項１０記載の半導体パッ
ケージによれば、凸部外枠体が、無底かつ無蓋で凸部内
部体が挿入される箱型形状であり、材質は、その熱膨張
係数が基部および凸部内部体の熱膨張係数と、パッケー
ジ基板の熱膨張係数とのほぼ中間の値となるような材質
であるので、凸部と貫通孔の内壁との間隔を狭くするこ
とができ、凸部と貫通孔の内壁との間隔を広くした場合
に生じる、載置台の位置決めのばらつきを抑制すること
ができると共に、載置部の材質が、その熱膨張係数が基
部および凸部内部体の熱膨張係数と、半導体集積回路の
基板の熱膨張係数とのほぼ中間の値となるような材質で
あるので、半導体集積回路の基板が熱膨張係数の違いに
より載置台から剥離することが防止される。According to a tenth aspect of the semiconductor package of the present invention, the outer frame body of the convex portion has a box shape in which the inner body of the convex portion is inserted without a bottom and without a lid, and the material is its thermal expansion. Since the coefficient of the material is such that the coefficient of thermal expansion of the base body and the internal portion of the convex portion is approximately the value of the thermal expansion coefficient of the package substrate, it is possible to reduce the distance between the convex portion and the inner wall of the through hole. In addition, it is possible to suppress variations in positioning of the mounting table that occur when the distance between the convex portion and the inner wall of the through hole is widened, and the material of the mounting portion has a coefficient of thermal expansion whose inside of the base portion and the convex portion. Since the material is such that the coefficient of thermal expansion of the body and the coefficient of thermal expansion of the substrate of the semiconductor integrated circuit are approximately intermediate values, the substrate of the semiconductor integrated circuit may be separated from the mounting table due to the difference in coefficient of thermal expansion. To be prevented.

【００３３】本発明に係る請求項１１記載の半導体パッ
ケージによれば、平面方向の長さを縦断面形状が台形形
状の凸部が熱膨張により膨張した場合に、凸部が貫通孔
の内壁面に接触するような隙間を有し、載置台の基部の
みを接着剤によって固着することで、断面形状が台形形
状の凸部が熱膨張により、凸部の表面を貫通孔のテーパ
面に押しつける方向に膨張し、凸部と貫通孔の内壁とが
係合することになる。従って、凸部と貫通孔との間に隙
間が生じることが防止され、空気および水分の侵入が阻
止され半導体集積回路の気密性を高めることができる。According to the semiconductor package of the eleventh aspect of the present invention, when the convex portion having a trapezoidal longitudinal section in the plane direction is expanded by thermal expansion, the convex portion has an inner wall surface of the through hole. The direction that presses the surface of the projection against the tapered surface of the through hole due to thermal expansion of the projection with a trapezoidal cross section by fixing the base of the mounting table with an adhesive. Expands, and the convex portion engages with the inner wall of the through hole. Therefore, it is possible to prevent a gap from being formed between the convex portion and the through hole, prevent the entry of air and moisture, and enhance the airtightness of the semiconductor integrated circuit.

【００３４】本発明に係る請求項１２記載の半導体パッ
ケージによれば、パッケージ基板が、一方の主面側の貫
通孔の周囲に、基部を収容する段差部を有しているの
で、パッケージ基板の一方の主面の表面に基部が突出せ
ず、半導体パッケージの外形形状を平板に保つことがで
きる。また、段差部の平面方向の長さは、基部が熱膨張
により膨張した場合に、基部の端縁部が段差部の内壁面
に接触しないような長さとなっているので、載置台の熱
膨張により塗布された接着剤に応力が加わることが抑制
され、接着剤が剥離して隙間が生じることが防止され
る。According to the twelfth aspect of the semiconductor package of the present invention, since the package substrate has the stepped portion for accommodating the base portion around the through hole on the one main surface side, the package substrate The base does not project to the surface of the one main surface, and the outer shape of the semiconductor package can be kept flat. Further, the length of the step portion in the plane direction is such that the edge portion of the base portion does not contact the inner wall surface of the step portion when the base portion expands due to thermal expansion. Thus, the stress applied to the applied adhesive agent is suppressed, and the adhesive agent is prevented from peeling to form a gap.

【００３５】[0035]

【実施例】【Example】

＜第１の実施例＞図１に本発明に係る半導体パッケージ
の第１の実施例として、半導体パッケージＡの正面図を
示し、図１のＡ−Ａ線の矢視断面図を図２に示し、図３
にその部分断面図を示す。<First Embodiment> FIG. 1 shows a front view of a semiconductor package A as a first embodiment of a semiconductor package according to the present invention, and FIG. 2 shows a sectional view taken along the line AA of FIG. , Fig. 3
The partial sectional view is shown in FIG.

【００３６】図１において略矩形形状のパッケージ基板
５Ａの中央部分に半導体集積回路１が配置され、半導体
集積回路１に設けられた図示されない電極パッドと、パ
ッケージ基板５Ａ上に設けられた図示されない電極とが
導線２で接続されている。なお、パッケージ基板５Ａ上
に設けられた電極は外部の回路との接続を行う外部端６
に接続されており、半導体集積回路１と外部の回路とは
外部端子６を介して接続されることになる。In FIG. 1, a semiconductor integrated circuit 1 is arranged in the central portion of a substantially rectangular package substrate 5A, an electrode pad (not shown) provided on the semiconductor integrated circuit 1 and an electrode (not shown) provided on the package substrate 5A. And are connected by a conductor 2. The electrodes provided on the package substrate 5A are external ends 6 for connecting to an external circuit.
The semiconductor integrated circuit 1 and an external circuit are connected via the external terminal 6.

【００３７】図２を用いて断面構成を説明する。図２に
示すように、パッケージ基板５Ａは、その中央部に貫通
孔１５Ａを備えている。貫通孔１５Ａの平面視形状は略
矩形であり、第１主面から第２主面にかけて貫通してお
り、第１および第２主面側の開口部にそれぞれ段差部を
有している。以後、第１主面の側に設けられた段差部を
第１段差部Ｇ１と呼称し、第２主面の側に設けられた段
差部を第２段差部Ｇ２と呼称する。The sectional structure will be described with reference to FIG. As shown in FIG. 2, the package substrate 5A has a through hole 15A in the center thereof. The shape of the through hole 15A in a plan view is substantially rectangular, penetrates from the first main surface to the second main surface, and has step portions in the openings on the first and second main surface sides, respectively. Hereinafter, the step portion provided on the first main surface side is referred to as a first step portion G1, and the step portion provided on the second main surface side is referred to as a second step portion G2.

【００３８】半導体集積回路１は平面視形状が略矩形の
金属製の載置台３Ａに接着された状態でパッケージ基板
５Ａの第１主面側から貫通孔１５Ａ内に挿入され、接着
剤４によってパッケージ基板５Ａに接着されている。The semiconductor integrated circuit 1 is inserted into the through hole 15A from the first main surface side of the package substrate 5A in a state of being adhered to the metal mounting table 3A having a substantially rectangular shape in a plan view, and is packaged by the adhesive 4 It is adhered to the substrate 5A.

【００３９】半導体集積回路１は貫通孔１５Ａ内に挿入
された状態で、導線２を介して第２段差部Ｇ２に設けら
れた図示されない電極に接続され、蓋７をかぶせること
で密閉され、外部と遮断され保護される。なお、図１に
おいて蓋７は示されていないが、破線よって示される部
分に蓋７が配置されることになる。The semiconductor integrated circuit 1 is inserted into the through hole 15A, connected to an electrode (not shown) provided on the second step portion G2 through the conductor 2, and is sealed by covering the lid 7 with the outside. And blocked and protected. Although the lid 7 is not shown in FIG. 1, the lid 7 is arranged at a portion indicated by a broken line.

【００４０】次に図３を用いて、載置台３Ａと貫通孔１
５Ａとの接合状態について詳細に説明する。ここで、載
置台３Ａの構成は、半導体集積回路１を載置した状態で
貫通孔１５Ａ内に挿入される凸部３１Ａと、凸部３１Ａ
よりも広い基部３２Ａとで構成されている。なお、凸部
３１Ａおよび基部３２Ａは一体で形成されている。Next, referring to FIG. 3, the mounting table 3A and the through hole 1
The joining state with 5A will be described in detail. Here, the configuration of the mounting table 3A is configured such that the semiconductor integrated circuit 1 is mounted on the projecting portion 31A inserted into the through hole 15A and the projecting portion 31A.
It is composed of a wider base 32A. The convex portion 31A and the base portion 32A are integrally formed.

【００４１】図３に示すように載置台３Ａは、半導体集
積回路１を載置した凸部３１Ａが貫通孔１５Ａ内に挿入
されると共に、基部３２Ａが第１段差部Ｇ１内に収容さ
れている。第１段差部Ｇ１の開口寸法は基部３２Ａの寸
法に比べて大きく、基部３２Ａを収容しても、基部３２
Ａの端縁部と第１段差部Ｇ１の内壁面との間には空間的
に余裕があるように構成されている。As shown in FIG. 3, in the mounting table 3A, the convex portion 31A on which the semiconductor integrated circuit 1 is mounted is inserted into the through hole 15A, and the base portion 32A is housed in the first step portion G1. . The opening size of the first step G1 is larger than the size of the base 32A, and even if the base 32A is housed, the base 32
There is a spatial allowance between the edge of A and the inner wall surface of the first step G1.

【００４２】ここで、第１段差部Ｇ１と基部３２Ａとの
間にのみ接着剤４が塗布され、第１段差部Ｇ１と基部３
２Ａとを接着している。従って、凸部３１Ａと貫通孔１
５Ａの内壁との間には接着剤４が存在せず間隙となって
いる。また、基部３２Ａの端縁部と第１段差部Ｇ１の内
壁面との間隔、および凸部３１Ａと貫通孔１５Ａの内壁
との間隔は、基部３２Ａおよび凸部３１Ａのそれぞれの
平面方向の長さの１０％〜２０％程度を目安として設定
される。Here, the adhesive 4 is applied only between the first step portion G1 and the base portion 32A, and the first step portion G1 and the base portion 3 are formed.
It is bonded to 2A. Therefore, the convex portion 31A and the through hole 1
There is no adhesive 4 between the inner wall of 5A and the inner wall of 5A. The distance between the edge of the base portion 32A and the inner wall surface of the first step G1 and the distance between the convex portion 31A and the inner wall of the through hole 15A are the lengths of the base portion 32A and the convex portion 31A in the planar direction. 10% to 20% is set as a standard.

【００４３】一般的に載置台３Ａとパッケージ基板５Ａ
に熱サイクルが加わった場合に、熱膨張係数の差による
応力が最も大きくなるのは平面方向である。従って、凸
部３１Ａと貫通孔１５Ａの内壁に挟まれるように接着剤
４が存在していると、応力による形状の変形により接着
剤４が剥離することになる。Generally, the mounting table 3A and the package substrate 5A
When a thermal cycle is applied to the sheet, the stress due to the difference in the thermal expansion coefficient becomes the largest in the plane direction. Therefore, when the adhesive 4 exists so as to be sandwiched between the convex portion 31A and the inner wall of the through hole 15A, the adhesive 4 is peeled off due to the deformation of the shape due to the stress.

【００４４】一方、本実施例の半導体パッケージＡのよ
うに、凸部３１Ａと貫通孔１５Ａの内壁との間には接着
剤４が存在せず間隙となっているので、熱サイクルによ
り平面方向の応力が凸部３１Ａおよび貫通孔１５Ａに与
えられることが防止される。また、基部３２Ａの端縁部
と第１段差部Ｇ１の内壁面との間には空間的に余裕があ
るように構成されているので、熱サイクルにより平面方
向の応力が基部３２Ａの端縁部および第１段差部Ｇ１の
内壁面に加わることが防止され、第１段差部Ｇ１と基部
３２Ａとの間に塗布された接着剤４に応力が加わること
が抑制され、接着剤４が剥離して隙間が生じることが防
止される。On the other hand, as in the semiconductor package A of this embodiment, since there is no adhesive 4 between the convex portion 31A and the inner wall of the through hole 15A, there is a gap, so that the thermal cycle results in a planar direction. Stress is prevented from being applied to the convex portion 31A and the through hole 15A. Further, since there is a spatial margin between the edge portion of the base portion 32A and the inner wall surface of the first step portion G1, the stress in the plane direction due to the thermal cycle causes an edge portion of the base portion 32A. Also, it is prevented from being applied to the inner wall surface of the first step portion G1, stress is suppressed from being applied to the adhesive 4 applied between the first step portion G1 and the base 32A, and the adhesive 4 peels off. A gap is prevented from being generated.

【００４５】＜第２の実施例＞図４に本発明に係る半導
体パッケージの第２の実施例として、半導体パッケージ
Ｂの部分断面図を示す。なお、半導体パッケージＢの正
面図は図１に示した半導体パッケージＡと同様であるの
で省略する。なお、図４は図１のＡ−Ａ線と同じ位置で
の部分断面図である。また、図１〜図３を用いて説明し
た第１の実施例と同一の構成については同一の符号を付
し、重複する説明は省略する。<Second Embodiment> FIG. 4 shows a partial sectional view of a semiconductor package B as a second embodiment of the semiconductor package according to the present invention. The front view of the semiconductor package B is the same as the semiconductor package A shown in FIG. 4 is a partial cross-sectional view at the same position as the line AA in FIG. Further, the same components as those in the first embodiment described with reference to FIGS. 1 to 3 are designated by the same reference numerals, and the duplicate description will be omitted.

【００４６】図４に示すように、パッケージ基板５Ｂ
は、その中央部に貫通孔１５Ｂを備えている。貫通孔１
５Ｂの平面視形状は略矩形であり、第１主面から第２主
面にかけて貫通しており、第１および第２主面側の開口
部にそれぞれ段差部を有している。以後、第１主面の側
に設けられた段差部を第１段差部Ｇ１と呼称し、第２主
面の側に設けられた段差部を第２段差部Ｇ２と呼称す
る。第１段差部Ｇ１には、貫通孔１５Ｂを取り囲むよう
に溝Ｌが設けられている。As shown in FIG. 4, the package substrate 5B
Has a through hole 15B in the center thereof. Through hole 1
The plan view shape of 5B is substantially rectangular, penetrates from the first main surface to the second main surface, and has step portions in the openings on the first and second main surface sides, respectively. Hereinafter, the step portion provided on the first main surface side is referred to as a first step portion G1, and the step portion provided on the second main surface side is referred to as a second step portion G2. A groove L is provided in the first step portion G1 so as to surround the through hole 15B.

【００４７】半導体集積回路１は平面視形状が略矩形の
金属製の載置台３Ｂに接着された状態でパッケージ基板
５Ｂの第１主面側から貫通孔１５Ｂ内に挿入され、接着
剤４によってパッケージ基板５Ｂに接着されている。The semiconductor integrated circuit 1 is inserted into the through hole 15B from the first main surface side of the package substrate 5B in a state of being bonded to the metal mounting table 3B having a substantially rectangular shape in a plan view, and the package is formed by the adhesive 4 It is adhered to the substrate 5B.

【００４８】ここで、図５に半導体集積回路１が接着さ
れた状態の載置台３Ｂの斜視図を示す。図５に示すよう
に、載置台３Ｂはその主面上に半導体集積回路１を載置
した状態で貫通孔１５Ｂ内に挿入される凸部３１Ｂと、
凸部３１Ｂよりも広い基部３２Ｂとで構成され、基部３
２Ｂは第１段差部Ｇ１に設けられた溝Ｌに対応するよう
に突出部Ｐが設けられている。なお、凸部３１Ｂおよび
基部３２Ｂは一体で形成されている。Here, FIG. 5 is a perspective view of the mounting table 3B with the semiconductor integrated circuit 1 bonded thereto. As shown in FIG. 5, the mounting table 3B has a convex portion 31B inserted into the through hole 15B with the semiconductor integrated circuit 1 mounted on the main surface thereof.
The base portion 32B, which is wider than the convex portion 31B,
2B is provided with a protrusion P so as to correspond to the groove L provided in the first step G1. The convex portion 31B and the base portion 32B are integrally formed.

【００４９】図４に示すように載置台３Ｂは、半導体集
積回路１を載置した凸部３１Ｂが貫通孔１５Ｂ内に挿入
されると共に、基部３２Ｂが第１段差部Ｇ１内に収容さ
れ、基部３２Ｂの突出部Ｐが第１段差部Ｇ１の溝Ｌ内に
挿入されている。As shown in FIG. 4, in the mounting table 3B, the convex portion 31B on which the semiconductor integrated circuit 1 is mounted is inserted into the through hole 15B, and the base portion 32B is accommodated in the first step portion G1. The protruding portion P of 32B is inserted into the groove L of the first step portion G1.

【００５０】ここで、第１段差部Ｇ１の溝Ｌ内と、第１
段差部Ｇ１の溝Ｌの両側に沿った部分にのみ接着剤４が
塗布され、第１段差部Ｇ１と基部３２Ｂとを接着してい
る。従って、凸部３１Ｂと貫通孔１５Ｂの内壁との間に
は接着剤４が存在せず間隙となっている。Here, in the groove L of the first step portion G1 and the first step
The adhesive 4 is applied only to the portions of the step portion G1 along both sides of the groove L to bond the first step portion G1 and the base portion 32B. Therefore, the adhesive 4 does not exist between the convex portion 31B and the inner wall of the through hole 15B, and there is a gap.

【００５１】また、第１段差部Ｇ１の開口寸法は基部３
２Ｂの寸法に比べて大きく、基部３２Ｂを収容しても、
基部３２Ｂの端縁部と第１段差部Ｇ１の内壁面との間に
は空間的に余裕があるように構成されている。The opening size of the first step portion G1 is the same as that of the base portion 3.
Larger than the size of 2B, even if the base 32B is housed,
There is a spatial allowance between the edge of the base 32B and the inner wall surface of the first step G1.

【００５２】ここで、基部３２Ｂの端縁部と第１段差部
Ｇ１の内壁面との間隔、および凸部３１Ｂと貫通孔１５
Ｂの内壁との間隔は、基部３２Ｂおよび凸部３１Ｂのそ
れぞれの平面方向の長さの１０％〜２０％程度を目安と
して設定される。Here, the distance between the edge of the base portion 32B and the inner wall surface of the first step portion G1, and the convex portion 31B and the through hole 15 are provided.
The distance between B and the inner wall is set to about 10% to 20% of the length of each of the base portion 32B and the convex portion 31B in the plane direction as a guide.

【００５３】以上説明したように本発明に係る半導体パ
ッケージＢは、凸部３１Ｂと貫通孔１５Ｂの内壁との間
には接着剤４が存在せず間隙となっているので、熱サイ
クルにより平面方向の応力が凸部３１Ｂおよび貫通孔１
５Ｂに与えられることが防止される。また、基部３２Ｂ
の端縁部と第１段差部Ｇ１の内壁面との間には空間的に
余裕があるように構成されているので、熱サイクルによ
り平面方向の応力が基部３２Ｂの端縁部および第１段差
部Ｇ１の内壁面に加わることが防止され、第１段差部Ｇ
１の段差部Ｇ１と基部３２Ｂとの間に塗布された接着剤
４に応力が加わることが抑制され、接着剤４が剥離して
隙間が生じることが防止される。As described above, in the semiconductor package B according to the present invention, since the adhesive 4 does not exist between the convex portion 31B and the inner wall of the through hole 15B, there is a gap, so that the thermal cycle leads to a planar direction. Is applied to the convex portion 31B and the through hole 1.
5B is prevented from being given. Also, the base 32B
Since there is a spatial margin between the edge of the base and the inner wall surface of the first step G1, the stress in the plane direction due to the thermal cycle causes the stress in the plane direction to the edge of the base 32B and the first step. It is prevented from being applied to the inner wall surface of the portion G1, and the first step portion G
It is suppressed that stress is applied to the adhesive 4 applied between the stepped portion G1 of No. 1 and the base portion 32B, and the adhesive 4 is prevented from peeling to form a gap.

【００５４】さらに、基部３２Ｂが突出部Ｐを有し、突
出部Ｐが接着剤４を塗布された第１段差部Ｇ１の溝Ｌ内
に挿入されているので、載置台３Ｂとパッケージ基板５
Ａとの接触部分が入り組んだ構造となり、空気および水
分の侵入が阻止され半導体集積回路１の気密性を高める
ことができる。Further, since the base portion 32B has the protruding portion P and the protruding portion P is inserted into the groove L of the first step portion G1 coated with the adhesive 4, the mounting table 3B and the package substrate 5 are arranged.
Since the contact portion with A has a complicated structure, the invasion of air and moisture can be prevented and the airtightness of the semiconductor integrated circuit 1 can be enhanced.

【００５５】＜第３の実施例＞図６に本発明に係る半導
体パッケージの第３の実施例として、半導体パッケージ
Ｃの部分断面図を示す。なお、半導体パッケージＣの正
面図は図１に示した半導体パッケージＡと同様であるの
で省略する。なお、図６は図１のＡ−Ａ線と同じ位置で
の部分断面図である。また、図１〜図３を用いて説明し
た第１の実施例と同一の構成については同一の符号を付
し、重複する説明は省略する。<Third Embodiment> FIG. 6 shows a partial cross-sectional view of a semiconductor package C as a third embodiment of the semiconductor package according to the present invention. The front view of the semiconductor package C is the same as that of the semiconductor package A shown in FIG. 6 is a partial cross-sectional view at the same position as the line AA in FIG. Further, the same components as those in the first embodiment described with reference to FIGS. 1 to 3 are designated by the same reference numerals, and the duplicate description will be omitted.

【００５６】図６に示すように、パッケージ基板５Ｃ
は、その中央部に貫通孔１５Ｃを備えている。貫通孔１
５Ｃの平面視形状は略矩形であり、第１主面から第２主
面にかけて貫通しており、第１および第２主面側の開口
部にそれぞれ段差部を有している。以後、第１主面の側
に設けられた段差部を第１段差部Ｇ１と呼称し、第２主
面の側に設けられた段差部を第２段差部Ｇ２と呼称す
る。第１段差部Ｇ１には、貫通孔１５Ｃを取り囲むよう
に溝Ｌ１が設けられている。As shown in FIG. 6, the package substrate 5C
Has a through hole 15C in the center thereof. Through hole 1
5C has a substantially rectangular shape in a plan view, penetrates from the first main surface to the second main surface, and has step portions in the openings on the first and second main surface sides, respectively. Hereinafter, the step portion provided on the first main surface side is referred to as a first step portion G1, and the step portion provided on the second main surface side is referred to as a second step portion G2. A groove L1 is provided in the first step portion G1 so as to surround the through hole 15C.

【００５７】半導体集積回路１は平面視形状が略矩形の
金属製の載置台３Ｃに接着された状態でパッケージ基板
５Ｃの第１主面側から貫通孔１５Ｃ内に挿入され、接着
剤４によってパッケージ基板５Ｃに接着されている。The semiconductor integrated circuit 1 is inserted into the through hole 15C from the first main surface side of the package substrate 5C in a state of being adhered to the metal mounting table 3C having a substantially rectangular shape in a plan view, and the package is bonded by the adhesive 4. It is adhered to the substrate 5C.

【００５８】ここで、載置台３Ｃの構成は、図５を用い
て説明した載置台３Ｂと同様に、その主面上に半導体集
積回路１を載置した状態で貫通孔１５Ｃ内に挿入される
凸部３１Ｃと、凸部３１Ｃよりも広い基部３２Ｃとで構
成され、基部３２Ｃは第１段差部Ｇ１に設けられた溝Ｌ
１に対応するように突出部Ｐ１が設けられている。突出
部Ｐ１の高さは、載置台３Ｃに設けられた突出部Ｐより
も若干低く形成され、溝Ｌ１内に塗布される後に説明す
る粘性樹脂に接触する程度の長さとなっている。なお、
凸部３１Ｃおよび基部３２Ｃは一体で形成されている。Here, the mounting table 3C has a structure similar to that of the mounting table 3B described with reference to FIG. 5, and is inserted into the through hole 15C with the semiconductor integrated circuit 1 mounted on the main surface thereof. It is composed of a convex portion 31C and a base portion 32C wider than the convex portion 31C, and the base portion 32C is a groove L provided in the first step portion G1.
The protrusion P1 is provided so as to correspond to 1. The height of the protrusion P1 is slightly lower than that of the protrusion P provided on the mounting table 3C, and is long enough to come into contact with the viscous resin which will be described later after being applied in the groove L1. In addition,
The convex portion 31C and the base portion 32C are integrally formed.

【００５９】図６に示すように載置台３Ｃは、半導体集
積回路１を載置した凸部３１Ｃが貫通孔１５Ｃ内に挿入
されると共に、基部３２Ｃが第１段差部Ｇ１内に収容さ
れ、基部３２Ｃの突出部Ｐ１が第１段差部Ｇ１の溝Ｌ１
内に挿入されている。As shown in FIG. 6, in the mounting table 3C, the convex portion 31C on which the semiconductor integrated circuit 1 is mounted is inserted into the through hole 15C, and the base portion 32C is housed in the first step portion G1. The protrusion P1 of 32C is the groove L1 of the first step G1.
Has been inserted inside.

【００６０】ここで、第１段差部Ｇ１の溝Ｌ１内には粘
性の高い液状の樹脂（以後「粘性樹脂」と呼称）８、例
えばシリコン樹脂が塗布され、第１段差部Ｇ１の溝Ｌ１
の両側に沿った部分にのみ接着剤４が塗布され、基部３
２Ｃを第１段差部Ｇ１内に挿入することで、突出部Ｐ１
が粘性樹脂８に接触し、接着剤４によって第１段差部Ｇ
１と基部３２Ｂとが接着される。従って、凸部３１Ｃと
貫通孔１５Ｃの内壁との間には接着剤４が存在せず間隙
となっている。Here, a highly viscous liquid resin (hereinafter referred to as "viscous resin") 8, for example, silicon resin, is applied in the groove L1 of the first step portion G1, and the groove L1 of the first step portion G1 is applied.
The adhesive 4 is applied only to the parts along both sides of the base 3
By inserting 2C into the first step G1, the protrusion P1
Contact the viscous resin 8 and the adhesive 4 causes the first step G
1 and the base 32B are bonded. Therefore, the adhesive 4 does not exist between the convex portion 31C and the inner wall of the through hole 15C, and there is a gap.

【００６１】また、第１段差部Ｇ１の開口寸法は基部３
２Ｃの寸法に比べて大きく、基部３２Ｃを収容しても、
基部３２Ｃの端縁部と第１段差部Ｇ１の内壁面との間に
は空間的に余裕があるように構成されている。The opening size of the first step portion G1 is determined by the base 3
It is larger than the size of 2C and accommodates the base 32C,
There is a space between the edge of the base 32C and the inner wall surface of the first step G1.

【００６２】ここで、基部３２Ｃの端縁部と第１段差部
Ｇ１の内壁面との間隔、および凸部３１Ｃと貫通孔１５
Ｃの内壁との間隔は、基部３２Ｃおよび凸部３１Ｃのそ
れぞれの平面方向の長さの１０％〜２０％程度を目安と
して設定される。Here, the distance between the edge of the base portion 32C and the inner wall surface of the first step portion G1, and the convex portion 31C and the through hole 15 are formed.
The distance between C and the inner wall is set to approximately 10% to 20% of the length of each of the base portion 32C and the convex portion 31C in the plane direction.

【００６３】以上説明したように本発明に係る半導体パ
ッケージＣは、凸部３１Ｃと貫通孔１５Ｃの内壁との間
には接着剤４が存在せず間隙となっているので、熱サイ
クルにより平面方向の応力が凸部３１Ｃおよび貫通孔１
５Ｃに与えられることが防止される。また、基部３２Ｃ
の端縁部と第１段差部Ｇ１の内壁面との間には空間的に
余裕があるように構成されているので、熱サイクルによ
り平面方向の応力が基部３２Ｃの端縁部および第１段差
部Ｇ１の内壁面に加わることが防止され、第１段差部Ｇ
１と基部３２Ｃとの間に塗布された接着剤４に応力が加
わることが抑制され、接着剤４が剥離して隙間が生じる
ことが防止される。As described above, in the semiconductor package C according to the present invention, since the adhesive 4 does not exist between the convex portion 31C and the inner wall of the through hole 15C, there is a gap, so that the thermal cycle leads to a planar direction. Is applied to the convex portion 31C and the through hole 1.
It is prevented from being given to 5C. Also, the base 32C
Since there is a spatial margin between the edge of the base plate and the inner wall surface of the first step G1, the stress in the plane direction due to the thermal cycle causes an edge of the base 32C and the first step. It is prevented from being applied to the inner wall surface of the portion G1, and the first step portion G
It is suppressed that stress is applied to the adhesive 4 applied between 1 and the base portion 32C, and the adhesive 4 is prevented from peeling and a gap is generated.

【００６４】さらに、基部３２Ｃが突出部Ｐ１を有し、
突出部Ｐ１が第１段差部Ｇ１の溝Ｌ１内に塗布された粘
性樹脂８に接触するので、載置台３Ｃとパッケージ基板
５Ｃとの接触部分が入り組んだ構造になると共に、粘性
樹脂８により空気および水分の侵入が阻止され半導体集
積回路１の気密性を高めることができる。なお、突出部
Ｐ１は粘性樹脂８に埋まり込むような長さにしても良
い。Further, the base portion 32C has a protruding portion P1,
Since the protruding portion P1 contacts the viscous resin 8 applied in the groove L1 of the first step portion G1, the contact portion between the mounting table 3C and the package substrate 5C is intricate, and the viscous resin 8 prevents air and The invasion of water can be prevented and the airtightness of the semiconductor integrated circuit 1 can be improved. The protrusion P1 may have a length such that it is embedded in the viscous resin 8.

【００６５】ここで、粘性樹脂８を用いたのは、熱サイ
クルにより平面方向および垂直方向の応力が加わったと
しても、粘性を有するため突出部Ｐ１および溝Ｌ１に張
り付いて容易には隙間を生じることがないからである。Here, since the viscous resin 8 is used, even if stress in the plane direction and the vertical direction is applied due to the heat cycle, the viscous resin 8 sticks to the protrusion P1 and the groove L1 to easily form a gap. This is because it will not occur.

【００６６】＜第４の実施例＞図７に本発明に係る半導
体パッケージの第４の実施例として、半導体パッケージ
Ｄの部分断面図を示す。なお、半導体パッケージＤの正
面図は図１に示した半導体パッケージＡと同様であるの
で省略する。なお、図７は図１のＡ−Ａ線と同じ位置で
の部分断面図である。また、図１〜図３を用いて説明し
た第１の実施例と同一の構成については同一の符号を付
し、重複する説明は省略する。<Fourth Embodiment> FIG. 7 shows a partial sectional view of a semiconductor package D as a fourth embodiment of the semiconductor package according to the present invention. The front view of the semiconductor package D is the same as that of the semiconductor package A shown in FIG. Note that FIG. 7 is a partial cross-sectional view at the same position as the line AA in FIG. Further, the same components as those in the first embodiment described with reference to FIGS. 1 to 3 are designated by the same reference numerals, and the duplicate description will be omitted.

【００６７】図７に示すように、パッケージ基板５Ｄ
は、その中央部に貫通孔１５Ｄを備えている。貫通孔１
５Ｄの平面視形状は略矩形であり、第１主面から第２主
面にかけて貫通しており、第１および第２主面側の開口
部にそれぞれ段差部を有している。以後、第１主面の側
に設けられた段差部を第１段差部Ｇ１と呼称し、第２主
面の側に設けられた段差部を第２段差部Ｇ２と呼称す
る。第１段差部Ｇ１には、貫通孔１５Ｄを取り囲むよう
に溝Ｌ２が設けられている。As shown in FIG. 7, the package substrate 5D
Has a through hole 15D in the center thereof. Through hole 1
The plan view shape of 5D is substantially rectangular, penetrates from the first main surface to the second main surface, and has step portions at the openings on the first and second main surface sides, respectively. Hereinafter, the step portion provided on the first main surface side is referred to as a first step portion G1, and the step portion provided on the second main surface side is referred to as a second step portion G2. A groove L2 is provided in the first step portion G1 so as to surround the through hole 15D.

【００６８】半導体集積回路１は平面視形状が略矩形の
金属製の載置台３Ｄに接着された状態でパッケージ基板
５Ｄの第１主面側から貫通孔１５Ｄ内に挿入され、接着
剤４によってパッケージ基板５Ｄに接着されている。The semiconductor integrated circuit 1 is inserted into the through hole 15D from the first main surface side of the package substrate 5D in a state of being adhered to the metal mounting table 3D having a substantially rectangular shape in a plan view, and the package is formed by the adhesive 4 It is adhered to the substrate 5D.

【００６９】ここで、図７に示すように、載置台３Ｄは
その主面上に半導体集積回路１を載置した状態で貫通孔
１５Ｄ内に挿入される凸部３１Ｄと、凸部３１Ｄよりも
広い基部３２Ｄとで構成され、基部３２Ｄは第１段差部
Ｇ１に設けられた溝Ｌ２に対応するように溝Ｌ３が設け
られている。なお、凸部３１Ｄおよび基部３２Ｄは一体
で形成されている。Here, as shown in FIG. 7, the mounting table 3D has a protrusion 31D to be inserted into the through hole 15D with the semiconductor integrated circuit 1 placed on the main surface thereof, and a protrusion 31D. The base 32D has a wide base 32D, and the base 32D is provided with a groove L3 corresponding to the groove L2 provided in the first step G1. The convex portion 31D and the base portion 32D are integrally formed.

【００７０】図８に半導体集積回路１を載置した状態の
載置台３Ｄの斜視図を示す。図８に示すように載置台３
Ｄは、半導体集積回路１を載置した凸部３１Ｄが貫通孔
１５Ｄ内に挿入されると共に、基部３２Ｄが第１段差部
Ｇ１内に収容される。FIG. 8 is a perspective view of the mounting table 3D on which the semiconductor integrated circuit 1 is mounted. As shown in FIG.
In D, the convex portion 31D on which the semiconductor integrated circuit 1 is mounted is inserted into the through hole 15D, and the base portion 32D is accommodated in the first step portion G1.

【００７１】ここで、溝Ｌ２内（または溝Ｌ３内）に
は、例えば弾力のある樹脂、プラスチックなどの高分子
材料、あるいはシリコンゴムなどで形成された気密リン
グ９がが配置されており、第１段差部Ｇ１の溝Ｌ２の両
側に沿った部分にのみ接着剤４が塗布され、基部３２Ｄ
を第１段差部Ｇ１内に挿入することで、気密リング９が
溝Ｌ２および溝Ｌ３の底面に接触して押しつぶされ、接
着剤４によって第１段差部Ｇ１と基部３２Ｄとが接着さ
れる。従って、凸部３１Ｄと貫通孔１５Ｃの内壁との間
には接着剤４が存在せず間隙となっている。ここで、気
密リング９の断面の直径は、接着剤４を間に挟んで、溝
Ｌ２および溝Ｌ３を向かい合わせたときに形成される空
間よりも若干大きく形成されている。Here, in the groove L2 (or in the groove L3), an airtight ring 9 made of, for example, an elastic resin, a polymeric material such as plastic, or silicon rubber is arranged. The adhesive 4 is applied only to the portions of the step portion G1 along both sides of the groove L2.
Is inserted into the first step portion G1, the airtight ring 9 comes into contact with the bottom surfaces of the grooves L2 and L3 and is crushed, and the first step portion G1 and the base portion 32D are bonded by the adhesive 4. Therefore, the adhesive 4 does not exist between the convex portion 31D and the inner wall of the through hole 15C, and there is a gap. Here, the diameter of the cross section of the airtight ring 9 is formed to be slightly larger than the space formed when the groove L2 and the groove L3 are opposed to each other with the adhesive 4 interposed therebetween.

【００７２】また、第１段差部Ｇ１の開口寸法は基部３
２Ｄの寸法に比べて大きく、基部３２Ｄを収容しても、
基部３２Ｄの端縁部と第１段差部Ｇ１の内壁面との間に
は空間的に余裕があるように構成されている。The opening size of the first step portion G1 is determined by the base 3
Larger than the size of 2D, even if the base 32D is housed,
There is a spatial margin between the edge of the base 32D and the inner wall surface of the first step G1.

【００７３】ここで、基部３２Ｄの端縁部と第１段差部
Ｇ１の内壁面との間隔、および凸部３１Ｄと貫通孔１５
Ｄの内壁との間隔は、基部３２Ｄおよび凸部３１Ｄのそ
れぞれの平面方向の長さの１０％〜２０％程度を目安と
して設定される。Here, the distance between the edge of the base portion 32D and the inner wall surface of the first step portion G1, and the convex portion 31D and the through hole 15 are formed.
The distance between D and the inner wall is set to approximately 10% to 20% of the length of each of the base portion 32D and the convex portion 31D in the plane direction.

【００７４】以上説明したように本発明に係る半導体パ
ッケージＤは、凸部３１Ｄと貫通孔１５Ｄの内壁との間
には接着剤４が存在せず間隙となっているので、熱サイ
クルにより平面方向の応力が凸部３１Ｄおよび貫通孔１
５Ｄに与えられることが防止される。また、基部３２Ｄ
の端縁部と第１段差部Ｇ１の内壁面との間には空間的に
余裕があるように構成されているので、熱サイクルによ
り平面方向の応力が基部３２Ｄの端縁部および第１段差
部Ｇ１の内壁面に加わることが防止され、第１段差部Ｇ
１と基部３２Ｄとの間に塗布された接着剤４に応力が加
わることが抑制され、接着剤４が剥離して隙間が生じる
ことが防止される。As described above, in the semiconductor package D according to the present invention, since the adhesive 4 does not exist between the convex portion 31D and the inner wall of the through hole 15D and there is a gap, the planar direction due to the heat cycle. Is applied to the convex portion 31D and the through hole 1.
It is prevented from being given to 5D. Also, the base 32D
Since there is a spatial margin between the edge of the base 32D and the inner wall surface of the first step G1, the stress in the planar direction due to the thermal cycle causes an edge of the base 32D and the first step. It is prevented from being applied to the inner wall surface of the portion G1, and the first step portion G
Stress is suppressed from being applied to the adhesive 4 applied between 1 and the base portion 32D, and the adhesive 4 is prevented from peeling and a gap is generated.

【００７５】さらに、第１段差部Ｇ１が溝Ｌ２を有し、
基部３２Ｄが溝Ｌ３を有し、溝Ｌ２および溝Ｌ３を向か
い合わせたときに形成される空間内に、溝Ｌ２および溝
Ｌ３の底面に接触して押しつぶされた気密リング９を有
しているので、気密リング９により空気および水分の侵
入が阻止され半導体集積回路１の気密性を高めることが
できる。Further, the first step portion G1 has a groove L2,
Since the base portion 32D has the groove L3 and the airtight ring 9 crushed in contact with the bottom surfaces of the groove L2 and the groove L3 in the space formed when the groove L2 and the groove L3 face each other. The airtight ring 9 prevents the invasion of air and moisture and enhances the airtightness of the semiconductor integrated circuit 1.

【００７６】ここで、弾力のある樹脂、プラスチックな
どの高分子材料、あるいはシリコンゴムなどで形成され
た気密リング９を用いるのは、熱サイクルにより平面方
向および垂直方向の応力が加わったとしても、粘弾力性
を有するため溝Ｌ２および溝Ｌ３の内部に密着して容易
には隙間を生じることがないと共に、第３の実施例で説
明した粘性樹脂８に比べて取り扱いが簡単だからであ
る。Here, the use of the airtight ring 9 made of an elastic resin, a polymer material such as plastic, or silicon rubber, even if stress in the plane direction and the vertical direction is applied by the heat cycle, This is because it has viscoelasticity so that it does not come into close contact with the insides of the grooves L2 and L3 to easily form a gap, and it is easier to handle than the viscous resin 8 described in the third embodiment.

【００７７】なお、以上の説明では気密リング９の縦断
面形状は円形であるとしたが、断面形状が矩形であって
も良い。Although the airtight ring 9 has a circular cross section in the above description, it may have a rectangular cross section.

【００７８】＜第５の実施例＞図９に本発明に係る半導
体パッケージの第５の実施例として、半導体パッケージ
Ｅの部分断面図を示す。なお、半導体パッケージＥの正
面図は図１に示した半導体パッケージＡと同様であるの
で省略する。なお、図９は図１のＡ−Ａ線と同じ位置で
の部分断面図である。また、図１〜図３を用いて説明し
た第１の実施例と同一の構成については同一の符号を付
し、重複する説明は省略する。<Fifth Embodiment> FIG. 9 shows a partial sectional view of a semiconductor package E as a fifth embodiment of the semiconductor package according to the present invention. The front view of the semiconductor package E is the same as the semiconductor package A shown in FIG. Note that FIG. 9 is a partial cross-sectional view at the same position as the line AA in FIG. Further, the same components as those in the first embodiment described with reference to FIGS. 1 to 3 are designated by the same reference numerals, and the duplicate description will be omitted.

【００７９】図９に示すように、パッケージ基板５Ｅ
は、その中央部に貫通孔１５Ｅを備えている。貫通孔１
５Ｅの平面視形状は略矩形であり、第１主面から第２主
面にかけて貫通しており、第１および第２主面側の開口
部にそれぞれ段差部を有している。以後、第１主面の側
に設けられた段差部を第１段差部Ｇ１と呼称し、第２主
面の側に設けられた段差部を第２段差部Ｇ２と呼称す
る。第１段差部Ｇ１には、貫通孔１５Ｅを取り囲むよう
に突出部Ｐ２が設けられている。As shown in FIG. 9, the package substrate 5E
Has a through hole 15E in the center thereof. Through hole 1
The planar view shape of 5E is substantially rectangular, penetrates from the first main surface to the second main surface, and has step portions in the openings on the first and second main surface sides, respectively. Hereinafter, the step portion provided on the first main surface side is referred to as a first step portion G1, and the step portion provided on the second main surface side is referred to as a second step portion G2. The first step G1 is provided with a protrusion P2 so as to surround the through hole 15E.

【００８０】半導体集積回路１は平面視形状が略矩形の
金属製の載置台３Ｅに接着された状態でパッケージ基板
５Ｅの第１主面側から貫通孔１５Ｅ内に挿入され、接着
剤４によってパッケージ基板５Ｅに接着されている。The semiconductor integrated circuit 1 is inserted into the through hole 15E from the first main surface side of the package substrate 5E in a state of being adhered to the metal mounting table 3E having a substantially rectangular shape in a plan view, and the package 4 by the adhesive 4 It is adhered to the substrate 5E.

【００８１】ここで、載置台３Ｅの構成は、図８を用い
て説明した載置台３Ｄと同様に、その主面上に半導体集
積回路１を載置した状態で貫通孔１５Ｅ内に挿入される
凸部３１Ｅと、凸部３１Ｅよりも広い基部３２Ｅとで構
成され、基部３２Ｅは第１段差部Ｇ１に設けられた突出
部Ｐ２に対応するように溝Ｌ４が設けられている。溝Ｌ
４の溝幅は、載置台３Ｄに設けられた溝Ｌ３よりも若干
広く形成されている。なお、凸部３１Ｅおよび基部３２
Ｅは一体で形成されている。Here, the structure of the mounting table 3E is inserted into the through hole 15E with the semiconductor integrated circuit 1 mounted on the main surface thereof, as in the mounting table 3D described with reference to FIG. It is composed of a convex portion 31E and a base portion 32E wider than the convex portion 31E, and the base portion 32E is provided with a groove L4 so as to correspond to the protruding portion P2 provided in the first step portion G1. Groove L
The groove width of No. 4 is slightly wider than the groove L3 provided on the mounting table 3D. Incidentally, the convex portion 31E and the base portion 32
E is integrally formed.

【００８２】図９に示すように載置台３Ｅは、半導体集
積回路１を載置した凸部３１Ｅが貫通孔１５Ｅ内に挿入
されると共に、基部３２Ｅが第１段差部Ｇ１内に収容さ
れ、突出部Ｐ２が載置台３Ｅの溝Ｌ４内に挿入されてい
る。As shown in FIG. 9, in the mounting table 3E, the convex portion 31E on which the semiconductor integrated circuit 1 is mounted is inserted into the through hole 15E, and the base portion 32E is accommodated in the first step portion G1 to project. The portion P2 is inserted into the groove L4 of the mounting table 3E.

【００８３】ここで、載置台３Ｅの溝Ｌ４内と、第１段
差部Ｇ１の突出部Ｐ２の両側に沿った部分にのみ接着剤
４が塗布され、第１段差部Ｇ１と基部３２Ｂとを接着し
ている。従って、凸部３１Ｂと貫通孔１５Ｂの内壁との
間には接着剤４が存在せず間隙となっている。Here, the adhesive 4 is applied only to the inside of the groove L4 of the mounting table 3E and to the portions along both sides of the protrusion P2 of the first step portion G1 to bond the first step portion G1 and the base portion 32B. are doing. Therefore, the adhesive 4 does not exist between the convex portion 31B and the inner wall of the through hole 15B, and there is a gap.

【００８４】また、第１段差部Ｇ１の開口寸法は基部３
２Ｅの寸法に比べて大きく、基部３２Ｅを収容しても、
基部３２Ｅの端縁部と第１段差部Ｇ１の内壁面との間に
は空間的に余裕があるように構成されている。The opening size of the first step portion G1 is determined by the base 3
Larger than the size of 2E, even if the base 32E is housed,
There is a spatial allowance between the edge of the base 32E and the inner wall surface of the first step G1.

【００８５】ここで、基部３２Ｅの端縁部と第１段差部
Ｇ１の内壁面との間隔、および凸部３１Ｅと貫通孔１５
Ｅの内壁との間隔は、基部３２Ｅおよび凸部３１Ｅのそ
れぞれの平面方向の長さの１０％〜２０％程度を目安と
して設定される。Here, the distance between the edge portion of the base portion 32E and the inner wall surface of the first step portion G1, and the convex portion 31E and the through hole 15 are formed.
The distance between E and the inner wall is set to be about 10% to 20% of the length of each of the base portion 32E and the convex portion 31E in the plane direction.

【００８６】以上説明したように本発明に係る半導体パ
ッケージＥは、凸部３１Ｅと貫通孔１５Ｅの内壁との間
には接着剤４が存在せず間隙となっているので、熱サイ
クルにより平面方向の応力が凸部３１Ｅおよび貫通孔１
５Ｅに与えられることが防止される。また、基部３２Ｅ
の端縁部と第１段差部Ｇ１の内壁面との間には空間的に
余裕があるように構成されているので、熱サイクルによ
り平面方向の応力が基部３２Ｅの端縁部および第１段差
部Ｇ１の内壁面に加わることが防止され、第１段差部Ｇ
１と基部３２Ｅとの間に塗布された接着剤４に応力が加
わることが抑制され、接着剤４が剥離して隙間が生じる
ことが防止される。As described above, in the semiconductor package E according to the present invention, since the adhesive 4 does not exist between the convex portion 31E and the inner wall of the through hole 15E, there is a gap, so that the thermal cycle causes a planar direction. Is applied to the convex portion 31E and the through hole 1.
It is prevented from being given to 5E. Also, the base 32E
Since there is a spatial allowance between the edge of the base and the inner wall surface of the first step G1, the stress in the planar direction due to the thermal cycle causes an edge of the base 32E and the first step. It is prevented from being applied to the inner wall surface of the portion G1, and the first step portion G
1 is suppressed from being applied to the adhesive 4 applied between the base 1 and the base portion 32E, and the adhesive 4 is prevented from peeling to form a gap.

【００８７】さらに、第１段差部Ｇ１が突出部Ｐ２を有
し、突出部Ｐ２が接着剤４を塗布された基部３２Ｅの溝
Ｌ４内に挿入され、接着剤４に接触しているので、載置
台３Ｅとパッケージ基板５Ｅとの接触部分が入り組んだ
構造となり、空気および水分の侵入が阻止され半導体集
積回路１の気密性を高めることができる。Further, since the first step portion G1 has the protruding portion P2, and the protruding portion P2 is inserted into the groove L4 of the base portion 32E coated with the adhesive agent 4 and is in contact with the adhesive agent 4, it is mounted. Since the contact portion between the mounting table 3E and the package substrate 5E is intricately structured, invasion of air and moisture is prevented, and the airtightness of the semiconductor integrated circuit 1 can be enhanced.

【００８８】＜変形例＞以上説明した本発明に係る半導
体パッケージの第５の実施例では、基部３２Ｅは第１段
差部Ｇ１に設けられた突出部Ｐ２に対応するように溝Ｌ
４が設けられ、第１段差部Ｇ１には、貫通孔１５Ｅを取
り囲むように突出部Ｐ２が設けられ、突出部Ｐ２が接着
剤４を塗布された基部３２Ｅの溝Ｌ４内に挿入され、接
着剤４に接触する構成となっているが、図１０に示すよ
うに、接着剤４の代わりに溝Ｌ４内に粘性樹脂８を塗布
し、突出部Ｐ２の高さを、塗布された粘性樹脂８に接触
する程度として、粘性樹脂８により空気および水分の侵
入が阻止され半導体集積回路１の気密性を高めても良
い。なお、この場合溝Ｌ４の溝幅および溝深さは、図６
を用いて説明した第３の実施例の溝Ｌ１に準じる。<Modification> In the fifth embodiment of the semiconductor package according to the present invention described above, the base 32E is provided with the groove L so as to correspond to the protrusion P2 provided in the first step G1.
4 is provided, the first stepped portion G1 is provided with a protrusion P2 so as to surround the through hole 15E, and the protrusion P2 is inserted into the groove L4 of the base 32E coated with the adhesive 4, 4, the viscous resin 8 is applied in the groove L4 instead of the adhesive 4, and the height of the protrusion P2 is changed to the applied viscous resin 8 as shown in FIG. As the degree of contact, the viscous resin 8 may prevent the invasion of air and moisture to enhance the airtightness of the semiconductor integrated circuit 1. In this case, the groove width and the groove depth of the groove L4 are as shown in FIG.
This is the same as the groove L1 of the third embodiment described using.

【００８９】＜第６の実施例＞図１１に本発明に係る半
導体パッケージの第６の実施例として、半導体パッケー
ジＦの部分断面図を示す。なお、半導体パッケージＦの
正面図は図１に示した半導体パッケージＡと同様である
ので省略する。なお、図１１は図１のＡ−Ａ線と同じ位
置での部分断面図である。また、図１〜図３を用いて説
明した第１の実施例と同一の構成については同一の符号
を付し、重複する説明は省略する。<Sixth Embodiment> FIG. 11 shows a partial sectional view of a semiconductor package F as a sixth embodiment of the semiconductor package according to the present invention. The front view of the semiconductor package F is the same as that of the semiconductor package A shown in FIG. Note that FIG. 11 is a partial cross-sectional view at the same position as the line AA in FIG. Further, the same components as those in the first embodiment described with reference to FIGS. 1 to 3 are designated by the same reference numerals, and the duplicate description will be omitted.

【００９０】図１１に示すように、パッケージ基板５Ｆ
は、その中央部に貫通孔１５Ｆを備えている。貫通孔１
５Ｆの平面視形状は略矩形であり、第１主面から第２主
面にかけて貫通しており、第１および第２主面側の開口
部にそれぞれ段差部を有している。以後、第１主面の側
に設けられた段差部を第１段差部Ｇ１と呼称し、第２主
面の側に設けられた段差部を第２段差部Ｇ２と呼称す
る。As shown in FIG. 11, the package substrate 5F
Has a through hole 15F in the center thereof. Through hole 1
The plan view shape of 5F is substantially rectangular, penetrates from the first main surface to the second main surface, and has step portions in the openings on the first and second main surface sides, respectively. Hereinafter, the step portion provided on the first main surface side is referred to as a first step portion G1, and the step portion provided on the second main surface side is referred to as a second step portion G2.

【００９１】半導体集積回路１は平面視形状が略矩形の
金属製の載置台３Ｆに接着された状態でパッケージ基板
５Ｆの第１主面側から貫通孔１５Ｆ内に挿入され、接着
剤４によってパッケージ基板５Ｆに接着されている。The semiconductor integrated circuit 1 is inserted into the through hole 15F from the first main surface side of the package substrate 5F in a state where it is adhered to the metal mounting table 3F having a substantially rectangular shape in plan view, and the package is formed by the adhesive 4 It is adhered to the substrate 5F.

【００９２】ここで、図１２に半導体集積回路１が接着
された状態の載置台３Ｆの斜視図を示す。図１２に示す
ように、載置台３Ｆはその主面上に半導体集積回路１を
載置した状態で貫通孔１５Ｄ内に挿入される凸部３１Ｆ
と、凸部３１Ｆよりも広い基部３２Ｆとで構成されてい
る。さらに、凸部３１Ｆは材質の違いによって凸部外枠
体３１１および凸部内部体３１２に分割される構成とな
っている。Here, FIG. 12 shows a perspective view of the mounting table 3F with the semiconductor integrated circuit 1 bonded thereto. As shown in FIG. 12, the mounting table 3F has a convex portion 31F inserted into the through hole 15D with the semiconductor integrated circuit 1 mounted on the main surface thereof.
And a base portion 32F wider than the convex portion 31F. Further, the convex portion 31F is divided into a convex outer frame body 311 and a convex inner body 312 depending on the material.

【００９３】図１３に、凸部３１Ｆを凸部外枠体３１１
と凸部内部体３１２とに分割した状態の斜視図を示す。
図１３に示すように、凸部外枠体３１１は、無底かつ無
蓋で、凸部内部体３１２が挿入される箱型形状であり、
その外形形状および外形寸法は、凸部３１Ｆの外形形状
および外形寸法を規定した構成となっている。また、一
方の端部には端縁部沿って鍔部を有している。In FIG. 13, the convex portion 31F is shown as the convex outer frame 311.
3 is a perspective view showing a state in which it is divided into a convex inner body 312 and a convex inner body 312. FIG.
As shown in FIG. 13, the convex outer frame body 311 is a bottom-shaped and lidless box-shaped body into which the convex inner body 312 is inserted.
The outer shape and the outer dimension thereof are configured to define the outer shape and the outer dimension of the convex portion 31F. Further, the one end has a flange along the edge.

【００９４】凸部内部体３１２は基部３２Ｆと一体で形
成されており、その外形形状および外形寸法は、凸部外
枠体３１１の貫通孔の内形形状および内形寸法に応じて
形成され、また、凸部内部体３１２の周囲の基部３２Ｆ
の表面は凸部外枠体３１１の鍔部の外形形状および外形
寸法に合わせて座ぐりを施された座ぐり部となってい
る。従って、凸部内部体３１２を凸部外枠体３１１に挿
入すると、基部３２Ｆの表面の座ぐり部に凸部外枠体３
１１の鍔部が係合し、凸部外枠体３１１と凸部内部体３
１２とが一体化して載置台３Ｆが形をなすことになる。The convex inner body 312 is formed integrally with the base 32F, and its outer shape and outer dimension are formed in accordance with the inner shape and inner dimension of the through hole of the protruding outer frame 311. In addition, the base 32F around the convex inner body 312
The surface of is a counterbore part which is countersunk according to the outer shape and outer dimensions of the flange part of the outer convex frame 311. Therefore, when the convex inner body 312 is inserted into the convex outer frame 311, the convex outer frame 3 is attached to the counterbore on the surface of the base 32F.
The flange portion 11 is engaged, and the convex outer frame body 311 and the convex inner body 3
12 and 12 are integrated to form the mounting table 3F.

【００９５】ここで、凸部外枠体３１１の材質は、その
熱膨張係数が凸部内部体３１２を含む基部３２Ｆの材質
の熱膨張係数と、パッケージ基板５Ｆの材質の熱膨張係
数との中間程度となるような材質を用いる。Here, the material of the convex outer frame body 311 is such that the coefficient of thermal expansion is between the coefficient of thermal expansion of the material of the base 32F including the convex inner body 312 and the coefficient of thermal expansion of the material of the package substrate 5F. Use a material that is suitable.

【００９６】また、凸部外枠体３１１の鍔部の外形寸法
は、基部３２Ｆを第１段差部Ｇ１に収容した場合に、凸
部外枠体３１１の鍔部が第１段差部Ｇ１に塗布される接
着剤４の塗布部分に係合するように規定される。Further, the outer dimensions of the flange portion of the convex outer frame body 311 are such that the flange portion of the convex outer frame body 311 is applied to the first step portion G1 when the base portion 32F is housed in the first step portion G1. Is defined to engage the applied portion of the adhesive 4.

【００９７】図１１に示すように載置台３Ｆは、半導体
集積回路１を載置した凸部３１Ｆが貫通孔１５Ｆ内に挿
入されると共に、基部３２Ｆが第１段差部Ｇ１内に収容
されている。As shown in FIG. 11, in the mounting table 3F, the convex portion 31F on which the semiconductor integrated circuit 1 is mounted is inserted into the through hole 15F, and the base portion 32F is housed in the first step portion G1. .

【００９８】ここで、第１段差部Ｇ１と基部３２Ｆとの
間にのみ接着剤４が塗布され、第１段差部Ｇ１と基部３
２Ｆとを接着している。従って、凸部３１Ｆと貫通孔１
５Ｆの内壁との間には接着剤４が存在せず間隙となって
いる。Here, the adhesive 4 is applied only between the first step portion G1 and the base portion 32F, and the first step portion G1 and the base portion 3 are formed.
It is adhered to 2F. Therefore, the convex portion 31F and the through hole 1
The adhesive 4 does not exist between the inner wall of 5F and the inner wall, which is a gap.

【００９９】また、第１段差部Ｇ１の開口寸法は基部３
２Ｆの寸法に比べて大きく、基部３２Ｆを収容しても、
基部３２Ｆの端縁部と第１段差部Ｇ１の内壁面との間に
は空間的に余裕があるように構成されている。The opening size of the first step portion G1 is determined by the base 3
Larger than the size of 2F, even if the base 32F is housed,
There is a spatial margin between the edge of the base 32F and the inner wall surface of the first step G1.

【０１００】ここで、基部３２Ｆの端縁部と第１段差部
Ｇ１の内壁面との間隔、および凸部３１Ｆと貫通孔１５
Ｆの内壁との間隔は、基部３２Ｆおよび凸部３１Ｆのそ
れぞれの平面方向の長さの１０％〜２０％程度を目安と
して設定される。Here, the interval between the edge portion of the base portion 32F and the inner wall surface of the first step portion G1 and the convex portion 31F and the through hole 15 are formed.
The distance between F and the inner wall is set to approximately 10% to 20% of the length of each of the base portion 32F and the convex portion 31F in the plane direction.

【０１０１】以上説明したように本発明に係る半導体パ
ッケージＦは、凸部３１Ｆと貫通孔１５Ｆの内壁との間
には接着剤４が存在せず間隙となっているので、熱サイ
クルにより平面方向の応力が凸部３１Ｆおよび貫通孔１
５Ｆに与えられることが防止される。また、基部３２Ｆ
の端縁部と第１段差部Ｇ１の内壁面との間には空間的に
余裕があるように構成されているので、熱サイクルによ
り平面方向の応力が基部３２Ｆの端縁部および第１段差
部Ｇ１の内壁面に加わることが防止され、第１段差部Ｇ
１と基部３２Ｆとの間に塗布された接着剤４に応力が加
わることが抑制され、接着剤４が剥離して隙間が生じる
ことが防止される。As described above, in the semiconductor package F according to the present invention, since the adhesive 4 does not exist between the convex portion 31F and the inner wall of the through hole 15F, there is a gap, so that the thermal cycle causes a planar direction. Is applied to the convex portion 31F and the through hole 1.
It is prevented from being given to 5F. Also, the base 32F
Since there is a spatial margin between the edge of the base and the inner wall surface of the first step G1, the stress in the plane direction due to the thermal cycle causes the stress in the planar direction and the edge of the base 32F and the first step. It is prevented from being applied to the inner wall surface of the portion G1, and the first step portion G
It is suppressed that stress is applied to the adhesive 4 applied between the base 1 and the base 32F, and the adhesive 4 is prevented from peeling to form a gap.

【０１０２】さらに、凸部３１Ｆは材質の違いによって
凸部外枠体３１１および凸部内部体３１２に分割される
構成となっており、凸部外枠体３１１の材質は、その熱
膨張係数が凸部内部体３１２を含む基部３２Ｆの材質の
熱膨張係数と、パッケージ基板５Ｆの材質の熱膨張係数
との中間程度となるような材質となっているので、第１
段差部Ｇ１と基部３２Ｆとの間に塗布された接着剤４に
加わる応力が減少し、接着剤４が剥離して隙間が生じる
ことが防止される。Furthermore, the convex portion 31F is divided into a convex outer frame body 311 and a convex inner body 312 according to the difference in material, and the material of the convex outer frame body 311 has a coefficient of thermal expansion. Since the material is such that the coefficient of thermal expansion of the material of the base portion 32F including the convex inner body 312 and the coefficient of thermal expansion of the material of the package substrate 5F are about the middle,
The stress applied to the adhesive agent 4 applied between the step portion G1 and the base portion 32F is reduced, and the adhesive agent 4 is prevented from peeling off to form a gap.

【０１０３】＜第７の実施例＞図１４に本発明に係る半
導体パッケージの第７の実施例として、半導体パッケー
ジＧの部分断面図を示す。なお、半導体パッケージＧの
正面図は図１に示した半導体パッケージＡと同様である
ので省略する。なお、図１４は図１のＡ−Ａ線と同じ位
置での部分断面図である。また、図１〜図３を用いて説
明した第１の実施例と同一の構成については同一の符号
を付し、重複する説明は省略する。<Seventh Embodiment> FIG. 14 shows a partial sectional view of a semiconductor package G as a seventh embodiment of the semiconductor package according to the present invention. The front view of the semiconductor package G is the same as the semiconductor package A shown in FIG. Note that FIG. 14 is a partial cross-sectional view at the same position as the line AA in FIG. Further, the same components as those in the first embodiment described with reference to FIGS. 1 to 3 are designated by the same reference numerals, and the duplicate description will be omitted.

【０１０４】図１４に示すように、パッケージ基板５Ｇ
は、その中央部に貫通孔１５Ｇを備えている。貫通孔１
５Ｇの平面視形状は略矩形であり、第１主面から第２主
面にかけて貫通しており、第１および第２主面側の開口
部にそれぞれ段差部を有している。以後、第１主面の側
に設けられた段差部を第１段差部Ｇ１と呼称し、第２主
面の側に設けられた段差部を第２段差部Ｇ２と呼称す
る。As shown in FIG. 14, the package substrate 5G
Has a through hole 15G in the center thereof. Through hole 1
The plan view shape of 5G is substantially rectangular, penetrates from the first main surface to the second main surface, and has step portions in the openings on the first and second main surface sides, respectively. Hereinafter, the step portion provided on the first main surface side is referred to as a first step portion G1, and the step portion provided on the second main surface side is referred to as a second step portion G2.

【０１０５】半導体集積回路１は平面視形状が略矩形の
金属製の載置台３Ｇに接着された状態でパッケージ基板
５Ｇの第１主面側から貫通孔１５Ｇ内に挿入され、接着
剤４によってパッケージ基板５Ｇに接着されている。The semiconductor integrated circuit 1 is inserted into the through hole 15G from the first main surface side of the package substrate 5G in a state of being adhered to the metal mounting table 3G having a substantially rectangular shape in plan view, and the package 4 is formed by the adhesive 4 It is adhered to the substrate 5G.

【０１０６】ここで、載置台３Ｇの構成を図１５に示す
斜視図を用いて説明する。載置台３Ｇは、半導体集積回
路１を載置した状態で貫通孔１５Ｇ内に挿入される凸部
３１Ｇと、凸部３１Ｇよりも広い基部３２Ｇとで構成さ
れ、凸部３１Ｇおよび基部３２Ｇの材質は異なり、分割
される構成となっており、凸部３１Ｇおよび基部３２Ｇ
を接着することで載置台３Ｇの形をなすことになる。Here, the structure of the mounting table 3G will be described with reference to the perspective view shown in FIG. The mounting table 3G includes a convex portion 31G that is inserted into the through hole 15G with the semiconductor integrated circuit 1 mounted thereon, and a base portion 32G that is wider than the convex portion 31G. The convex portion 31G and the base portion 32G are made of a material. Differently, it is divided and has a convex portion 31G and a base portion 32G.
By adhering to each other, the mounting table 3G is formed.

【０１０７】ここで、凸部３１Ｇの材質は、その熱膨張
係数が基部３２Ｇの材質の熱膨張係数と、パッケージ基
板５Ｇの材質の熱膨張係数との中間程度となるような材
質を用いる。Here, the material of the convex portion 31G is such that the coefficient of thermal expansion thereof is approximately between the coefficient of thermal expansion of the material of the base portion 32G and the coefficient of thermal expansion of the material of the package substrate 5G.

【０１０８】図１４に示すように載置台３Ｇは、半導体
集積回路１を載置した凸部３１Ｇが貫通孔１５Ｇ内に挿
入されると共に、基部３２Ｇが第１段差部Ｇ１内に収容
されている。第１段差部Ｇ１の開口寸法は基部３２Ｇの
寸法に比べて大きく、基部３２Ｇを収容しても、基部３
２Ｇの端縁部と第１段差部Ｇ１の内壁面との間には空間
的に余裕があるように構成されている。As shown in FIG. 14, in the mounting table 3G, the convex portion 31G on which the semiconductor integrated circuit 1 is mounted is inserted into the through hole 15G, and the base portion 32G is housed in the first step portion G1. . The opening size of the first step G1 is larger than the size of the base 32G, and even if the base 32G is housed, the base 3
There is a spatial allowance between the edge of 2G and the inner wall surface of the first step G1.

【０１０９】ここで、第１段差部Ｇ１と基部３２Ｇとの
間にのみ接着剤４が塗布され、第１段差部Ｇ１と基部３
２Ｇとを接着している。従って、凸部３１Ｇと貫通孔１
５Ｇの内壁との間には接着剤４が存在せず間隙となって
いる。また、基部３２Ｇの端縁部と第１段差部Ｇ１の内
壁面との間隔は平面方向の長さの１０％〜２０％程度を
目安として設定される。Here, the adhesive 4 is applied only between the first step G1 and the base 32G, and the first step G1 and the base 3 are applied.
It is bonded to 2G. Therefore, the convex portion 31G and the through hole 1
The adhesive 4 does not exist between the inner wall of 5G and the inner wall of 5G. The distance between the edge of the base portion 32G and the inner wall surface of the first step portion G1 is set to approximately 10% to 20% of the length in the plane direction as a guide.

【０１１０】以上説明したように本発明に係る半導体パ
ッケージＧは、凸部３１Ｇと貫通孔１５Ｇの内壁との間
には接着剤４が存在せず間隙となっているので、熱サイ
クルにより平面方向の応力が凸部３１Ｇおよび貫通孔１
５Ｇに与えられることが防止される。また、基部３２Ｇ
の端縁部と第１段差部Ｇ１の内壁面との間には空間的に
余裕があるように構成されているので、熱サイクルによ
り平面方向の応力が基部３２Ｇの端縁部および第１段差
部Ｇ１の内壁面に加わることが防止され、第１段差部Ｇ
１と基部３２Ｇとの間に塗布された接着剤４に応力が加
わることが抑制され、接着剤４が剥離して隙間が生じる
ことが防止される。As described above, in the semiconductor package G according to the present invention, since the adhesive 4 does not exist between the convex portion 31G and the inner wall of the through hole 15G, there is a gap, so that the thermal cycle causes a planar direction. Is applied to the convex portion 31G and the through hole 1.
It is prevented from being given to 5G. Also, the base 32G
Since there is a spatial allowance between the end edge of the base 32G and the inner wall surface of the first step G1, the stress in the planar direction due to the thermal cycle causes the stress in the planar direction to increase at the end of the base 32G and the first step. It is prevented from being applied to the inner wall surface of the portion G1, and the first step portion G
It is suppressed that stress is applied to the adhesive 4 applied between 1 and the base portion 32G, and the adhesive 4 is prevented from peeling and a gap is generated.

【０１１１】また、凸部３１Ｇおよび基部３２Ｇの材質
が異なり、凸部３１Ｇの熱膨張係数は基部３２Ｇの材質
の熱膨張係数と、パッケージ基板５Ｇの材質の熱膨張係
数との中間程度となるような材質を用いているので、凸
部３１Ｇと貫通孔１５Ｇの内壁との間隔を、基部３２Ｇ
の端縁部と第１段差部Ｇ１の内壁面との間隔よりも狭く
しても、凸部３１Ｇと貫通孔１５Ｇの内壁との間に応力
が加わることが防止され、凸部３１Ｇと貫通孔１５Ｇの
内壁との間隔を広くした場合に生じる、載置台３Ｇの位
置決めのばらつきを抑制することができる。Further, the materials of the convex portion 31G and the base portion 32G are different, and the thermal expansion coefficient of the convex portion 31G is about the middle of the thermal expansion coefficient of the material of the base portion 32G and the thermal expansion coefficient of the material of the package substrate 5G. Since different materials are used, the distance between the convex portion 31G and the inner wall of the through hole 15G can be set to the base portion 32G.
Even if the distance is smaller than the distance between the edge portion of the first step portion G1 and the inner wall surface of the first step portion G1, stress is prevented from being applied between the convex portion 31G and the inner wall of the through hole 15G, and the convex portion 31G and the through hole are formed. It is possible to suppress variations in the positioning of the mounting table 3G, which occurs when the distance between the inner wall of 15G and the inner wall is increased.

【０１１２】＜第８の実施例＞図１６に本発明に係る半
導体パッケージの第８の実施例として、半導体パッケー
ジＨの部分断面図を示す。なお、半導体パッケージＨの
正面図は図１に示した半導体パッケージＡとほぼ同様で
あるので省略する。なお、図１６は図１のＡ−Ａ線と同
じ位置での部分断面図である。また、図１〜図３を用い
て説明した第１の実施例と同一の構成については同一の
符号を付し、重複する説明は省略する。<Eighth Embodiment> FIG. 16 shows a partial sectional view of a semiconductor package H as an eighth embodiment of the semiconductor package according to the present invention. The front view of the semiconductor package H is almost the same as the semiconductor package A shown in FIG. Note that FIG. 16 is a partial cross-sectional view at the same position as the line AA in FIG. Further, the same components as those in the first embodiment described with reference to FIGS. 1 to 3 are designated by the same reference numerals, and the duplicate description will be omitted.

【０１１３】図１６に示すように、パッケージ基板５Ｈ
は、その中央部に貫通孔１５Ｈを備えている。貫通孔１
５Ｈの平面視形状は略矩形であり、第１主面から第２主
面にかけて貫通しており、第１および第２主面側の開口
部にそれぞれ段差部を有している。以後、第１主面の側
に設けられた段差部を第１段差部Ｇ１と呼称し、第２主
面の側に設けられた段差部を第２段差部Ｇ２と呼称す
る。As shown in FIG. 16, the package substrate 5H
Has a through hole 15H in the center thereof. Through hole 1
The plan view shape of 5H is substantially rectangular, penetrates from the first main surface to the second main surface, and has step portions at the openings on the first and second main surface sides, respectively. Hereinafter, the step portion provided on the first main surface side is referred to as a first step portion G1, and the step portion provided on the second main surface side is referred to as a second step portion G2.

【０１１４】半導体集積回路１は平面視形状が略矩形の
金属製の載置台３Ｈに接着された状態でパッケージ基板
５Ｈの第１主面側から貫通孔１５Ｈ内に挿入され、接着
剤４によってパッケージ基板５Ｈに接着されている。The semiconductor integrated circuit 1 is inserted into the through hole 15H from the first main surface side of the package substrate 5H in a state of being adhered to the metal mounting table 3H having a substantially rectangular shape in a plan view, and the package 4 by the adhesive 4 It is adhered to the substrate 5H.

【０１１５】ここで、載置台３Ｈの構成を図１７に示す
斜視図を用いて説明する。載置台３Ｈは、半導体集積回
路１を載置した状態で貫通孔１５Ｈ内に挿入される凸部
３１Ｈと、凸部３１Ｈよりも広い基部３２Ｈとで構成さ
れている。また、凸部３１Ｈは半導体集積回路１が載置
される載置部３１３と、載置部３１３と基部３２Ｈとの
間に設けられる中間部３１４とで構成されている。Here, the structure of the mounting table 3H will be described with reference to the perspective view shown in FIG. The mounting table 3H includes a convex portion 31H that is inserted into the through hole 15H with the semiconductor integrated circuit 1 mounted thereon, and a base portion 32H that is wider than the convex portion 31H. In addition, the convex portion 31H includes a mounting portion 313 on which the semiconductor integrated circuit 1 is mounted and an intermediate portion 314 provided between the mounting portion 313 and the base portion 32H.

【０１１６】基部３２Ｈおよび載置部３１３、中間部３
１４の材質はそれぞれ異なり、基部３２Ｈおよび載置部
３１３、中間部３１４をそれぞれ接着することで載置台
３Ｈの形をなすことになる。Base portion 32H, placing portion 313, intermediate portion 3
The materials of 14 are different, and the base 32H, the mounting portion 313, and the intermediate portion 314 are adhered to each other to form the mounting table 3H.

【０１１７】ここで、中間部３１４の材質は、その熱膨
張係数が基部３２Ｈの材質の熱膨張係数と、パッケージ
基板５Ｇの材質の熱膨張係数との中間程度となるような
材質を用い、載置部３１３の材質は、その熱膨張係数が
基部３２Ｈの材質の熱膨張係数と、半導体集積回路１の
基板（半導体層を形成する基板のことで、シリコン基板
やＧａＡｓ基板などの半導体基板）の材質の熱膨張係数
との中間程度となるような材質を用いる。Here, as the material of the intermediate portion 314, a material having a coefficient of thermal expansion intermediate between the coefficient of thermal expansion of the material of the base portion 32H and the coefficient of thermal expansion of the material of the package substrate 5G is used. The material of the mounting portion 313 has a coefficient of thermal expansion that is the same as that of the material of the base portion 32H and the substrate of the semiconductor integrated circuit 1 (a substrate on which a semiconductor layer is formed, such as a silicon substrate or a GaAs substrate). Use a material that is about the middle of the thermal expansion coefficient of the material.

【０１１８】図１６に示すように載置台３Ｈは、半導体
集積回路１を載置した凸部３１Ｈが貫通孔１５Ｈ内に挿
入されると共に、基部３２Ｈが第１段差部Ｇ１内に収容
されている。第１段差部Ｇ１の開口寸法は基部３２Ｈの
寸法に比べて大きく、基部３２Ｈを収容しても、基部３
２Ｈの端縁部と第１段差部Ｇ１の内壁面との間には空間
的に余裕があるように構成されている。As shown in FIG. 16, in the mounting table 3H, the convex portion 31H on which the semiconductor integrated circuit 1 is mounted is inserted into the through hole 15H, and the base portion 32H is housed in the first step portion G1. . The opening size of the first step G1 is larger than the size of the base 32H, and even if the base 32H is housed, the base 3
There is a spatial allowance between the edge of 2H and the inner wall surface of the first step G1.

【０１１９】ここで、第１段差部Ｇ１と基部３２Ｈとの
間にのみ接着剤４が塗布され、第１段差部Ｇ１と基部３
２Ｈとを接着している。従って、凸部３１Ｈと貫通孔１
５Ｈの内壁との間には接着剤４が存在せず間隙となって
いる。また、基部３２Ｈの端縁部と第１段差部Ｇ１の内
壁面との間隔は平面方向の長さの１０％〜２０％程度を
目安として設定される。Here, the adhesive 4 is applied only between the first step portion G1 and the base portion 32H, and the first step portion G1 and the base portion 3 are formed.
It is bonded to 2H. Therefore, the convex portion 31H and the through hole 1
The adhesive 4 does not exist between the inner wall of 5H and the inner wall, and a gap is formed. The distance between the edge of the base portion 32H and the inner wall surface of the first step portion G1 is set to about 10% to 20% of the length in the plane direction as a guide.

【０１２０】以上説明したように本発明に係る半導体パ
ッケージＨは、凸部３１Ｈと貫通孔１５Ｈの内壁との間
には接着剤４が存在せず間隙となっているので、熱サイ
クルにより平面方向の応力が凸部３１Ｈおよび貫通孔１
５Ｈに与えられることが防止される。また、基部３２Ｈ
の端縁部と第１段差部Ｇ１の内壁面との間には空間的に
余裕があるように構成されているので、熱サイクルによ
り平面方向の応力が基部３２Ｈの端縁部および第１段差
部Ｇ１の内壁面に加わることが防止され、第１段差部Ｇ
１と基部３２Ｈとの間に塗布された接着剤４に応力が加
わることが抑制され、接着剤４が剥離して隙間が生じる
ことが防止される。As described above, in the semiconductor package H according to the present invention, since the adhesive 4 does not exist between the convex portion 31H and the inner wall of the through hole 15H, there is a gap. Is applied to the convex portion 31H and the through hole 1.
It is prevented from being given to 5H. Also, the base 32H
Since there is a spatial allowance between the edge of the base and the inner wall surface of the first step G1, the stress in the planar direction due to the heat cycle causes the stress in the plane direction to go to the edge of the base 32H and the first step. It is prevented from being applied to the inner wall surface of the portion G1, and the first step portion G
It is suppressed that stress is applied to the adhesive 4 applied between the base 1 and the base 32H, and the adhesive 4 is prevented from peeling and a gap is generated.

【０１２１】また、基部３２Ｈおよび載置部３１３、中
間部３１４の材質はそれぞれ異なり、中間部３１４の熱
膨張係数が、基部３２Ｈの材質の熱膨張係数と、パッケ
ージ基板５Ｇの材質の熱膨張係数との中間程度となるよ
うな材質を用いているので、中間部３１４と貫通孔１５
Ｈの内壁との間隔を、基部３２Ｈの端縁部と第１段差部
Ｇ１の内壁面との間隔よりも狭くしても、中間部３１４
と貫通孔１５Ｈの内壁との間に応力が加わることが防止
され、中間部３１４と貫通孔１５Ｇの内壁との間隔を広
くした場合に生じる、載置台３Ｈの位置決めのばらつき
を抑制することができ、さらに、載置部３１３の熱膨張
係数が、基部３２Ｈの材質の熱膨張係数と、半導体集積
回路１の基板の材質の熱膨張係数との中間程度となるよ
うな材質を用いているので、半導体集積回路１の基板が
熱膨張係数の違いにより載置台３Ｈから剥離することが
防止される。The materials of the base portion 32H, the mounting portion 313, and the intermediate portion 314 are different from each other, and the thermal expansion coefficient of the intermediate portion 314 is the thermal expansion coefficient of the material of the base portion 32H and the thermal expansion coefficient of the material of the package substrate 5G. Since it is made of a material that is in the middle between the intermediate portion 314 and the through hole 15,
Even if the distance between the inner wall of H and the inner wall of the first step G1 is smaller than the distance between the edge of the base 32H and the inner wall of the first step G1, the middle portion 314
It is possible to prevent stress from being applied between the inner wall of the through hole 15H and the through hole 15H, and to suppress variations in positioning of the mounting table 3H that occur when the distance between the intermediate portion 314 and the inner wall of the through hole 15G is increased. Further, since the thermal expansion coefficient of the mounting portion 313 is about the intermediate between the thermal expansion coefficient of the material of the base 32H and the thermal expansion coefficient of the material of the substrate of the semiconductor integrated circuit 1, It is possible to prevent the substrate of the semiconductor integrated circuit 1 from peeling off from the mounting table 3H due to the difference in thermal expansion coefficient.

【０１２２】＜第９の実施例＞図１８に本発明に係る半
導体パッケージの第９の実施例として、半導体パッケー
ジＩの部分断面図を示す。なお、半導体パッケージＩの
正面図は図１に示した半導体パッケージＡとほぼ同様で
あるので省略する。なお、図１８は図１のＡ−Ａ線と同
じ位置での部分断面図である。また、図１〜図３を用い
て説明した第１の実施例と同一の構成については同一の
符号を付し、重複する説明は省略する。<Ninth Embodiment> FIG. 18 shows a partial sectional view of a semiconductor package I as a ninth embodiment of the semiconductor package according to the present invention. The front view of the semiconductor package I is almost the same as the semiconductor package A shown in FIG. Note that FIG. 18 is a partial cross-sectional view at the same position as the line AA in FIG. Further, the same components as those in the first embodiment described with reference to FIGS. 1 to 3 are designated by the same reference numerals, and the duplicate description will be omitted.

【０１２３】図１８に示すように、パッケージ基板５Ｉ
は、その中央部に貫通孔１５Ｉを備えている。貫通孔１
５Ｉの平面視形状は略矩形であり、第１主面から第２主
面にかけて貫通しており、第１および第２主面側の開口
部にそれぞれ段差部を有している。以後、第１主面の側
に設けられた段差部を第１段差部Ｇ１と呼称し、第２主
面の側に設けられた段差部を第２段差部Ｇ２と呼称す
る。As shown in FIG. 18, the package substrate 5I
Has a through hole 15I at its center. Through hole 1
The shape of 5I in a plan view is substantially rectangular, penetrates from the first main surface to the second main surface, and has step portions in the openings on the first and second main surface sides, respectively. Hereinafter, the step portion provided on the first main surface side is referred to as a first step portion G1, and the step portion provided on the second main surface side is referred to as a second step portion G2.

【０１２４】半導体集積回路１は平面視形状が略矩形の
金属製の載置台３Ｉに接着された状態でパッケージ基板
５Ｉの第１主面側から貫通孔１５Ｉ内に挿入され、接着
剤４によってパッケージ基板５Ｉに接着されている。The semiconductor integrated circuit 1 is inserted into the through hole 15I from the first main surface side of the package substrate 5I in a state of being adhered to the metal mounting table 3I having a substantially rectangular shape in a plan view, and the package 4 by the adhesive 4 It is adhered to the substrate 5I.

【０１２５】ここで、載置台３Ｉの構成を図１９に示す
斜視図を用いて説明する。載置台３Ｉは、半導体集積回
路１を載置した状態で貫通孔１５Ｉ内に挿入される凸部
３１Ｉと、凸部３１Ｉよりも広い基部３２Ｉとで構成さ
れている。さらに、凸部３１Ｉは、材質の違いによって
凸部外枠体３１５および凸部内部体３１６と、半導体集
積回路１が載置される載置部３１７とに分割されてい
る。なお、基部３２Ｉと凸部内部体３１６とは一体で形
成されている。Here, the structure of the mounting table 3I will be described with reference to the perspective view shown in FIG. The mounting table 3I includes a convex portion 31I inserted into the through hole 15I in a state where the semiconductor integrated circuit 1 is mounted, and a base portion 32I wider than the convex portion 31I. Furthermore, the convex portion 31I is divided into a convex outer frame body 315 and a convex inner body 316, and a mounting portion 317 on which the semiconductor integrated circuit 1 is mounted, depending on the difference in material. The base 32I and the convex inner body 316 are integrally formed.

【０１２６】凸部外枠体３１５は、無底かつ無蓋で凸部
内部体３１６に挿入される箱型形状であって、その外形
形状および外形寸法は、凸部３１Ｉの外形形状および外
形寸法を規定している。The convex outer frame 315 has a box-like shape that is inserted into the convex inner body 316 without a bottom and without a lid, and its outer shape and outer dimensions are the same as those of the convex portion 31I. Stipulates.

【０１２７】また、載置部３１７は凸部３１Ｉの主面上
および外周部３１の端面上に設けられ、凸部外枠体３１
５および載置部３１６をそれぞれ接合することで載置台
３Ｉの形をなすことになる。The mounting portion 317 is provided on the main surface of the convex portion 31I and on the end surface of the outer peripheral portion 31, and the convex portion outer frame body 31 is provided.
5 and the mounting portion 316 are joined together to form the mounting table 3I.

【０１２８】ここで、凸部外枠体３１５の材質は、その
熱膨張係数が基部３２Ｉおよび凸部内部体３１６の材質
の熱膨張係数と、パッケージ基板５Ｉの材質の熱膨張係
数との中間程度となるような材質を用い、載置部３１７
の材質は、その熱膨張係数が基部３２Ｉおよび凸部内部
体３１６の材質の熱膨張係数と、半導体集積回路１の基
板の材質の熱膨張係数との中間程度となるような材質を
用いる。Here, the material of the convex outer frame body 315 is such that its coefficient of thermal expansion is intermediate between the coefficient of thermal expansion of the material of the base portion 32I and the convex inner body 316 and the coefficient of thermal expansion of the material of the package substrate 5I. And a mounting part 317
The material of is used such that its coefficient of thermal expansion is approximately between the coefficient of thermal expansion of the material of the base portion 32I and the convex inner body 316 and the coefficient of thermal expansion of the material of the substrate of the semiconductor integrated circuit 1.

【０１２９】図１８に示すように載置台３Ｉは、半導体
集積回路１を載置した凸部３１Ｉが貫通孔１５Ｉ内に挿
入されると共に、基部３２Ｉが第１段差部Ｇ１内に収容
されている。第１段差部Ｇ１の開口寸法は基部３２Ｉの
寸法に比べて大きく、基部３２Ｉを収容しても、基部３
２Ｉの端縁部と第１段差部Ｇ１の内壁面との間には空間
的に余裕があるように構成されている。As shown in FIG. 18, in the mounting table 3I, the convex portion 31I on which the semiconductor integrated circuit 1 is mounted is inserted into the through hole 15I, and the base portion 32I is housed in the first step portion G1. . The opening size of the first step G1 is larger than the size of the base 32I, and even if the base 32I is housed, the base 3
There is a space between the edge of 2I and the inner wall surface of the first step G1.

【０１３０】ここで、第１段差部Ｇ１と基部３２Ｉとの
間にのみ接着剤４が塗布され、第１段差部Ｇ１と基部３
２Ｉとを接着している。従って、凸部３１Ｉと貫通孔１
５Ｉの内壁との間には接着剤４が存在せず間隙となって
いる。また、基部３２Ｉの端縁部と第１段差部Ｇ１の内
壁面との間隔は平面方向の長さの１０％〜２０％程度を
目安として設定される。Here, the adhesive 4 is applied only between the first step portion G1 and the base portion 32I, and the first step portion G1 and the base portion 3 are formed.
2I is adhered. Therefore, the convex portion 31I and the through hole 1
The adhesive 4 does not exist between the inner wall of 5I and the inner wall of 5I. The distance between the edge of the base portion 32I and the inner wall surface of the first step portion G1 is set to approximately 10% to 20% of the length in the plane direction.

【０１３１】以上説明したように本発明に係る半導体パ
ッケージＩは、凸部３１Ｉと貫通孔１５Ｉの内壁との間
には接着剤４が存在せず間隙となっているので、熱サイ
クルにより平面方向の応力が凸部３１Ｉおよび貫通孔１
５Ｉに与えられることが防止される。また、基部３２Ｉ
の端縁部と第１段差部Ｇ１の内壁面との間には空間的に
余裕があるように構成されているので、熱サイクルによ
り平面方向の応力が基部３２Ｉの端縁部および第１段差
部Ｇ１の内壁面に加わることが防止され、第１段差部Ｇ
１と基部３２Ｉとの間に塗布された接着剤４に応力が加
わることが抑制され、接着剤４が剥離して隙間が生じる
ことが防止される。As described above, in the semiconductor package I according to the present invention, since the adhesive 4 does not exist between the convex portion 31I and the inner wall of the through hole 15I and there is a gap, the planar direction due to the thermal cycle is generated. Is applied to the convex portion 31I and the through hole 1.
5I is prevented from being given. Also, the base 32I
Since there is a spatial allowance between the edge of the base and the inner wall surface of the first step portion G1, the stress in the plane direction due to the thermal cycle causes the stress in the plane direction to the edge of the base 32I and the first step. It is prevented from being applied to the inner wall surface of the portion G1, and the first step portion G
It is suppressed that stress is applied to the adhesive 4 applied between the adhesive 1 and the base 32I, and the adhesive 4 is prevented from peeling to form a gap.

【０１３２】また、凸部外枠体３１５、凸部内部体３１
６、載置部３１７の材質はそれぞれ異なり、凸部外枠体
３１５の熱膨張係数が、基部３２Ｉおよび凸部内部体３
１６の材質の熱膨張係数と、パッケージ基板５Ｇの材質
の熱膨張係数との中間程度となるような材質を用いてい
るので、凸部外枠体３１５と貫通孔１５Ｉの内壁との間
隔を、基部３２Ｉの端縁部と第１段差部Ｇ１の内壁面と
の間隔よりも狭くしても、凸部外枠体３１５と貫通孔１
５Ｉの内壁との間に応力が加わることが防止され、凸部
３１Ｉと貫通孔１５Ｇの内壁との間隔を広くした場合に
生じる、載置台３Ｉの位置決めのばらつきを抑制するこ
とができ、さらに、載置部３１７の熱膨張係数が、基部
３２Ｉおよび凸部３１Ｉの材質の熱膨張係数と、半導体
集積回路１の基板の材質の熱膨張係数との中間程度とな
るような材質を用いているので、半導体集積回路１の基
板が熱膨張係数の違いにより載置台３Ｉから剥離するこ
とが防止される。Also, the convex outer frame body 315 and the convex inner body 31 are provided.
6, the material of the mounting portion 317 is different, and the thermal expansion coefficient of the convex outer frame body 315 is different from that of the base portion 32I and the convex inner body 3.
Since a material having an intermediate coefficient of thermal expansion between the material of No. 16 and the thermal expansion coefficient of the material of the package substrate 5G is used, the interval between the convex outer frame body 315 and the inner wall of the through hole 15I is Even if the distance between the edge of the base portion 32I and the inner wall surface of the first step portion G1 is narrower, the convex outer frame body 315 and the through hole 1
It is possible to prevent stress from being applied to the inner wall of 5I, and to suppress variations in positioning of the mounting table 3I that occur when the distance between the convex portion 31I and the inner wall of the through hole 15G is widened. Since the thermal expansion coefficient of the mounting portion 317 is approximately the intermediate between the thermal expansion coefficient of the material of the base portion 32I and the convex portion 31I and the thermal expansion coefficient of the material of the substrate of the semiconductor integrated circuit 1. The substrate of the semiconductor integrated circuit 1 is prevented from peeling off from the mounting table 3I due to the difference in thermal expansion coefficient.

【０１３３】＜第１０の実施例＞図２０に本発明に係る
半導体パッケージの第１０の実施例として、半導体パッ
ケージＪの部分断面図を示す。なお、半導体パッケージ
Ｊの正面図は図１に示した半導体パッケージＡとほぼ同
様であるので省略する。なお、図６は図１のＡ−Ａ線と
同じ位置での部分断面図である。また、図１〜図３を用
いて説明した第１の実施例と同一の構成については同一
の符号を付し、重複する説明は省略する。<Tenth Embodiment> FIG. 20 is a partial sectional view of a semiconductor package J as a tenth embodiment of the semiconductor package according to the present invention. The front view of the semiconductor package J is almost the same as the semiconductor package A shown in FIG. 6 is a partial cross-sectional view at the same position as the line AA in FIG. Further, the same components as those in the first embodiment described with reference to FIGS. 1 to 3 are designated by the same reference numerals, and the duplicate description will be omitted.

【０１３４】図２０に示すように、パッケージ基板５Ｊ
は、その中央部に貫通孔１５Ｊを備えている。貫通孔１
５Ｊの平面視形状は略矩形であり、第１主面から第２主
面にかけて貫通しており、第１および第２主面側の開口
部にそれぞれ段差部を有している。以後、第１主面の側
に設けられた段差部を第１段差部Ｇ１と呼称し、第２主
面の側に設けられた段差部を第２段差部Ｇ２と呼称す
る。As shown in FIG. 20, the package substrate 5J
Has a through hole 15J in the center thereof. Through hole 1
The plan view shape of 5J is substantially rectangular, penetrates from the first main surface to the second main surface, and has step portions in the openings on the first and second main surface sides, respectively. Hereinafter, the step portion provided on the first main surface side is referred to as a first step portion G1, and the step portion provided on the second main surface side is referred to as a second step portion G2.

【０１３５】半導体集積回路１は平面視形状が略矩形の
金属製の載置台３Ｊに接着された状態でパッケージ基板
５Ｊの第１主面側から貫通孔１５Ｊ内に挿入され、接着
剤４によってパッケージ基板５Ｊに接着されている。The semiconductor integrated circuit 1 is inserted into the through hole 15J from the first main surface side of the package substrate 5J in a state of being adhered to the metal mounting table 3J having a substantially rectangular shape in a plan view, and the package 4 by the adhesive 4 It is adhered to the substrate 5J.

【０１３６】ここで、載置台３Ｊの構成は、縦断面形状
が台形で、その上底側に半導体集積回路１を載置した状
態で貫通孔１５Ｊ内に挿入される凸部３１Ｊと、凸部３
１Ｊの下底側よりも広い基部３２Ｊとで構成されてい
る。ここで貫通孔１５Ｊの断面形状は載置台３Ｊの凸部
３１Ｊの断面形状に合わせたテーパ（第１主面方向に開
いたテーパ）を有する形状となっている。Here, the mounting table 3J has a trapezoidal vertical cross section, and the convex portion 31J and the convex portion which are inserted into the through hole 15J with the semiconductor integrated circuit 1 mounted on the upper bottom side thereof. Three
The base portion 32J is wider than the lower bottom side of 1J. Here, the cross-sectional shape of the through hole 15J is a shape having a taper (taper opened in the first main surface direction) that matches the cross-sectional shape of the convex portion 31J of the mounting table 3J.

【０１３７】図２０に示すように載置台３Ｊは、半導体
集積回路１を載置した凸部３１Ｊが貫通孔１５Ｊ内に挿
入され、第１段差部Ｇ１にのみ塗布された接着剤４によ
って接着されている。従って、凸部３１Ｊと貫通孔１５
Ｊの内壁との間には接着剤４が存在せず間隙となってい
る。As shown in FIG. 20, in the mounting table 3J, the convex portion 31J on which the semiconductor integrated circuit 1 is mounted is inserted into the through hole 15J and is bonded by the adhesive 4 applied only to the first step portion G1. ing. Therefore, the convex portion 31J and the through hole 15
The adhesive 4 does not exist between the inner wall of J and the inner wall of J.

【０１３８】また、第１段差部Ｇ１の開口寸法は基部３
２Ｊの寸法に比べて大きく、基部３２Ｊを収容しても、
基部３２Ｊの端縁部と第１段差部Ｇ１の内壁面との間に
は空間的に余裕があるように構成されている。The opening size of the first step portion G1 is determined by the base 3
It is larger than the size of 2J and accommodates the base 32J,
There is a spatial allowance between the edge of the base 32J and the inner wall surface of the first step G1.

【０１３９】ここで、基部３２Ｊの端縁部と第１段差部
Ｇ１の内壁面との間隔は、基部３２Ｃの平面方向の長さ
の１０％〜２０％程度を目安として設定されるが、凸部
３１Ｊと貫通孔１５Ｊの内壁との間隔は、凸部３１Ｊが
熱膨張した場合に貫通孔１５Ｊの内壁に接触するよう
に、熱膨張量を考慮して設定される。この値は、基部３
２Ｊの端縁部と第１段差部Ｇ１の内壁面との間隔の半分
以下を目安とする。Here, the distance between the edge of the base portion 32J and the inner wall surface of the first step portion G1 is set to about 10% to 20% of the length of the base portion 32C in the plane direction. The distance between the portion 31J and the inner wall of the through hole 15J is set in consideration of the amount of thermal expansion so that when the convex portion 31J thermally expands, it contacts the inner wall of the through hole 15J. This value is
As a guide, half or less of the distance between the edge portion of 2J and the inner wall surface of the first step portion G1 is used.

【０１４０】以上説明したように本発明に係る半導体パ
ッケージＪは、凸部３１Ｊの縦断面形状が台形であり、
貫通孔１５Ｊの縦断面形状が凸部３１Ｊの縦断面形状に
合わせたテーパを有する形状となっており、凸部３１Ｊ
と貫通孔１５Ｊの内壁との間隔は、凸部３１Ｊが熱膨張
した場合に貫通孔１５Ｊの内壁に接触するように、熱膨
張量を考慮して設定されているので、熱サイクルが加わ
ると凸部３１Ｊは平面方向だけでなく斜め下方向、すな
わち凸部３１Ｊの表面を貫通孔１５Ｊのテーパ面に押し
つける方向にも膨張し、凸部３１Ｊと貫通孔１５Ｊの内
壁とが係合することになる。従って、凸部３１Ｊは貫通
孔１５Ｊ内に密着することになり、凸部３１Ｊと貫通孔
１５Ｊとの間に隙間が生じることが防止され、空気およ
び水分の侵入が阻止され半導体集積回路１の気密性を高
めることができる。As described above, in the semiconductor package J according to the present invention, the protrusion 31J has a trapezoidal vertical cross section,
The vertical cross-sectional shape of the through hole 15J has a taper that matches the vertical cross-sectional shape of the convex portion 31J.
The distance between the inner wall of the through hole 15J and the inner wall of the through hole 15J is set in consideration of the thermal expansion amount so as to contact the inner wall of the through hole 15J when the convex portion 31J thermally expands. The portion 31J expands not only in the plane direction but also in an obliquely downward direction, that is, in the direction in which the surface of the convex portion 31J is pressed against the tapered surface of the through hole 15J, and the convex portion 31J and the inner wall of the through hole 15J engage with each other. . Therefore, the convex portion 31J comes into close contact with the through hole 15J, a gap is prevented from being formed between the convex portion 31J and the through hole 15J, air and moisture are prevented from entering, and the semiconductor integrated circuit 1 is hermetically sealed. You can improve your sex.

【０１４１】また、基部３２Ｊの端縁部と第１段差部Ｇ
１の内壁面との間には空間的に余裕があるように構成さ
れているので、熱サイクルにより平面方向の応力が基部
３２Ｊの端縁部および第１段差部Ｇ１の内壁面に加わる
ことが防止され、第１段差部Ｇ１と基部３２Ｊとの間に
塗布された接着剤４に応力が加わることが抑制され、接
着剤４が剥離して隙間が生じることが防止される。Further, the edge of the base 32J and the first step G
Since there is a space between the inner wall surface of No. 1 and the inner wall surface of No. 1, stress in the plane direction may be applied to the end edge portion of the base portion 32J and the inner wall surface of the first step portion G1 due to the heat cycle. This prevents the adhesive 4 applied between the first step portion G1 and the base portion 32J from being stressed, and prevents the adhesive 4 from peeling to form a gap.

【０１４２】＜変形例＞なお、以上説明した本発明に係
る半導体パッケージの第１〜第１０の実施例では、パッ
ケージ基板の第１主面側に段差部を設け、載置台の基部
を収容する構成について説明したが、図２２を用いて説
明した従来の半導体パッケージのように、載置台の基部
がパッケージ基板の第１主面上に突出する構成であって
も良い。その場合でも第１〜第１０の実施例で説明した
構成を適用することは問題ない。<Modification> In the first to tenth embodiments of the semiconductor package according to the present invention described above, the step portion is provided on the first main surface side of the package substrate to accommodate the base of the mounting table. Although the structure has been described, the base of the mounting table may project onto the first main surface of the package substrate, as in the conventional semiconductor package described with reference to FIG. Even in that case, there is no problem in applying the configurations described in the first to tenth embodiments.

【０１４３】また、以上説明した本発明に係る半導体パ
ッケージの第１〜第９の実施例では、載置台の凸部の形
状は縦断面形状を矩形として説明したが、第１０の実施
例に示すように縦断面形状を台形形状にしても良い。そ
の場合、貫通孔の縦断面形状は凸部の断面形状に合わせ
てテーパを有する形状とする。Further, in the first to ninth embodiments of the semiconductor package according to the present invention described above, the shape of the convex portion of the mounting table is explained as a rectangular vertical cross-sectional shape, but it is shown in the tenth embodiment. Thus, the vertical cross-sectional shape may be trapezoidal. In that case, the vertical cross-sectional shape of the through hole is tapered to match the cross-sectional shape of the convex portion.

【０１４４】また、以上説明した本発明に係る半導体パ
ッケージの第１〜第１０の実施例では、接着剤の特性に
ついては言及していないが、硬化後にも若干の粘度を有
するような材質のもの使用し、それを厚めに塗布するこ
とで熱サイクルによる平面方向の応力の吸収力を高めて
も良い。In the first to tenth embodiments of the semiconductor package according to the present invention described above, the characteristics of the adhesive are not mentioned, but the material having a slight viscosity even after curing is used. It is also possible to increase the absorption of the stress in the plane direction due to the heat cycle by using it and applying it thickly.

【０１４５】また、以上説明した本発明に係る半導体パ
ッケージの第１〜第１０の実施例では、載置台として金
属製のものを、パッケージ基板としてプラスチック基板
を例として説明したが、載置台が金属製で、パッケージ
基板がセラミック製であるような場合にも本発明を適用
できることは言うまでもない。Further, in the first to tenth embodiments of the semiconductor package according to the present invention described above, the mounting base is made of metal and the package substrate is made of the plastic substrate, but the mounting base is made of metal. Needless to say, the present invention can be applied to the case where the package substrate is made of ceramic and is made of ceramic.

【０１４６】[0146]

【発明の効果】本発明に係る請求項１記載の半導体パッ
ケージによれば、載置台が熱膨張した場合に、平面方向
の応力が凸部および貫通孔の内壁面に加わることが防止
され、塗布された接着剤に応力が加わることが抑制さ
れ、接着剤が剥離して隙間が生じることが防止されるの
で、隙間から侵入した空気および水分により半導体集積
回路が腐食したり、載置台の接着力が低下して、載置台
が脱落することが防止される。According to the semiconductor package of the first aspect of the present invention, when the mounting table is thermally expanded, the stress in the plane direction is prevented from being applied to the inner wall surfaces of the convex portion and the through hole, and the coating is performed. The applied adhesive is prevented from being stressed, and the adhesive is prevented from peeling off to form a gap. Therefore, air and moisture entering from the gap corrode the semiconductor integrated circuit, or the adhesive strength of the mounting table is increased. And the mounting table is prevented from falling off.

【０１４７】本発明に係る請求項２記載の半導体パッケ
ージによれば、載置台とパッケージ基板との接触部分が
入り組んだ構造となり、空気および水分の侵入が阻止さ
れ半導体集積回路の気密性を高めることができる。According to the second aspect of the semiconductor package of the present invention, the contact portion between the mounting table and the package substrate is intricately structured, and the invasion of air and moisture is prevented, and the airtightness of the semiconductor integrated circuit is improved. You can

【０１４８】本発明に係る請求項３記載の半導体パッケ
ージによれば、載置台とパッケージ基板との接触部分が
入り組んだ構造になると共に、粘性樹脂により空気およ
び水分の侵入が阻止され半導体集積回路の気密性を一層
高めることができる。According to the semiconductor package of claim 3 of the present invention, the contact portion between the mounting table and the package substrate is intricately structured, and the viscous resin prevents the intrusion of air and moisture, and Airtightness can be further enhanced.

【０１４９】本発明に係る請求項４記載の半導体パッケ
ージによれば、気密リングにより空気および水分の侵入
が阻止され半導体集積回路の気密性を高めることができ
る。According to the semiconductor package of the fourth aspect of the present invention, the airtight ring can prevent the invasion of air and moisture and enhance the airtightness of the semiconductor integrated circuit.

【０１５０】本発明に係る請求項５記載の半導体パッケ
ージによれば、載置台とパッケージ基板との接触部分が
入り組んだ構造となり、空気および水分の侵入が阻止さ
れ半導体集積回路の気密性を高めることができる。According to the semiconductor package of the fifth aspect of the present invention, the contact portion between the mounting table and the package substrate is intricately structured, and the invasion of air and moisture is prevented, and the airtightness of the semiconductor integrated circuit is improved. You can

【０１５１】本発明に係る請求項６記載の半導体パッケ
ージによれば、載置台とパッケージ基板との接触部分が
入り組んだ構造になると共に、粘性樹脂により空気およ
び水分の侵入が阻止され半導体集積回路の気密性を一層
高めることができる。According to the semiconductor package of the sixth aspect of the present invention, the contact portion between the mounting table and the package substrate is intricately structured, and the viscous resin prevents the intrusion of air and moisture, and Airtightness can be further enhanced.

【０１５２】本発明に係る請求項７記載の半導体パッケ
ージによれば、凸部と貫通孔の内壁との間隔を狭くする
ことができ、凸部と貫通孔の内壁との間隔を広くした場
合に生じる、載置台の位置決めのばらつきを抑制するこ
とができると共に、鍔部に接触するように塗布された接
着剤に加わる応力がさらに減少し、接着剤が剥離して隙
間が生じることが防止される。According to the semiconductor package of claim 7 of the present invention, it is possible to reduce the distance between the convex portion and the inner wall of the through hole, and to increase the distance between the convex portion and the inner wall of the through hole. It is possible to suppress the variation in the positioning of the mounting table that occurs, and further reduce the stress applied to the adhesive applied so as to come into contact with the collar portion, thereby preventing the adhesive from peeling and forming a gap. .

【０１５３】本発明に係る請求項８記載の半導体パッケ
ージによれば、凸部と貫通孔の内壁との間隔を広くした
場合に生じる、載置台の位置決めのばらつきを抑制する
ことができる。According to the semiconductor package of the eighth aspect of the present invention, it is possible to suppress the variation in the positioning of the mounting table which occurs when the distance between the convex portion and the inner wall of the through hole is widened.

【０１５４】本発明に係る請求項９記載の半導体パッケ
ージによれば、凸部と貫通孔の内壁との間隔を狭くする
ことができ、凸部と貫通孔の内壁との間隔を広くした場
合に生じる、載置台の位置決めのばらつきを抑制するこ
とができると共に、半導体集積回路の基板が熱膨張係数
の違いにより載置台から剥離することが防止される。According to the semiconductor package of claim 9 of the present invention, it is possible to narrow the gap between the convex portion and the inner wall of the through hole, and to widen the gap between the convex portion and the inner wall of the through hole. It is possible to suppress variations in the positioning of the mounting table that occur, and it is possible to prevent the substrate of the semiconductor integrated circuit from being separated from the mounting table due to the difference in thermal expansion coefficient.

【０１５５】本発明に係る請求項１０記載の半導体パッ
ケージによれば、凸部と貫通孔の内壁との間隔を狭くす
ることができ、凸部と貫通孔の内壁との間隔を広くした
場合に生じる、載置台の位置決めのばらつきを抑制する
ことができると共に、半導体集積回路の基板が熱膨張係
数の違いにより載置台から剥離することが防止される。According to the semiconductor package of the tenth aspect of the present invention, the distance between the convex portion and the inner wall of the through hole can be narrowed, and when the distance between the convex portion and the inner wall of the through hole is widened. It is possible to suppress variations in the positioning of the mounting table that occur, and it is possible to prevent the substrate of the semiconductor integrated circuit from being separated from the mounting table due to the difference in thermal expansion coefficient.

【０１５６】本発明に係る請求項１１記載の半導体パッ
ケージによれば、断面形状が台形形状の凸部が熱膨張に
より、凸部の表面を貫通孔のテーパ面に押しつける方向
に膨張し、凸部と貫通孔の内壁とが係合することにな
り、凸部と貫通孔との間に隙間が生じることが防止さ
れ、空気および水分の侵入が阻止され半導体集積回路の
気密性を高めることができる。According to the semiconductor package of the eleventh aspect of the present invention, the convex portion having a trapezoidal sectional shape expands in the direction in which the surface of the convex portion is pressed against the tapered surface of the through hole by thermal expansion, and the convex portion is formed. And the inner wall of the through hole are engaged with each other, a gap is prevented from being formed between the convex portion and the through hole, intrusion of air and moisture is prevented, and airtightness of the semiconductor integrated circuit can be improved. .

【０１５７】本発明に係る請求項１２記載の半導体パッ
ケージによれば、パッケージ基板の一方の主面の表面に
基部が突出せず、半導体パッケージの外形形状を平板に
保つことができる。また、載置台の熱膨張により塗布さ
れた接着剤に応力が加わることが抑制され、接着剤が剥
離して隙間が生じることが防止される。According to the twelfth aspect of the semiconductor package of the present invention, the base does not project to the surface of the one main surface of the package substrate, and the outer shape of the semiconductor package can be kept flat. Further, stress is suppressed from being applied to the applied adhesive due to thermal expansion of the mounting table, and it is possible to prevent the adhesive from peeling off to form a gap.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明に係る半導体パッケージの第１の実施
例を示す正面図である。FIG. 1 is a front view showing a first embodiment of a semiconductor package according to the present invention.

【図２】 本発明に係る半導体パッケージの第１の実施
例を示す断面図である。FIG. 2 is a cross-sectional view showing a first embodiment of a semiconductor package according to the present invention.

【図３】 本発明に係る半導体パッケージの第１の実施
例を示す部分断面図である。FIG. 3 is a partial sectional view showing a first embodiment of a semiconductor package according to the present invention.

【図４】 本発明に係る半導体パッケージの第２の実施
例を示す部分断面図である。FIG. 4 is a partial sectional view showing a second embodiment of the semiconductor package according to the present invention.

【図５】 本発明に係る半導体パッケージの第２の実施
例を示す斜視図である。FIG. 5 is a perspective view showing a second embodiment of the semiconductor package according to the present invention.

【図６】 本発明に係る半導体パッケージの第３の実施
例を示す部分断面図である。FIG. 6 is a partial sectional view showing a third embodiment of the semiconductor package according to the present invention.

【図７】 本発明に係る半導体パッケージの第４の実施
例を示す部分断面図である。FIG. 7 is a partial sectional view showing a fourth embodiment of the semiconductor package according to the present invention.

【図８】 本発明に係る半導体パッケージの第４の実施
例を示す斜視図である。FIG. 8 is a perspective view showing a fourth embodiment of the semiconductor package according to the present invention.

【図９】 本発明に係る半導体パッケージの第５の実施
例を示す部分断面図である。FIG. 9 is a partial sectional view showing a fifth embodiment of the semiconductor package according to the present invention.

【図１０】 本発明に係る半導体パッケージの変形例を
示す部分断面図である。FIG. 10 is a partial cross-sectional view showing a modified example of the semiconductor package according to the present invention.

【図１１】 本発明に係る半導体パッケージの第６の実
施例を示す部分断面図である。FIG. 11 is a partial sectional view showing a sixth embodiment of the semiconductor package according to the present invention.

【図１２】 本発明に係る半導体パッケージの第６の実
施例を示す斜視図である。FIG. 12 is a perspective view showing a sixth embodiment of the semiconductor package according to the present invention.

【図１３】 本発明に係る半導体パッケージの第６の実
施例を示す斜視図である。FIG. 13 is a perspective view showing a sixth embodiment of the semiconductor package according to the present invention.

【図１４】 本発明に係る半導体パッケージの第７の実
施例を示す部分断面図である。FIG. 14 is a partial sectional view showing a seventh embodiment of a semiconductor package according to the present invention.

【図１５】 本発明に係る半導体パッケージの第７の実
施例を示す斜視図である。FIG. 15 is a perspective view showing a seventh embodiment of the semiconductor package according to the present invention.

【図１６】 本発明に係る半導体パッケージの第８の実
施例を示す部分断面図である。FIG. 16 is a partial sectional view showing an eighth embodiment of the semiconductor package according to the present invention.

【図１７】 本発明に係る半導体パッケージの第８の実
施例を示す斜視図である。FIG. 17 is a perspective view showing an eighth embodiment of the semiconductor package according to the present invention.

【図１８】 本発明に係る半導体パッケージの第９の実
施例を示す部分断面図である。FIG. 18 is a partial sectional view showing a ninth embodiment of the semiconductor package according to the present invention.

【図１９】 本発明に係る半導体パッケージの第９の実
施例を示す斜視図である。FIG. 19 is a perspective view showing a ninth embodiment of the semiconductor package according to the present invention.

【図２０】 本発明に係る半導体パッケージの第１０の
実施例を示す部分断面図である。FIG. 20 is a partial sectional view showing a tenth embodiment of the semiconductor package according to the present invention.

【図２１】 従来の半導体パッケージを示す正面図であ
る。FIG. 21 is a front view showing a conventional semiconductor package.

【図２２】 従来の半導体パッケージを示す断面図であ
る。FIG. 22 is a sectional view showing a conventional semiconductor package.

【図２３】 従来の半導体パッケージを示す斜視図であ
る。FIG. 23 is a perspective view showing a conventional semiconductor package.

【符号の説明】[Explanation of symbols]

３Ａ〜３Ｊ 載置台、５Ａ〜５Ｊ パッケージ基板、１
５Ａ〜１５Ｊ 貫通孔、３１Ａ〜３１Ｊ 凸部、３２Ａ
〜３２Ｊ 基部、Ｐ，Ｐ１，Ｐ２ 突出部、Ｌ，Ｌ１，
Ｌ２，Ｌ３ 溝、３１１，３１５ 凸部外枠体、３１
２，３１６ 凸部内部体、３１３，３１７ 載置部、３
１４ 中間部、Ｇ１ 第１段差部、Ｇ２第２段差部。3A-3J mounting table, 5A-5J package substrate, 1
5A to 15J through hole, 31A to 31J convex portion, 32A
~ 32J Base, P, P1, P2 Projection, L, L1,
L2, L3 groove, 311, 315 convex outer frame, 31
2, 316 convex inner body, 313, 317 mounting portion, 3
14 Intermediate portion, G1 first step portion, G2 second step portion.

Claims (12)

【特許請求の範囲】[Claims] 【請求項１】 半導体集積回路を載置する載置台と、主
面に垂直な方向に貫通孔を有し、前記半導体集積回路を
前記載置台に載置した状態で一方の主面側から前記貫通
孔内に挿入することで前記半導体集積回路を収容するパ
ッケージ基板とを備え、前記パッケージ基板は前記載置
台よりも熱膨張係数の小さい材質で形成された半導体パ
ッケージであって、 前記載置台は、前記貫通孔内に挿入される凸部と、前記
凸部よりも広い基部とを有し、 前記凸部と前記貫通孔の内壁面との間には、前記凸部が
熱膨張により膨張した場合に、前記凸部が前記貫通孔の
内壁面に接触することを防ぐ隙間を有し、 前記載置台の前記基部のみが接着剤によって前記パッケ
ージ基板の一方の主面に固着されていることを特徴とす
る半導体パッケージ。1. A mounting table on which a semiconductor integrated circuit is mounted, and a through hole extending in a direction perpendicular to the main surface, wherein the semiconductor integrated circuit is mounted on the mounting table from one main surface side. A package substrate that accommodates the semiconductor integrated circuit by being inserted into the through hole, wherein the package substrate is a semiconductor package formed of a material having a thermal expansion coefficient smaller than that of the mounting table, and the mounting table is A protrusion that is inserted into the through hole and a base that is wider than the protrusion, and the protrusion is expanded by thermal expansion between the protrusion and the inner wall surface of the through hole. In this case, there is a gap that prevents the convex portion from coming into contact with the inner wall surface of the through hole, and only the base portion of the mounting table is fixed to one main surface of the package substrate with an adhesive. Characteristic semiconductor package. 【請求項２】 前記パッケージ基板の前記一方の主面
は、前記貫通孔を取り囲むように設けられた溝を有し、 前記載置台の前記基部は、前記溝に対応して前記凸部を
取り囲むように設けられ、前記貫通孔に前記凸部を挿入
することで、前記溝内に挿入される突出部を有し、 前記接着剤は、前記溝内および前記溝の両側に塗布され
ている請求項１記載の半導体パッケージ。2. The one main surface of the package substrate has a groove provided so as to surround the through hole, and the base portion of the mounting table surrounds the convex portion corresponding to the groove. And a protrusion that is inserted into the groove by inserting the convex portion into the through hole, wherein the adhesive is applied to the groove and both sides of the groove. The semiconductor package according to item 1. 【請求項３】 前記パッケージ基板の前記一方の主面
は、前記貫通孔を取り囲むように設けられた溝を有し、 前記溝内に粘性樹脂が塗布され、 前記載置台の前記基部は、前記溝に対応して前記凸部を
取り囲むように設けられ、前記貫通孔に前記凸部を挿入
することで、前記粘性樹脂に接触する突出部を有し、 前記接着剤は、前記溝の両側に塗布されている請求項１
記載の半導体パッケージ。3. The one main surface of the package substrate has a groove provided so as to surround the through hole, viscous resin is applied in the groove, and the base portion of the mounting table is It is provided so as to surround the convex portion corresponding to the groove, and by inserting the convex portion into the through hole, there is a protruding portion that comes into contact with the viscous resin, and the adhesive is provided on both sides of the groove. It is applied 1.
The semiconductor package described. 【請求項４】 前記パッケージ基板の前記一方の主面
は、前記貫通孔を取り囲むように設けられた第１の溝を
有し、 前記載置台の前記基部は、前記第１の溝に対応して前記
凸部を取り囲むように設けられた第２の溝を有し、 前記貫通孔に前記凸部を挿入することで、前記第１の溝
および前記第２の溝によって規制される空間内に、弾力
性を有し圧縮されることで気密を保つ気密リングが設け
られ、 前記接着剤は、前記第１の溝の両側に塗布されている請
求項１記載の半導体パッケージ。4. The one main surface of the package substrate has a first groove provided so as to surround the through hole, and the base portion of the mounting table corresponds to the first groove. A second groove provided so as to surround the convex portion, and by inserting the convex portion into the through hole, the space is regulated by the first groove and the second groove. The semiconductor package according to claim 1, further comprising an airtight ring that is elastic and compressed to keep airtightness, and the adhesive is applied to both sides of the first groove. 【請求項５】 前記載置台の前記基部は、前記凸部を取
り囲むように設けられた溝を有し、 前記パッケージ基板の前記一方の主面は、前記溝に対応
して前記貫通孔を取り囲むように設けられ、前記貫通孔
に前記凸部を挿入することで、前記溝内に挿入される突
出部を有し、 前記接着剤は、前記溝内および前記溝の両側に塗布され
ている請求項１記載の半導体パッケージ。5. The base of the mounting table has a groove provided so as to surround the convex portion, and the one main surface of the package substrate surrounds the through hole corresponding to the groove. And a protrusion that is inserted into the groove by inserting the convex portion into the through hole, wherein the adhesive is applied to the groove and both sides of the groove. The semiconductor package according to item 1. 【請求項６】 前記載置台の前記基部は、前記凸部を取
り囲むように設けられた溝を有し、 前記溝内に粘性樹脂が塗布され、 前記パッケージ基板の前記一方の主面は、前記溝に対応
して前記貫通孔を取り囲むように設けられ、前記貫通孔
に前記凸部を挿入することで、前記粘性樹脂に接触する
突出部を有し、 前記接着剤は、前記溝の両側に塗布されている請求項１
記載の半導体パッケージ。6. The base of the mounting table has a groove provided so as to surround the convex portion, a viscous resin is applied into the groove, and the one main surface of the package substrate is It is provided so as to surround the through hole corresponding to the groove, and has a protruding portion that comes into contact with the viscous resin by inserting the convex portion into the through hole, and the adhesive is provided on both sides of the groove. It is applied 1.
The semiconductor package described. 【請求項７】 前記載置台の前記凸部は、凸部外枠体お
よび凸部内部体を備え、 前記凸部外枠体は、無底かつ無蓋で前記凸部内部体が挿
入される箱型形状であって、その外形形状および外形寸
法は、前記凸部の外形形状および外形寸法を規定し、そ
の一方の端面側には端縁部に沿った鍔部を有し、 前記凸部内部体は前記基部と一体で形成され、その外形
形状および外形寸法は、前記凸部外枠体の内形形状およ
び内形寸法に応じて形成され、前記凸部内部体の周囲の
前記基部の表面は前記凸部外枠体の鍔部の外形形状およ
び外形寸法に合わせて座ぐりを施された座ぐり部を有
し、 前記凸部内部体を前記凸部外枠体に挿入することで、前
記座ぐり部に前記鍔部が係合して前記載置台の形をな
し、 前記凸部外枠体の材質は、その熱膨張係数が前記基部お
よび前記凸部内部体の熱膨張係数と、前記パッケージ基
板の熱膨張係数とのほぼ中間の値となるような材質であ
り、 前記接着剤は、前記鍔部に接触するように塗布されてい
る請求項１記載の半導体パッケージ。7. The box of the mounting table, wherein the convex portion includes a convex outer frame body and a convex inner body, and the convex outer frame body is a bottomless and lidless container into which the convex inner body is inserted. A mold shape, the outer shape and outer dimension of which define the outer shape and outer dimension of the convex portion, and one end face side of which has a collar portion along an edge portion, The body is formed integrally with the base portion, and the outer shape and the outer dimension thereof are formed according to the inner shape and inner dimension of the convex outer frame body, and the surface of the base portion around the convex inner body. Has a spot facing part that is provided with a spot facing according to the outer shape and the outer dimension of the flange portion of the convex outer frame body, and by inserting the convex inner body into the convex outer frame body, The flange portion is engaged with the spot facing portion to form the mounting table, and the material of the convex outer frame body has a coefficient of thermal expansion of Of the thermal expansion coefficient of the inner portion and the convex inner body, and the thermal expansion coefficient of the package substrate are approximately intermediate values, the adhesive is applied so as to contact the flange portion. The semiconductor package according to claim 1, wherein 【請求項８】 前記載置台の前記凸部および前記基部は
熱膨張係数の異なる材質で形成され、 前記凸部の材質は、その熱膨張係数が前記基部の熱膨張
係数と、前記パッケージ基板の熱膨張係数とのほぼ中間
の値となるような材質である請求項１記載の半導体パッ
ケージ。8. The convex portion and the base portion of the mounting table are formed of materials having different thermal expansion coefficients, and the material of the convex portion has a thermal expansion coefficient that is the same as that of the base portion and that of the package substrate. The semiconductor package according to claim 1, which is made of a material having a value substantially in the middle of the coefficient of thermal expansion. 【請求項９】 前記載置台の前記凸部は、前記半導体集
積回路を載置する載置部および、前記載置部と前記基部
との間に設けられた中間部を備え、 前記中間部の材質は、その熱膨張係数が前記基部の熱膨
張係数と、前記パッケージ基板の熱膨張係数とのほぼ中
間の値となるような材質であり、 前記載置部の材質は、その熱膨張係数が前記基部の熱膨
張係数と、前記半導体集積回路の基板の熱膨張係数との
ほぼ中間の値となるような材質である請求項１記載の半
導体パッケージ。9. The convex portion of the mounting table comprises a mounting portion on which the semiconductor integrated circuit is mounted, and an intermediate portion provided between the mounting portion and the base portion. The material is a material whose coefficient of thermal expansion has a value approximately in the middle of the coefficient of thermal expansion of the base portion and the coefficient of thermal expansion of the package substrate. 2. The semiconductor package according to claim 1, wherein the material has a material having an intermediate value between the coefficient of thermal expansion of the base and the coefficient of thermal expansion of the substrate of the semiconductor integrated circuit. 【請求項１０】 前記載置台の前記凸部は、凸部外枠体
および凸部内部体と前記半導体集積回路を載置する載置
部を備え、 前記凸部外枠体は、無底かつ無蓋で前記凸部内部体が挿
入される箱型形状であって、その外形形状および外形寸
法は、前記凸部の外形形状および外形寸法を規定し、 前記凸部内部体は前記基部と一体で形成され、その外形
形状および外形寸法は、前記凸部外枠体の内形形状およ
び内形寸法に応じて形成され、 前記凸部内部体を前記凸部外枠体に挿入し、前記凸部内
部体および前記凸部外枠体上に接するように前記載置部
を接合することで前記載置台の形をなし、 前記凸部外枠体の材質は、その熱膨張係数が前記基部お
よび前記凸部内部体の熱膨張係数と、前記パッケージ基
板の熱膨張係数とのほぼ中間の値となるような材質であ
り、 前記載置部の材質は、その熱膨張係数が前記基部および
前記凸部内部体の熱膨張係数と、前記半導体集積回路の
基板の熱膨張係数とのほぼ中間の値となるような材質で
ある請求項１記載の半導体パッケージ。10. The convex portion of the mounting table comprises a convex outer frame body, a convex inner body, and a mounting portion on which the semiconductor integrated circuit is mounted, and the convex outer frame body is bottomless and has a bottom surface. It is a box shape into which the convex inner body is inserted without a lid, and the outer shape and outer dimension thereof define the outer shape and outer dimension of the convex section, and the convex inner body is integrally formed with the base. The outer shape and outer dimension thereof are formed according to the inner shape and inner dimension of the convex outer frame body, and the convex inner body is inserted into the convex outer frame body to form the convex portion. The above-mentioned mounting table is formed by joining the above-mentioned mounting portion so as to contact the inner body and the above convex outer frame body, and the material of the above convex outer frame body has a coefficient of thermal expansion of the base portion and the above Make sure that the coefficient of thermal expansion of the inner part of the convex portion and the coefficient of thermal expansion of the package substrate are approximately halfway between The material of the mounting portion is such that the coefficient of thermal expansion thereof is approximately an intermediate value between the coefficient of thermal expansion of the base and the convex inner body and the coefficient of thermal expansion of the substrate of the semiconductor integrated circuit. The semiconductor package according to claim 1, which is made of a different material. 【請求項１１】 半導体集積回路を載置する載置台と、
主面に垂直な方向に貫通孔を有し、前記半導体集積回路
を前記載置台に載置した状態で一方の主面側から前記貫
通孔内に挿入することで前記半導体集積回路を収容する
パッケージ基板とを備え、前記パッケージ基板は前記載
置台よりも熱膨張係数の小さい材質で形成された半導体
パッケージであって、 前記載置台は、前記貫通孔内に挿入される凸部と、前記
凸部よりも広い基部とを有し、 前記載置台の前記凸部の縦断面形状は台形形状であり、 前記貫通孔の縦断面形状は前記凸部の縦断面形状に合わ
せたテーパを有する形状であり、 前記凸部と前記貫通孔の内壁面との間には、前記凸部が
熱膨張により膨張した場合に、前記凸部が前記貫通孔の
内壁面に接触するような隙間を有し、 前記載置台の前記基部のみが接着剤によって前記パッケ
ージ基板の一方の主面に固着されていることを特徴とす
る半導体パッケージ。11. A mounting table on which a semiconductor integrated circuit is mounted,
A package which has a through hole in a direction perpendicular to the main surface and which accommodates the semiconductor integrated circuit by inserting the semiconductor integrated circuit into the through hole from one main surface side in a state where the semiconductor integrated circuit is placed on the mounting table. And a package substrate, wherein the package substrate is a semiconductor package formed of a material having a smaller thermal expansion coefficient than the mounting table, wherein the mounting table includes a convex portion to be inserted into the through hole and the convex portion. And a wider base portion, and the vertical cross-sectional shape of the convex portion of the mounting table is a trapezoidal shape, and the vertical cross-sectional shape of the through hole is a shape having a taper adapted to the vertical cross-sectional shape of the convex portion. , Between the convex portion and the inner wall surface of the through hole, when the convex portion is expanded by thermal expansion, there is a gap such that the convex portion contacts the inner wall surface of the through hole, Only the base of the table is attached to the package by an adhesive. Semiconductor package, characterized in that it is fixed to one main surface of the di substrate. 【請求項１２】 前記パッケージ基板は、前記一方の主
面側の前記貫通孔の周囲に、前記基部を収容する段差部
を有し、 前記段差部の平面方向の長さは、前記基部が熱膨張によ
り膨張した場合に、前記基部の端縁部が前記段差部の内
壁面に接触しないような長さである請求項１〜請求項１
１のいずれかに記載の半導体パッケージ。12. The package substrate has a stepped portion that accommodates the base portion around the through hole on the one main surface side, and a planar length of the stepped portion is such that The length is such that the end edge portion of the base portion does not come into contact with the inner wall surface of the step portion when expanded by expansion.
1. The semiconductor package according to any one of 1.
JP7011555A 1995-01-27 1995-01-27 Semiconductor package Pending JPH08204045A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7011555A JPH08204045A (en) 1995-01-27 1995-01-27 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7011555A JPH08204045A (en) 1995-01-27 1995-01-27 Semiconductor package

Publications (1)

Publication Number Publication Date
JPH08204045A true JPH08204045A (en) 1996-08-09

Family

ID=11781201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7011555A Pending JPH08204045A (en) 1995-01-27 1995-01-27 Semiconductor package

Country Status (1)

Country Link
JP (1) JPH08204045A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009224635A (en) * 2008-03-18 2009-10-01 Nichia Corp Semiconductor device
JP4664675B2 (en) * 2002-09-02 2011-04-06 キネティック リミテッド Hermetically sealed

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4664675B2 (en) * 2002-09-02 2011-04-06 キネティック リミテッド Hermetically sealed
JP2009224635A (en) * 2008-03-18 2009-10-01 Nichia Corp Semiconductor device

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