JPH08203941A - Semiconductor device and manufacturing device for that - Google Patents
Semiconductor device and manufacturing device for thatInfo
- Publication number
- JPH08203941A JPH08203941A JP7026056A JP2605695A JPH08203941A JP H08203941 A JPH08203941 A JP H08203941A JP 7026056 A JP7026056 A JP 7026056A JP 2605695 A JP2605695 A JP 2605695A JP H08203941 A JPH08203941 A JP H08203941A
- Authority
- JP
- Japan
- Prior art keywords
- lead terminal
- semiconductor chip
- semiconductor device
- lead
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Moulds For Moulding Plastics Or The Like (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【目次】以下の順序で本発明を説明する。 産業上の利用分野 従来の技術（図５〜図７） 発明が解決しようとする課題（図８） 課題を解決するための手段（図１〜図４） 作用 実施例（図１〜図４） 発明の効果[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology (FIGS. 5 to 7) Problem to be Solved by the Invention (FIG. 8) Means for Solving the Problem (FIGS. 1 to 4) Action Example (FIGS. 1 to 4) The invention's effect
【０００２】[0002]
【産業上の利用分野】本発明は半導体装置及びその製造
装置に関し、特にＴＡＢ(tape automated bonding)方式
で組立られるＩＣパツケージ（ＴＣＰ）に適用して好適
なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing apparatus thereof, and is particularly suitable for application to an IC package (TCP) assembled by a TAB (tape automated bonding) method.
【０００３】[0003]
【従来の技術】従来、ＩＣ(integrated circuit)チツプ
をプリント配線基板に実装するためのパツケージとして
は、例えば、図５に示すようなＱＦＰ(quad flat packa
ge) １が用いられている。このＱＦＰ１は、ＩＣチツプ
２の電極が対応するリード端子３と金ワイヤ４等を用い
てワイヤボンデイング法により接続され、例えばエポキ
シ樹脂５によつて一体に封止されて形成される。2. Description of the Related Art Conventionally, as a package for mounting an IC (integrated circuit) chip on a printed wiring board, for example, a QFP (quad flat packa) as shown in FIG.
ge) 1 is used. The QFP 1 is formed such that the electrodes of the IC chip 2 are connected to the corresponding lead terminals 3 by the wire bonding method using the gold wires 4 and the like, and are integrally sealed with, for example, an epoxy resin 5.
【０００４】ところでＱＦＰ１の場合、例えば、ＩＣチ
ツプ２の電極が150 〔μｍ〕ピツチであると、各リード
端子は現状0.5 〔mm〕ピツチ、最小でも0.3 〔mm〕ピツ
チと２倍以上となり、200 ピン以上のＱＦＰでは外形寸
法が25〔mm2 〕以上になる。このように実装面積が大き
くなることは高密度実装の流れに反するだけでなく、パ
ツケージが大きくなることによつてプリント配線基板の
反り等の影響を受け易くなり、実装が難しくなる。In the case of the QFP1, for example, when the electrode of the IC chip 2 has a pitch of 150 [μm], each lead terminal is presently 0.5 [mm] pitch, and the minimum is 0.3 [mm] pitch. For QFPs with more than pins, the external dimensions are 25 [mm 2 ] or more. Such a large mounting area not only goes against the flow of high-density mounting, but also becomes larger due to the larger package, which makes it more susceptible to warping of the printed wiring board, which makes mounting difficult.
【０００５】そこで最近、図６（Ａ）及び（Ｂ）に示す
ように、ポリイミド等のフイルムテープ上に積層された
銅箔で形成したリードパターンを用いてパツケージを形
成するＴＣＰ(tape carrier package)６が注目され始め
ている。このＴＣＰ６はＡｕ又はＳｎの突起状電極を付
けたＩＣチツプ７にフイルムテープ８に形成されたリー
ド端子９を重ね合わせ、上からボンデイング装置で加圧
及び加熱してインナーリード端子９Ａをボンデイングし
ている。Therefore, recently, as shown in FIGS. 6A and 6B, a TCP (tape carrier package) for forming a package using a lead pattern formed of a copper foil laminated on a film tape of polyimide or the like. 6 is starting to get attention. In this TCP 6, the lead terminals 9 formed on the film tape 8 are superposed on the IC chip 7 having the Au- or Sn-shaped protruding electrodes, and the inner lead terminals 9A are bonded by pressing and heating from above with a bonding device. There is.
【０００６】図７にＴＣＰ６の成形の方法を示す。ＴＣ
Ｐ６の成形は、先ず、成形金型１０の上金型１０Ａと下
金型１０Ｂの間にＴＣＰ６を配し（図７（Ａ））、上金
型１０Ａと下金型１０ＢによつてＴＣＰ６をプレスして
リード端子９を成形する（図７（Ｂ））。次に余分なテ
ープ８をカツト刃１１を用いるか又は打ち抜き金型（図
示せず）によつて切り取る（図７（Ｃ））。ここで切り
取り（カツテイング）は外側のフイルム８を残す場合
と、残さない場合とがある。FIG. 7 shows a method of molding the TCP6. TC
In the molding of P6, first, TCP6 is arranged between the upper mold 10A and the lower mold 10B of the molding mold 10 (FIG. 7 (A)), and TCP6 is formed by the upper mold 10A and the lower mold 10B. The lead terminal 9 is molded by pressing (FIG. 7 (B)). Next, the excess tape 8 is cut out by using a cutting blade 11 or a punching die (not shown) (FIG. 7C). Here, the cutting (cutting) may or may not leave the outer film 8.
【０００７】このようにして成形されたＴＣＰ６は、図
８（Ａ）及び（Ｂ）に示すように、アウターリード９Ｂ
をプリント配線基板１２のランド１３に熱圧着法等を用
いて半田付けされる。ＴＣＰ６は通常0.2 〜0.3 〔mm〕
ピツチであり、もつと狭ピツチのものも開発されている
ので、パツケージの大きさを小さくすることができる。
またアウターリードボンデイングで熱圧着法を用いるこ
とによつてプリント配線基板の反りをの影響を受けるこ
となくチツプ実装できる。The TCP 6 molded in this manner has outer leads 9B as shown in FIGS. 8 (A) and 8 (B).
Is soldered to the land 13 of the printed wiring board 12 using a thermocompression bonding method or the like. TCP6 is usually 0.2-0.3 [mm]
The size of the package can be reduced because it is a pitch and a narrow pitch has been developed.
Further, by using the thermocompression bonding method in the outer lead bonding, the chip mounting can be performed without being affected by the warp of the printed wiring board.
【０００８】ＴＣＰ６のリード端子９は例えば、30〔μ
ｍ〕厚の銅箔をエツチングして形成しているので、鉄
(Ｆe)、ニツケル( Ｎｉ) 合金で形成しているＱＦＰの
リード端子に比べて軟らかく、半導体装置を熱サイクル
にかけた場合、チツプと部品との間に熱膨張係数差のた
めに生じる応力を緩和するのに有効である。The lead terminal 9 of the TCP 6 is, for example, 30 [μ
[m] Since it is formed by etching thick copper foil,
(Fe), softer than the lead terminal of QFP made of nickel (Ni) alloy, and relaxes the stress caused by the difference in the thermal expansion coefficient between the chip and the component when the semiconductor device is subjected to thermal cycling. It is effective to do.
【０００９】[0009]
【発明が解決しようとする課題】ところがＴＣＰのリー
ド端子は例えば、30〔μｍ〕厚と薄いため外力に弱くリ
ード端子の変形、曲折及び切断が生じ易いという問題が
あつた。さらに実装前のＴＣＰ６ではリード端子のスキ
ユー（横方向の傾き）やコプラナリテイ（上下方向の傾
き）が悪化し、実装する際にリード端子をランドに位置
決めすることが困難になるという問題があつた。また実
装後に他の工程等で何らかの物体が接触すると、リード
端子が変形したり、切断されるようなことがあるという
問題があつた。However, since the TCP lead terminal is thin, for example, 30 [μm], it has a problem that it is vulnerable to external force and is easily deformed, bent or cut. Further, in TCP6 before mounting, there is a problem that skew of the lead terminal (lateral inclination) and coplanarity (vertical inclination) are deteriorated, and it becomes difficult to position the lead terminal on the land during mounting. In addition, there is a problem that the lead terminal may be deformed or cut when some object comes into contact with it in another process after mounting.
【００１０】本発明は以上の点を考慮してなされたもの
で、半導体装置のリード端子の変形が生じない実装の容
易な半導体装置及びその製造装置を提案しようとするも
のである。The present invention has been made in consideration of the above points, and an object thereof is to propose a semiconductor device which can be easily mounted without deformation of the lead terminals of the semiconductor device and a manufacturing apparatus thereof.
【００１１】[0011]
【課題を解決するための手段】かかる課題を解決するた
め本発明においては、導体箔により形成される複数のリ
ード端子（９）がそれぞれ半導体チツプ（７）の対応す
る電極に接続されると共に、各リード端子（９）が半導
体チツプ（７）の外側周囲に配置されたフイルム（８）
上に一体に形成された半導体装置（６）において、半導
体チツプ（７）と各リード端子（９）の先端部を除く部
分とを一体に封止する封止部材（２３）とを備える。In order to solve the above problems, according to the present invention, a plurality of lead terminals (9) formed of a conductor foil are connected to corresponding electrodes of a semiconductor chip (7), respectively. A film (8) in which each lead terminal (9) is arranged around the outside of the semiconductor chip (7).
A semiconductor device (6) integrally formed on the upper surface of the semiconductor device includes a semiconductor chip (7) and a sealing member (23) for integrally sealing the lead terminals (9) excluding the tips.
【００１２】また本発明においては、導体箔により形成
される複数のリード端子（９）がそれぞれ半導体チツプ
（７）の対応する電極に接続されると共に、各リード端
子（９）が半導体チツプ（７）の外側周囲に配置された
フイルム（８）上に一体に形成された半導体装置の製造
装置（２１、２２、３０）において、半導体チツプ
（７）及びリード端子（９）を封止する封止空間（Ｃ
Ｂ）の上側部分を形成する上金型（２２Ａ）と、上金型
（２２Ａ）に対向して配置され、封止材料を注入する注
入口（２５）を有し、半導体チツプ（７）及びリード端
子（９）を載せ封止空間（ＣＢ）の底側部分を形成する
下金型（２２Ｂ）とを具え、プレス成形した後の各リー
ド端子（９）及び半導体チツプ（７）を上金型（２２
Ａ）と下金型（２２Ｂ）の間に形成する封止空間（Ｃ
Ｂ）内に配置して注入口（２５）から封止空間に封止材
料を注入し、半導体チツプ（７）及びリード端子（９）
の所定部位を封止する所定部位を封止する。Further, in the present invention, the plurality of lead terminals (9) formed of the conductor foil are connected to the corresponding electrodes of the semiconductor chip (7), and each lead terminal (9) is connected to the semiconductor chip (7). In a semiconductor device manufacturing apparatus (21, 22, 30) integrally formed on a film (8) arranged around the outer periphery of (4), the semiconductor chip (7) and the lead terminal (9) are sealed. Space (C
B) has an upper mold (22A) forming an upper part thereof, and an injection port (25) arranged to face the upper mold (22A) and injecting a sealing material, and the semiconductor chip (7) and A lower die (22B) on which the lead terminal (9) is placed and which forms the bottom side portion of the sealed space (CB), and each lead terminal (9) and the semiconductor chip (7) after press molding are placed on the upper die. Mold (22
Sealing space (C) formed between A) and the lower mold (22B)
The semiconductor chip (7) and the lead terminal (9) are placed in B) and the sealing material is injected into the sealing space from the injection port (25).
The predetermined part is sealed.
【００１３】また本発明においては、導体箔により形成
される複数のリード端子（９）がそれぞれ半導体チツプ
（７）の対応する電極に接続されると共に、各リード端
子（９）が半導体チツプ（７）の外側周囲に配置された
フイルム（８）上に一体に形成された半導体装置の製造
装置（２１、２２、３０）において、半導体チツプ
（７）及びリード端子（９）の形状に応じた所定形状を
有する上金型（３０Ａ）と、上金型（３０Ａ）に対向し
て配置され、各リード端子（９）を一体に上金型（３０
Ａ）との間に挟んで保持する保持手段（３０Ｃ）と、保
持手段の内側に上金型に対向して配置され、封止材料を
注入する注入口を有し、上金型（３０Ａ）と一体になり
所定形状の金型を形成し、かつ上金型から離脱する方向
に移動して半導体チツプ及び各リード端子（９）を封止
する封止空間（ＣＢ）を形成する移動成形金型（３０
Ｂ）とを具え、各リード端子（９）に対して両面方向か
ら上金型（３０Ａ）と移動成形金型（３０Ｂ）とを当接
させ、所定形状に上金型（３０Ａ）プレス成形した後、
移動成形金型（３０Ｂ）が上金型（３０Ａ）に対して離
脱する方向に移動して上金型（３０Ａ）との間に半導体
チツプ（７）及び各リード端子（９）の封止空間（Ｃ
Ｂ）を形成し、注入口（３１）より封止材料を注入して
半導体チツプ（７）及びリード端子（９）の所定部位を
封止する。Further, in the present invention, the plurality of lead terminals (9) formed of the conductor foil are connected to the corresponding electrodes of the semiconductor chip (7), and each lead terminal (9) is connected to the semiconductor chip (7). In a semiconductor device manufacturing apparatus (21, 22, 30) integrally formed on a film (8) arranged around the outer periphery of (4), a predetermined shape corresponding to the shapes of the semiconductor chip (7) and the lead terminal (9). The upper die (30A) having a shape is disposed so as to face the upper die (30A), and each lead terminal (9) is integrated with the upper die (30A).
The upper mold (30A) has a holding means (30C) which is sandwiched between the upper mold (A) and a holding means (30C) and an injection port which is arranged inside the holding means so as to face the upper mold and injects the sealing material. And a movable molding die that forms a mold having a predetermined shape and moves in a direction to separate from the upper mold to form a sealing space (CB) that seals the semiconductor chip and each lead terminal (9). Mold (30
B), the upper mold (30A) and the moving molding mold (30B) are brought into contact with each lead terminal (9) from both sides to press-mold the upper mold (30A) into a predetermined shape. rear,
The movable molding die (30B) moves in a direction to separate from the upper die (30A), and the semiconductor chip (7) and each lead terminal (9) are sealed between the movable molding die (30B) and the upper die (30A). (C
B) is formed, and a sealing material is injected through the injection port (31) to seal the semiconductor chip (7) and the predetermined portions of the lead terminals (9).
【００１４】[0014]
【作用】半導体チツプ（７）の対応する電極に接続され
るリード端子（９）が半導体チツプ（９）の外側周囲に
配置されたフイルム（８）上に一体に形成された半導体
装置（６）を半導体チツプと各リード端子（９）の先端
を除く部分とを一体に封止部材（２３）によつて封止す
ることにより、リード端子（９）の変形を少なくし得
る。A semiconductor device (6) in which lead terminals (9) connected to corresponding electrodes of the semiconductor chip (7) are integrally formed on a film (8) arranged around the outside of the semiconductor chip (9). By integrally sealing the semiconductor chip and the portion excluding the tip of each lead terminal (9) with the sealing member (23), the deformation of the lead terminal (9) can be reduced.
【００１５】[0015]
【実施例】以下図面について、本発明の一実施例を詳述
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.
【００１６】図１（Ａ）及び（Ｂ）において、２０は本
発明による半導体装置を示し、半導体装置２０は導体箔
のリード端子９がポリイミドのフイルムテープに積層さ
れたＴＣＰ６を樹脂封止することによつて形成されてい
る。In FIGS. 1A and 1B, reference numeral 20 denotes a semiconductor device according to the present invention. In the semiconductor device 20, a lead terminal 9 of a conductor foil is resin-sealed with a TCP 6 laminated on a polyimide film tape. It is formed by.
【００１７】図２（Ａ）及び（Ｂ）に半導体装置２０の
成形と封止の方法を示す。半導体装置２０は先ず、図２
（Ａ）に示す成形金型２１によつてリード端子９の形状
が成形され、次いで図２（Ｂ）に示す成形金型２２によ
つてＴＣＰ６の外形に合わせてリード端子９がカツテイ
ング成形された後、エポキシ樹脂２３によつて封止成形
される。2A and 2B show a method of molding and sealing the semiconductor device 20. The semiconductor device 20 is first shown in FIG.
The shape of the lead terminal 9 is molded by the molding die 21 shown in (A), and then the lead terminal 9 is cut and molded according to the outer shape of the TCP 6 by the molding die 22 shown in FIG. 2 (B). Then, the epoxy resin 23 is used for sealing molding.
【００１８】成形金型２１は、上金型２１Ａと下金型２
１ＢはそれぞれＴＣＰチツプの凹凸に沿つた形状の接触
部を有する所定の押型を有し、上金型２１Ａと下金型２
１Ｂとの間に配したＴＣＰ６のリード端子９を上下方向
からプレス成形することによりＴＣＰ６のリード端子９
の形状をチツプ実装できるように成形する。The molding die 21 includes an upper die 21A and a lower die 2.
1B has a predetermined die having contact portions each having a shape along the unevenness of the TCP chip, and has an upper die 21A and a lower die 2
The lead terminal 9 of the TCP6 provided between the lead terminal 9 of the TCP6 and the lead terminal 9 of the TCP6 is press-formed from above and below.
Mold the shape of so that it can be mounted in a chip.
【００１９】リード端子９の成形が完了すると、ＴＣＰ
６は成形金型２２によつて封止成形される。成形金型２
２の上金型２２Ａは、外枠周囲の下端にＴＣＰの外形に
合わされた形状のカツト刃２４を保持し、金型の内側に
ＴＣＰ６の半導体チツプ７及びリード端子９の所定部分
を封止する空間（キヤビテイ）ＣＢを形成する。下金型
２２ＢはＴＣＰ６を上に搭載する平らな台状の金型で、
ＴＣＰ６の搭載面には中央部に樹脂注入の注入孔２５が
設けられている。下金型２２ＢはＴＣＰ６のリード端子
９の端部を上金型２２Ａと上下方向から密着させて挟み
込みむことによつて、電気的に接続されるリード端子の
端部の半田付け部分に樹脂がはみ出さないようにする。When the molding of the lead terminal 9 is completed, the TCP
6 is sealed and molded by the molding die 22. Mold 2
The upper die 22A of 2 holds a cutting blade 24 having a shape adapted to the outer shape of the TCP at the lower end around the outer frame, and seals predetermined portions of the semiconductor chip 7 and the lead terminals 9 of the TCP 6 inside the die. A space (cavity) CB is formed. The lower die 22B is a flat trapezoidal die with TCP6 mounted on it.
An injection hole 25 for resin injection is provided at the center of the mounting surface of the TCP 6. Since the lower die 22B sandwiches the end portion of the lead terminal 9 of the TCP 6 from the upper die 22A by closely adhering the end portion to the upper die 22A, the resin is attached to the soldered portion of the end portion of the lead terminal electrically connected. Do not let it stick out.
【００２０】以上の構成において、成形金型２１の下金
型２１Ｂ上にＴＣＰ６を位置合わせして、ＴＣＰ６のリ
ード端子９の曲げ位置を制御した後、上金型２１Ａと下
金型２１Ｂとの間に配したＴＣＰ６をプレスしてリード
端子９を成形する。続いてリード端子９を成形金型２２
に配して、リード端子９の形状が成形された後のＴＣＰ
６を上金型２２Ａによつて上金型２２Ａの下端周囲に取
付けられたカツト刃２４によつて打ち抜く。このとき下
金型２２Ｂの台は平面であり、上金型２２Ａがリード端
子９の曲げ部分に当たらなければ問題がないので精密な
位置合わせを必要としなくて済む。In the above structure, the TCP 6 is aligned with the lower mold 21B of the molding mold 21 to control the bending position of the lead terminal 9 of the TCP 6, and then the upper mold 21A and the lower mold 21B are separated. The TCP 6 placed in between is pressed to form the lead terminal 9. Then, the lead terminal 9 is formed on the molding die 22.
And the TCP after the lead terminal 9 has been shaped
6 is punched out by a cutting blade 24 attached around the lower end of the upper die 22A by the upper die 22A. At this time, the base of the lower mold 22B is flat, and there is no problem if the upper mold 22A does not hit the bent portion of the lead terminal 9, so that precise positioning is not necessary.
【００２１】ＴＣＰ６が成形金型２２に打ち抜かれる
と、引き続き封止成形が行われる。すなわち、トランス
フアモールド法により粉末又はタブレツト状に予備成形
された熱硬化性エポキシ樹脂２３を下金型２２Ｂの中程
に開けられた樹脂注入孔２５より低圧で封止空間内に注
入し、溶融流動させて封止成形する。この際、リード端
子９の厚みが30〔μｍ〕程度あるので図３に示すよう
に、アウターリード９Ｂのリード端子間の基部にエポキ
シ樹脂が滲み出す（図中Ａで示す）。この滲みでたエポ
キシ樹脂によつてアウターリード９Ｂは固定され、これ
により外部に露出したアウターリード９Ｂの変形を防ぐ
ことができる。さらにリード端子９のバタツキが小さく
なり、半導体装置の実装時にチツプに対してリード端子
９が浮き上がることが未然に防止され、半田付け不良等
がなくなる。因みに金型の抜け性に影響する抜勾配や面
粗度等の金型の特徴はＱＦＰモールドの場合に準じてい
る。When the TCP 6 is stamped into the molding die 22, the sealing molding is continued. That is, a thermosetting epoxy resin 23 preliminarily molded into powder or tablet by transfer molding method is injected into the sealed space at a low pressure through a resin injection hole 25 opened in the middle of the lower mold 22B and melted. Flow and seal and mold. At this time, since the thickness of the lead terminal 9 is about 30 [μm], the epoxy resin oozes out to the base portion between the lead terminals of the outer lead 9B (shown by A in the figure), as shown in FIG. The outer lead 9B is fixed by the bleeding epoxy resin, whereby the outer lead 9B exposed to the outside can be prevented from being deformed. Further, the fluttering of the lead terminals 9 is reduced, and the lead terminals 9 are prevented from floating up with respect to the chip when the semiconductor device is mounted, and soldering defects and the like are eliminated. By the way, the characteristics of the mold such as draft and surface roughness that influence the mold releasability are the same as those of the QFP mold.
【００２２】以上の構成によれば、ＴＣＰ６の封止成形
の際、各リード端子９間に滲むエポキシ樹脂により半田
付け部以外のＴＣＰ６のリード端子９を固めることによ
つて、半導体装置の実装時のＴＣＰ６のリード端子９の
バタツキを抑制し得る。またリード端子９成形の直後に
リード端子９を固定するのでリード端子９の形状をくず
すおそれが少ない。さらに、半導体装置の実装後におい
ても、他の工程での不要な接触等によるリード端子９の
変形を防止し得る。さらに樹脂によるリード端子９の固
定は、専用の装置を新たに設けることなくリード端子９
を打ち抜いた後、成形金型２２によつて樹脂封止と同時
に実行するので新たに工程を増やす必要がなくコスト面
でも有利になる。According to the above configuration, when the TCP 6 is sealed and molded, the lead terminals 9 of the TCP 6 other than the soldered portions are fixed by the epoxy resin that bleeds between the lead terminals 9, so that the semiconductor device is mounted. Flapping of the lead terminal 9 of the TCP 6 can be suppressed. Further, since the lead terminal 9 is fixed immediately after the molding of the lead terminal 9, there is less possibility of breaking the shape of the lead terminal 9. Further, even after the semiconductor device is mounted, the lead terminal 9 can be prevented from being deformed due to unnecessary contact in other steps. Further, the fixing of the lead terminal 9 with resin does not require a new dedicated device.
After punching, the molding die 22 is performed at the same time as the resin sealing, so that it is not necessary to add a new process, which is advantageous in terms of cost.
【００２３】なお上述の実施例においては、リード端子
ａ成形金型と封止成形金型が独立した別のものの場合に
ついて述べたが、本発明はこれに限らず、図４に示すよ
うな成形金型３０を用いれば、１つの金型だけでリード
端子９の成形及び封止成形を実行することができる。す
なわち、成形金型３０は上部に固定された成形金型の受
け型３０Ａと、その下に対向して配置される２段の受け
金型３０Ｂ及び３０Ｃによつて構成される。樹脂封止す
るＴＣＰ６の半導体チツプ７とテープ８の凹凸形状に応
じた所定の押型を有する受け金型３０Ｂは、受け型３０
Ａとの間でアウターリード９Ｂをプレス成形した後、下
方向に移動して半導体チツプ７及びリード端子９のキヤ
ビテイＣＢを形成する。このときアウターリード９Ｂの
端部は上側の受け型３０Ａと下側の受け型３０Ｃとの間
にはさまれて保持され続ける。In the above-described embodiment, the case where the lead terminal a molding die and the sealing molding die are independent is described, but the present invention is not limited to this, and the molding as shown in FIG. If the mold 30 is used, the lead terminal 9 can be molded and sealed with only one mold. That is, the molding die 30 is composed of a molding die receiving die 30A fixed to the upper part, and two stages of receiving dies 30B and 30C which are arranged below and facing each other. The receiving die 30B having a predetermined die corresponding to the uneven shape of the semiconductor chip 7 of the TCP 6 and the tape 8 to be resin-sealed is the receiving die 30.
After the outer lead 9B is press-molded with A, it moves downward to form the cavity CB of the semiconductor chip 7 and the lead terminal 9. At this time, the ends of the outer leads 9B are sandwiched and held between the upper receiving mold 30A and the lower receiving mold 30C.
【００２４】成形金型３０によつてＴＣＰ６のリード端
子９が成形されると、受け型３０Ｂが所定の高さまで降
下し、この結果、受け型３０Ａと受け型３０Ｂの間にキ
ヤビイテイＣＢができる。このようにして形成されたキ
ヤビイテイＣＢに注入口３１からエポキシ樹脂を注入し
てＴＣＰ６のチツプを封止成形する。この際、上述した
実施例と同様にＴＣＰ６のアウターリード端子９には各
リード端子同士の間の隙間にエポキシ樹脂が滲み出し、
これによつてアウターリード端子９Ｂが固定される。こ
のようにしてエポキシ樹脂２３によつて封止成形された
半導体チツプ７及びリード端子９はリード端子９とテー
プ８の不要な部分がカツト刃１１によつてカツテイング
され、半導体装置２０に成形される。このときアウター
リード端子９Ｂの端部の半田付け部分は受け型３０Ａと
３０Ｃによつて密着して挟まれているのでエポキシ樹脂
が付かない。これにより上述の実施例と同様の効果が得
られる。When the lead terminal 9 of the TCP 6 is molded by the molding die 30, the receiving die 30B is lowered to a predetermined height, and as a result, a cavity CB is formed between the receiving die 30A and the receiving die 30B. An epoxy resin is injected from the injection port 31 into the cavity CB thus formed, and the chip of the TCP 6 is sealed and molded. At this time, as in the above-described embodiment, the epoxy resin oozes into the outer lead terminals 9 of the TCP 6 in the gap between the lead terminals,
As a result, the outer lead terminal 9B is fixed. In the semiconductor chip 7 and the lead terminal 9 thus sealed and molded with the epoxy resin 23, unnecessary portions of the lead terminal 9 and the tape 8 are cut by the cutting blade 11 and molded into the semiconductor device 20. . At this time, the soldering portion at the end portion of the outer lead terminal 9B is sandwiched by the receiving molds 30A and 30C so as to be in close contact with each other, so that no epoxy resin is attached. As a result, the same effect as that of the above-described embodiment can be obtained.
【００２５】さらに上述の実施例においては、ＴＣＰの
封止成形法としてトランスフアモールド法を用いた場合
について述べたが、本発明はこれに限らず、射出成形法
を用いても良い。さらに上述の実施例においては、成形
金型２１でリード端子９を成形し、成形金型２２で封止
成形した場合について述べたが、本発明はこれに限ら
ず、成形金型２２の代わりに成形金型２１を用いて封止
成形してカツト刃を用いてリード端子９を成形するよう
にしても良い。これによりリード端子の成形と封止成形
が同一の金型でできる。Further, in the above embodiment, the case where the transfer molding method is used as the TCP sealing molding method has been described, but the present invention is not limited to this, and an injection molding method may be used. Furthermore, in the above-described embodiment, the case where the lead terminal 9 is molded by the molding die 21 and the molding is performed by the molding die 22 has been described, but the present invention is not limited to this, and the molding die 22 may be used instead. The lead terminal 9 may be molded by using a molding die 21 for sealing molding and a cutting blade. Thereby, the molding of the lead terminal and the sealing molding can be performed by the same mold.
【００２６】[0026]
【発明の効果】上述のように本発明によれば、半導体チ
ツプの対応する電極に接続されるリード端子が半導体チ
ツプの外側周囲に配置されたフイルム上に一体に形成さ
れた半導体装置を半導体チツプと各リード端子の先端を
除く部分とを一体に封止部材によつて封止することによ
り、配線基板への実装が容易な半導体装置及びその製造
装置を実現し得る。As described above, according to the present invention, a semiconductor device in which lead terminals connected to corresponding electrodes of the semiconductor chip are integrally formed on a film arranged around the outside of the semiconductor chip is provided. The semiconductor device and its manufacturing apparatus that can be easily mounted on the wiring board can be realized by integrally sealing the portion of each lead terminal excluding the tip end with the sealing member.
【図１】本発明による半導体装置の斜視図（図１
（Ａ））及び断面図（図１（Ｂ））である。FIG. 1 is a perspective view of a semiconductor device according to the present invention (see FIG.
(A)) and sectional drawing (FIG. 1 (B)).
【図２】本発明による半導体装置の製造装置の説明に供
する断面図である。FIG. 2 is a cross-sectional view provided for explaining a semiconductor device manufacturing apparatus according to the present invention.
【図３】半導体装置のアウターリード部に滲んだ封止材
料を示す斜視図である。FIG. 3 is a perspective view showing a sealing material that has permeated an outer lead portion of a semiconductor device.
【図４】他の実施例の半導体装置の製造装置の説明に供
する断面図である。FIG. 4 is a cross-sectional view for explaining a semiconductor device manufacturing apparatus according to another embodiment.
【図５】ＱＦＰパツケージの構造を示す断面図である。FIG. 5 is a sectional view showing the structure of a QFP package.
【図６】ＴＣＰの断面図（図６（Ａ））及び斜視図（図
６（Ｂ））である。6A and 6B are a cross-sectional view (FIG. 6A) and a perspective view (FIG. 6B) of a TCP.
【図７】従来の半導体装置の製造装置に供する断面図で
ある。FIG. 7 is a cross-sectional view of a conventional semiconductor device manufacturing apparatus.
【図８】プリント配線基板に実装されるＴＣＰの示す斜
視図（図８（Ａ））及び断面図（図８（Ｂ））である。FIG. 8 is a perspective view (FIG. 8A) and a sectional view (FIG. 8B) showing a TCP mounted on a printed wiring board.
１……ＱＦＰ、２、７……ＩＣチツプ、３、４、９……
リード端子、５、２３……エポキシ樹脂、６……ＴＣ
Ｐ、８……テープ、１０……封止金型、１１……カツト
刃、１２……プリント配線基板、１３……ランド、２０
……半導体装置、２１、２２、３０……成形金型、注入
口……２５、３１。1 ... QFP, 2, 7 ... IC chip, 3, 4, 9 ...
Lead terminal, 5,23 ... Epoxy resin, 6 ... TC
P, 8 ... Tape, 10 ... Sealing mold, 11 ... Cutting blade, 12 ... Printed wiring board, 13 ... Land, 20
…… Semiconductor device, 21, 22, 30 …… Molding die, injection port …… 25,31.
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成７年５月２３日[Submission date] May 23, 1995
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００７[Correction target item name] 0007
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００７】このようにして成形されたＴＣＰ６は、図
８（Ａ）及び（Ｂ）に示すように、アウターリード９Ｂ
をプリント配線基板１２のランド１３に熱圧着法等を用
いて半田付けされる。ＴＣＰ６は通常０．２〜０．３
〔ｍｍ〕ピツチであり、もつと狭ピツチのものも開発さ
れているので、パツケージの大きさを小さくすることが
できる。またアウターリードボンデイングで熱圧着法を
用いることによつてプリント配線基板の反りの影響を受
けることなくチツプ実装できる。The TCP 6 molded in this manner has outer leads 9B as shown in FIGS. 8 (A) and 8 (B).
Is soldered to the land 13 of the printed wiring board 12 using a thermocompression bonding method or the like. TCP6 is usually 0.2-0.3
Since a [mm] pitch and a narrow pitch are also developed, the size of the package can be reduced. Moreover, by using the thermocompression bonding method in the outer lead bonding, chip mounting can be performed without being affected by the warp of the printed wiring board.
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００９[Correction target item name] 0009
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００９】[0009]
【発明が解決しようとする課題】ところがＴＣＰのリー
ド端子は例えば、３０〔μｍ〕厚と薄いため外力に弱く
リード端子の変形、曲折及び切断が生じ易いという問題
があつた。さらに実装前のＴＣＰ６ではリード端子のス
キユー（横方向のバタツキ）やコプラナリテイ（上下方
向のバタツキ）が悪化し、実装する際にリード端子をラ
ンドに位置決めすることが困難になるという問題があつ
た。また実装後に他の工程等で何らかの物体が接触する
と、リード端子が変形したり、切断されるようなことが
あるという問題があつた。However, since the TCP lead terminal is thin, for example, 30 [μm] thick, it has a problem that it is vulnerable to external force and is susceptible to deformation, bending and cutting. Further, in the TCP6 before mounting, there is a problem that the skew of the lead terminal (fluttering in the lateral direction) and the coplanarity (fluttering in the vertical direction) are deteriorated, and it becomes difficult to position the lead terminal on the land during mounting. In addition, there is a problem that the lead terminal may be deformed or cut when some object comes into contact with it in another process after mounting.
Claims (7)
がそれぞれ半導体チツプの対応する電極に接続されると
共に、各上記リード端子が上記半導体チツプの外側周囲
に配置されたフイルム上に一体に形成された半導体装置
において、 上記半導体チツプと各上記リード端子の先端部を除く部
分とを一体に封止する封止部材を具えることを特徴とす
る半導体装置。1. A plurality of lead terminals formed of a conductor foil are respectively connected to corresponding electrodes of a semiconductor chip, and each of the lead terminals is integrally formed on a film arranged on the outer periphery of the semiconductor chip. The semiconductor device according to claim 1, further comprising a sealing member that integrally seals the semiconductor chip and a portion of each lead terminal excluding the tip portion.
リード端子間を固定するリード端子間固定部材を有する
ことを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the sealing member has a lead terminal fixing member that fixes the lead terminals without electrical connection.
がそれぞれ半導体チツプの対応する電極に接続されると
共に、各上記リード端子が上記半導体チツプの外側周囲
に配置されたフイルム上に一体に形成された半導体装置
の製造装置において、 半導体チツプ及びリード端子を封止する封止空間の上側
部分を形成する上金型と、 上記上金型に対向して配置され、封止材料を注入する注
入口を有し、上記半導体チツプ及び上記リード端子を載
せ封止空間の底側部分を形成する下金型とを具え、プレ
ス成形した後の各上記リード端子及び上記半導体チツプ
を上記上金型と上記下金型の間に形成する上記封止空間
内に配置して上記注入口から上記封止空間に上記封止材
料を注入し、上記半導体チツプ及び上記リード端子の所
定部位を封止することを特徴とする半導体装置の製造装
置。3. A plurality of lead terminals formed of a conductor foil are respectively connected to corresponding electrodes of a semiconductor chip, and each of the lead terminals is integrally formed on a film arranged around the outside of the semiconductor chip. In the manufacturing apparatus of the semiconductor device, the upper die forming the upper part of the encapsulation space for encapsulating the semiconductor chip and the lead terminal, and the upper die are arranged so as to face the upper die, and the encapsulation material is injected. A lower mold having an inlet and forming the bottom portion of the sealed space on which the semiconductor chip and the lead terminal are mounted, and the lead terminal and the semiconductor chip after press molding are combined with the upper mold. Arranging in the sealing space formed between the lower molds, injecting the sealing material from the injection port into the sealing space, and sealing the semiconductor chip and predetermined portions of the lead terminals. Apparatus for manufacturing a semiconductor device according to claim.
端子の電気的接続のない部分であることを特徴とする請
求項３に記載の半導体装置の製造装置。4. The semiconductor device manufacturing apparatus according to claim 3, wherein the predetermined portion of the lead terminal is a portion where the lead terminal is not electrically connected.
成形することを特徴とする請求項４に記載の半導体装置
の製造装置。5. The semiconductor device manufacturing apparatus according to claim 4, wherein the lead terminal is press-molded by the upper mold.
がそれぞれ半導体チツプの対応する電極に接続されると
共に、各上記リード端子が上記半導体チツプの外側周囲
に配置されたフイルム上に一体に形成された半導体装置
の製造装置において、 半導体チツプ及びリード端子の形状に応じた所定形状を
有する上金型と、 上記上金型に対向して配置され、各上記リード端子を一
体に上記上金型との間に挟んで保持する保持手段と、 上記保持手段の内側に上記上金型に対向して配置され、
封止材料を注入する注入口を有し、上記上金型と一体に
なり所定形状の金型を形成し、かつ上記上金型から離脱
する方向に移動して上記半導体チツプ及び各上記リード
端子を封止する封止空間を形成する移動成形金型とを具
え、各上記リード端子に対して両面方向から上記上金型
と上記移動成形金型とを当接させ、所定形状に上記上金
型プレス成形した後、上記移動成形金型が上記上金型に
対して離脱する方向に移動して上記上金型との間に上記
半導体チツプ及び各上記リード端子の封止空間を形成
し、上記注入口より上記封止材料を注入して上記半導体
チツプ及び上記リード端子の所定部位を封止することを
特徴とする半導体装置の製造装置。6. A plurality of lead terminals formed of a conductor foil are respectively connected to corresponding electrodes of a semiconductor chip, and each of the lead terminals is integrally formed on a film arranged around the outside of the semiconductor chip. In an apparatus for manufacturing a semiconductor device, an upper die having a predetermined shape corresponding to the shape of a semiconductor chip and a lead terminal is arranged to face the upper die, and each of the lead terminals is integrated with the upper die. Holding means sandwiched between and, and arranged inside the holding means to face the upper mold,
The semiconductor chip and each of the lead terminals have an injection port for injecting a sealing material, are integrated with the upper mold to form a mold having a predetermined shape, and move in a direction of separating from the upper mold. And a movable molding die for forming a sealed space for sealing the upper mold and the movable mold in contact with each of the lead terminals from both sides, thereby forming the upper mold into a predetermined shape. After die press molding, the movable molding die moves in a direction to separate from the upper die to form a sealing space for the semiconductor chip and each lead terminal between the movable die and the upper die, An apparatus for manufacturing a semiconductor device, characterized in that the encapsulating material is injected through the injection port to seal the semiconductor chip and predetermined portions of the lead terminal.
端子の電気的な接続のない部分であることを特徴とする
請求項６に記載の半導体装置の製造装置。7. The semiconductor device manufacturing apparatus according to claim 6, wherein the predetermined portion of the lead terminal is a portion where the lead terminal is not electrically connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7026056A JPH08203941A (en) | 1995-01-20 | 1995-01-20 | Semiconductor device and manufacturing device for that |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7026056A JPH08203941A (en) | 1995-01-20 | 1995-01-20 | Semiconductor device and manufacturing device for that |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08203941A true JPH08203941A (en) | 1996-08-09 |
Family
ID=12183032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7026056A Pending JPH08203941A (en) | 1995-01-20 | 1995-01-20 | Semiconductor device and manufacturing device for that |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08203941A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003510835A (en) * | 1999-08-19 | 2003-03-18 | マイクロン・テクノロジー・インコーポレーテッド | Apparatus and method for providing a mechanically preformed conductive lead |
-
1995
- 1995-01-20 JP JP7026056A patent/JPH08203941A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003510835A (en) * | 1999-08-19 | 2003-03-18 | マイクロン・テクノロジー・インコーポレーテッド | Apparatus and method for providing a mechanically preformed conductive lead |
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