JPH08195468A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH08195468A JPH08195468A JP491695A JP491695A JPH08195468A JP H08195468 A JPH08195468 A JP H08195468A JP 491695 A JP491695 A JP 491695A JP 491695 A JP491695 A JP 491695A JP H08195468 A JPH08195468 A JP H08195468A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- lead frame
- groove
- semiconductor chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に用いるリ
ードフレームに係り、特に、ＬＯＣパッケージに用いて
最適なリードフレームに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame used for a semiconductor device, and more particularly to a lead frame optimal for use in a LOC package.
【０００２】[0002]
【従来の技術】図４はＬＯＣ（Ｌｅａｄ Ｏｎ Ｃｈｉ
ｐ）パッケージによる半導体装置の一例を示す断面図で
ある。四角型の半導体チップ１の電極形成面には、その
所定位置にリードフレーム３の先端部３ａが接着剤２を
介して貼着されている。接着剤２は、従来から用いられ
てきた絶縁テープに代わるもので、絶縁性及び熱可塑性
を備えた素材を溶媒に溶かした状態で用いられ、これを
図５に示すように、リードフレーム３の先端部３ａの全
面に塗布し、その後乾燥させ、ついで溶媒を除去する。
この状態で上記したようにリードフレーム３の先端部３
ａと半導体チップ１を位置決めしたまま加熱及び圧着す
れば、接着剤２が流動化し、両者の接着が行われる。2. Description of the Related Art FIG. 4 shows a LOC (Lead On Chi).
p) is a sectional view showing an example of a semiconductor device by a package. The tip portion 3a of the lead frame 3 is attached to a predetermined position on the electrode forming surface of the rectangular semiconductor chip 1 with an adhesive 2 interposed therebetween. The adhesive 2 is an alternative to the conventionally used insulating tape, and is used in a state in which a material having insulating and thermoplastic properties is dissolved in a solvent. As shown in FIG. The entire surface of the tip portion 3a is coated, then dried, and then the solvent is removed.
In this state, as described above, the tip portion 3 of the lead frame 3
If a and the semiconductor chip 1 are positioned and heated and pressure-bonded, the adhesive 2 is fluidized and the two are bonded.
【０００３】この後、半導体チップ１上の電極面と、こ
れに対応するリードフレーム３の先端部３ａとがボンデ
ィングワイヤ４によって接続される。更に、半導体チッ
プ１及びボンディングワイヤ４を封止するようにモール
ドレジン５が施され、各部材の固定及び耐湿性の向上が
図られている。この後、リードフレーム３の露出部分の
先端に曲げ加工が施される。これによって半導体装置が
完成する。Thereafter, the electrode surface on the semiconductor chip 1 and the corresponding tip portion 3a of the lead frame 3 are connected by a bonding wire 4. Further, a mold resin 5 is applied so as to seal the semiconductor chip 1 and the bonding wires 4, thereby fixing each member and improving moisture resistance. After that, the tip of the exposed portion of the lead frame 3 is bent. This completes the semiconductor device.
【０００４】[0004]
【発明が解決しようとする課題】しかし、上記した従来
技術にあっては、半導体チップにリードフレームの先端
部を接着するに際し、加熱と圧着が行われるため、図６
に示すように、流動化した接着剤２ａが周囲にはみ出
す。このはみ出し量は接着剤の塗布厚、リード面積、パ
ターン形状によって不均一になる。特に、ワイヤボンデ
ィング用電極部、リードフレームのワイヤボンディング
部へのはみ出しが発生した場合には、ワイヤボンディン
グが不可能になる。However, in the above-mentioned conventional technique, heating and pressure bonding are performed when the tip portion of the lead frame is bonded to the semiconductor chip.
As shown in FIG. 3, the fluidized adhesive 2a protrudes to the surroundings. This protrusion amount becomes non-uniform depending on the adhesive coating thickness, the lead area, and the pattern shape. In particular, if the electrode portion for wire bonding and the lead frame protrude to the wire bonding portion, wire bonding becomes impossible.
【０００５】そこで、本発明の目的は、ワイヤボンディ
ング部等への接着剤のはみ出しを無くすことのできるリ
ードフレームを提供することにある。Therefore, an object of the present invention is to provide a lead frame capable of preventing the adhesive from protruding to the wire bonding portion and the like.
【０００６】[0006]
【課題を解決するための手段】上記の目的を達成するた
めに、この発明は、接着剤を用いてリードフレームを半
導体チップに固定するＬＯＣ方式の半導体装置におい
て、前記リードフレームの前記接着剤が塗布される部分
に加熱及び加圧時の余剰接着剤を流入させる余剰接着剤
流入部を設けるようにしている。In order to achieve the above object, the present invention provides a LOC type semiconductor device in which a lead frame is fixed to a semiconductor chip by using an adhesive, wherein the adhesive of the lead frame is A surplus adhesive inflow portion is provided to allow the surplus adhesive to flow into the applied portion during heating and pressurization.
【０００７】前記余剰接着剤流入部は、前記接着剤の塗
布部分をとり囲むように設けられる溝であり、また、余
剰接着剤を限定された位置へ排出する排出溝を有する。The surplus adhesive inflow portion is a groove provided so as to surround the applied portion of the adhesive, and has a discharge groove for discharging the surplus adhesive to a limited position.
【０００８】[0008]
【作用】上記した手段によれば、リードフレームの先端
部に接着剤を塗布して半導体チップに接着するに際し、
リードフレームの先端部に形成した余剰接着剤流入部に
は、塗布した接着剤を加熱及び加圧処理されるときに接
着面からはみ出した接着剤が流入し、余剰接着剤をリー
ドフレームの先端部内に溜めるように機能する。また、
排出溝が余剰接着剤の広がりを防ぎ、限定された位置へ
排出する。この結果、ワイヤボンディング部等への接着
剤のはみ出しを無くし、ワイヤボンディングが確実に行
えるようにすることができる。According to the above-mentioned means, when the adhesive is applied to the tip portion of the lead frame to adhere to the semiconductor chip,
The surplus adhesive inflow portion formed at the tip of the lead frame flows into the surplus adhesive from the bonding surface when the applied adhesive is heated and pressure-treated, and the surplus adhesive is introduced into the tip of the lead frame. It functions as a reservoir. Also,
The discharge groove prevents the excess adhesive from spreading and discharges it to a limited position. As a result, it is possible to prevent the adhesive from protruding to the wire bonding portion and the like, and to ensure the wire bonding.
【０００９】[0009]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。 〔実施例〕図１は本発明によるリードフレームの第１の
実施例の主要部の構成を示す斜視図である。Embodiments of the present invention will be described below with reference to the drawings. [Embodiment] FIG. 1 is a perspective view showing a structure of a main portion of a first embodiment of a lead frame according to the present invention.
【００１０】図１に示すように、リードフレーム３の先
端部３ａの接着面の周囲には枠形（“口”の字形）に余
剰接着剤流入部としての溝６が設けられている。溝６の
断面形状は、Ｖ字形、Ｕ字形、Ｍ字形、Ｈ字形、＃字
形、半円形等の断面形状にすることができ、その加工に
はプレス等を用いることができる。また、溝６の平面形
状は枠形のほか、“日”の字形、“田”の字形、“且”
又は“目”の字形等にすることもできる。また、溝６の
深さ及び幅については後記するが、溝の深さを１０〜５
０μｍ程度にし、溝の幅を２０〜１００μｍ程度にすれ
ば本発明の効果を得ることができる。溝６は排出溝６ａ
を有する。As shown in FIG. 1, a groove 6 as a surplus adhesive inflow portion is provided around the bonding surface of the tip portion 3a of the lead frame 3 in a frame shape (a "mouth" shape). The cross-sectional shape of the groove 6 can be V-shaped, U-shaped, M-shaped, H-shaped, # -shaped, semi-circular, or the like, and a press or the like can be used for its processing. In addition to the frame shape, the plane shape of the groove 6 is a "day" shape, a "field" shape, and a "and" shape.
Alternatively, it may be a "eye" shape or the like. Although the depth and width of the groove 6 will be described later, the depth of the groove is set to 10 to 5
The effect of the present invention can be obtained by setting the groove width to about 0 μm and the groove width to about 20 to 100 μm. Groove 6 is discharge groove 6a
Have.
【００１１】このような溝６を設けることによって、接
着面に塗布された接着剤２は、接着に際して加熱及び加
圧が行われたとき、流動化した接着剤の一部が溝６へ流
れ込み、また、図２に示すように、排出溝６ａがワイヤ
ボンディング等に支障のないところへ余剰接着剤２ａを
排出するので、ワイヤボンディング部等へ流れ出す接着
剤を無くすることができる。By providing the groove 6 as described above, the adhesive 2 applied to the bonding surface is such that part of the fluidized adhesive flows into the groove 6 when heating and pressure are applied during bonding. Further, as shown in FIG. 2, since the excess adhesive 2a is discharged to the place where the discharge groove 6a does not hinder the wire bonding or the like, the adhesive flowing out to the wire bonding portion or the like can be eliminated.
【００１２】本発明者らは上記構成によるリードフレー
ムについて、以下のような試験を行った。すなわち、リ
ードフレーム３の先端部３ａの幅を０．６ｍｍとし、図
１に示すように溝６を設け、接着剤を塗布した後、チッ
プ代替え材としてのガラス板に貼り付け、接着剤の流れ
を確認した。その結果、図３に示すように、溝６の深さ
が１０μｍで溝の幅が２０μｍとする組み合わせのあた
りから顕著な効果が見られる。そして、溝６の深さを５
０μｍ、溝の幅を１００μｍにすれば、リードフレーム
３の先端部３ａの周囲には接着剤の流出は全く見られな
い状態になることがわかる。The present inventors conducted the following tests on the lead frame having the above-mentioned structure. That is, the width of the tip portion 3a of the lead frame 3 is set to 0.6 mm, the groove 6 is provided as shown in FIG. 1, the adhesive is applied, and then the adhesive is applied to a glass plate serving as a chip substitute material. It was confirmed. As a result, as shown in FIG. 3, a remarkable effect is seen around the combination in which the depth of the groove 6 is 10 μm and the width of the groove is 20 μm. Then, the depth of the groove 6 is set to 5
It can be seen that when the groove width is set to 0 μm and the groove width is set to 100 μm, the adhesive does not flow out around the tip portion 3a of the lead frame 3 at all.
【００１３】[0013]
【発明の効果】以上説明した通り、この発明は、接着剤
を用いてリードフレームを半導体チップに固定するＬＯ
Ｃ方式の半導体装置において、前記リードフレームの前
記接着剤が塗布される部分に加熱及び加圧時の余剰接着
剤を流入させる余剰接着剤流入部を設けるようにしたの
で、ワイヤボンディング部等への接着剤のはみ出しを無
くし、ワイヤボンディングが確実に行えるようにするこ
とができる。As described above, according to the present invention, the LO for fixing the lead frame to the semiconductor chip by using the adhesive.
In the C-type semiconductor device, since an excess adhesive inflow portion for inflowing the excess adhesive at the time of heating and pressurizing is provided in a portion of the lead frame to which the adhesive is applied, it is possible to connect to the wire bonding portion or the like. It is possible to eliminate the protrusion of the adhesive and to ensure the wire bonding.
【図１】本発明によるリードフレームの実施例の主要部
の構成を示す斜視図である。FIG. 1 is a perspective view showing a configuration of a main part of an embodiment of a lead frame according to the present invention.
【図２】本発明に係る余剰接着剤流入部の効果を示す説
明図である。FIG. 2 is an explanatory diagram showing an effect of a surplus adhesive inflow portion according to the present invention.
【図３】図１の実施例による余剰接着剤の流出防止効果
を示す説明図である。FIG. 3 is an explanatory diagram showing an effect of preventing the surplus adhesive from flowing out according to the embodiment of FIG.
【図４】ＬＯＣパッケージによる半導体装置の一例を示
す断面図である。FIG. 4 is a cross-sectional view showing an example of a semiconductor device using an LOC package.
【図５】図１における半導体装置の接着剤塗布面の詳細
を示す斜視図である。5 is a perspective view showing details of an adhesive application surface of the semiconductor device in FIG.
【図６】図６の状態で半導体チップに対する接着を行っ
た場合の余剰接着剤のはみ出しを示す説明図である。FIG. 6 is an explanatory diagram showing the protrusion of excess adhesive when the semiconductor chip is bonded in the state of FIG. 6;
１ 半導体チップ ２ 接着剤 ３ リードフレーム ３ａ 先端部 ６ 溝 ６ａ 排出溝 1 Semiconductor Chip 2 Adhesive 3 Lead Frame 3a Tip 6 Groove 6a Discharge Groove
Claims (3)
チップに固定するＬＯＣ方式の半導体装置において、前
記リードフレームの前記接着剤が塗布される部分に加熱
及び加圧時の余剰接着剤を流入させる余剰接着剤流入部
を設けたことを特徴とするリードフレーム。1. In a LOC type semiconductor device in which a lead frame is fixed to a semiconductor chip by using an adhesive, a surplus adhesive at the time of heating and pressurizing is flown into a portion of the lead frame to which the adhesive is applied. A lead frame having a surplus adhesive inflow portion.
塗布部分をとり囲むように設けられる溝であることを特
徴とする請求項１記載のリードフレーム。2. The lead frame according to claim 1, wherein the surplus adhesive inflow portion is a groove provided so as to surround a portion where the adhesive is applied.
剤を限定された位置へ排出する排出溝を有することを特
徴とする請求項１記載のリードフレーム。3. The lead frame according to claim 1, wherein the excess adhesive inflow portion has a discharge groove for discharging the excess adhesive to a limited position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP491695A JPH08195468A (en) | 1995-01-17 | 1995-01-17 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP491695A JPH08195468A (en) | 1995-01-17 | 1995-01-17 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08195468A true JPH08195468A (en) | 1996-07-30 |
Family
ID=11596961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP491695A Pending JPH08195468A (en) | 1995-01-17 | 1995-01-17 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08195468A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100216991B1 (en) * | 1996-09-11 | 1999-09-01 | 윤종용 | Leadframe having adhesive layer |
| EP1339102A1 (en) * | 2000-11-01 | 2003-08-27 | Mitsui High-tec, Inc. | Lead frame and semiconductor device using this |
-
1995
- 1995-01-17 JP JP491695A patent/JPH08195468A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100216991B1 (en) * | 1996-09-11 | 1999-09-01 | 윤종용 | Leadframe having adhesive layer |
| EP1339102A1 (en) * | 2000-11-01 | 2003-08-27 | Mitsui High-tec, Inc. | Lead frame and semiconductor device using this |
| EP1339102A4 (en) * | 2000-11-01 | 2009-04-29 | Mitsui High Tec | Lead frame and semiconductor device using this |
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