JPH0817730A - Polycrystal thin film of semiconductor device and its manufacture - Google Patents
Polycrystal thin film of semiconductor device and its manufactureInfo
- Publication number
- JPH0817730A JPH0817730A JP15117094A JP15117094A JPH0817730A JP H0817730 A JPH0817730 A JP H0817730A JP 15117094 A JP15117094 A JP 15117094A JP 15117094 A JP15117094 A JP 15117094A JP H0817730 A JPH0817730 A JP H0817730A
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- JP
- Japan
- Prior art keywords
- thin film
- amorphous
- amorphous thin
- film
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、イメージセンサや液晶
ディスプレイなどに用いられ、石英またはガラス製の絶
縁性基板上の活性層部分に用いられる半導体装置の多結
晶薄膜およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline thin film of a semiconductor device used for an image sensor, a liquid crystal display or the like and used for an active layer portion on an insulating substrate made of quartz or glass, and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来、石英またはガラス製の絶縁性基板
上の活性層部分に用いる半導体装置の多結晶薄膜は、イ
メージセンサや液晶ディスプレイなどにおけるトランジ
スタや抵抗などに用いられている。この多結晶薄膜を形
成する方法として、非晶質薄膜をスパッタ法、ＬＰＣＶ
Ｄ法およびプラズマＣＶＤ法などの薄膜形成法により形
成し、これに熱、光、Ｘ線などのエネルギーを加えるこ
とにより固相での結晶成長を行う固相成長法により、多
結晶薄膜を形成する方法が広く行われている。特に、半
導体材料として広く用いられている、シリコンを主材料
とした多結晶シリコン薄膜の場合、固相成長法として
は、真空または窒素などの不活性ガス雰囲気中の加熱炉
で、５８０℃以上の温度に加熱して多結晶化させる方法
が用いられている。2. Description of the Related Art Conventionally, a polycrystalline thin film of a semiconductor device used for an active layer portion on an insulating substrate made of quartz or glass has been used for transistors and resistors in image sensors and liquid crystal displays. As a method for forming this polycrystalline thin film, an amorphous thin film is sputtered, LPCV is used.
A polycrystalline thin film is formed by a solid phase growth method in which a thin film forming method such as the D method and the plasma CVD method is used, and energy is applied thereto such as heat, light, and X-rays to perform crystal growth in the solid phase. The method is widely practiced. In particular, in the case of a polycrystalline silicon thin film containing silicon as a main material, which is widely used as a semiconductor material, the solid phase growth method includes a heating furnace in an atmosphere of an inert gas such as vacuum or nitrogen at 580 ° C. or higher. A method of heating to a temperature to cause polycrystallization is used.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、近年、
絶縁性基板として、歪点６４０℃の安価な高歪点ガラス
基板を用いることが望まれているが、このガラス基板を
用いた場合、その変質および変形などの問題から、処理
に要する温度をせいぜい６００℃程度またはそれ以下に
する必要がある。However, in recent years,
It is desired to use an inexpensive high strain point glass substrate having a strain point of 640 ° C. as an insulating substrate. However, when this glass substrate is used, the temperature required for processing is at most due to problems such as alteration and deformation. It should be about 600 ° C or lower.
【０００４】一方、固相成長法では、結晶化に要する固
相成長時間、および、固相成長後の多結晶薄膜の特性
は、主に、非晶質膜の形成条件と固相成長の処理温度で
決定される。まず、固相成長の処理温度に関しては、処
理温度を高くするにしたがって、固相成長時間は短くな
り、結晶粒内の欠陥も少なくなり、固相成長後の多結晶
薄膜の特性も良くなるが、上記ガラス基板を用いた場
合、上記のように最高温度は６００℃程度にしなければ
ならない。次に、非晶質膜の形成条件に関しては、固相
成長時間と固相成長後の多結晶薄膜の特性とは相反する
関係にあり、現在のところ両方を満たす成膜方法および
条件は見いだされておらず、上記６００℃程度の低い処
理温度で、かつ固相成長後の多結晶薄膜の特性を満足さ
せる条件で多結晶薄膜を形成した場合、８時間程度の処
理時間を要しており、時間がかかりすぎるという問題を
有していた。On the other hand, in the solid phase growth method, the solid phase growth time required for crystallization and the characteristics of the polycrystalline thin film after solid phase growth are mainly based on the conditions for forming an amorphous film and the solid phase growth treatment. Determined by temperature. First, regarding the processing temperature of solid phase growth, the higher the processing temperature, the shorter the solid phase growth time, the fewer defects in crystal grains, and the better the characteristics of the polycrystalline thin film after solid phase growth. When the above glass substrate is used, the maximum temperature must be about 600 ° C. as described above. Next, regarding the conditions for forming an amorphous film, there is a contradictory relationship between the solid-phase growth time and the characteristics of the polycrystalline thin film after solid-phase growth, and at present a film-forming method and conditions satisfying both have been found. However, if the polycrystalline thin film is formed at the low processing temperature of about 600 ° C. and under the conditions that satisfy the characteristics of the polycrystalline thin film after solid phase growth, the processing time of about 8 hours is required, It had a problem that it took too long.
【０００５】即ち、６００℃程度の低い処理温度、多結
晶薄膜の特性、および製造時間の短縮の３つの条件は相
互に関連しており、この３条件を満足させることは難し
いという問題を有していた。That is, the three conditions of the low processing temperature of about 600 ° C., the characteristics of the polycrystalline thin film, and the shortening of the manufacturing time are interrelated, and it is difficult to satisfy these three conditions. Was there.
【０００６】本発明は、上記従来の問題を解決するもの
で、多結晶薄膜の特性を維持しつつ、低温で固相成長時
間を短縮することができる半導体装置の多結晶薄膜およ
びその製造方法を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and provides a polycrystalline thin film for a semiconductor device and a method for manufacturing the same, which can shorten the solid phase growth time at low temperature while maintaining the characteristics of the polycrystalline thin film. The purpose is to provide.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置の多
結晶薄膜は、絶縁層と第１の薄膜、および、第２の薄膜
に比べて結晶核の発生密度の高い該第１の薄膜と第２の
薄膜がそれぞれ界面を接するように設けられ、かつ該第
１の薄膜および第２の薄膜が非晶質から多結晶化されて
いるものであり、そのことにより上記目的が達成され
る。また、本発明の半導体装置の多結晶薄膜は、絶縁性
基板上に、絶縁層と第１の薄膜、および、第２の薄膜に
比べて結晶核の発生密度の高い該第１の薄膜と第２の薄
膜がそれぞれ界面を接するように設けられ、かつ該第１
の薄膜および第２の薄膜が非晶質から多結晶化されてい
るものであり、そのことにより上記目的が達成される。A polycrystalline thin film of a semiconductor device according to the present invention comprises an insulating layer, a first thin film, and a first thin film having a higher generation density of crystal nuclei than a second thin film. The second thin films are provided so that their interfaces are in contact with each other, and the first thin film and the second thin film are polycrystallized from amorphous, whereby the above object is achieved. In addition, the polycrystalline thin film of the semiconductor device of the present invention comprises an insulating layer, a first thin film, and a first thin film and a first thin film having a higher crystal nucleus generation density than the second thin film on an insulating substrate. Two thin films are provided so that their interfaces are in contact with each other, and
The thin film and the second thin film are amorphous to polycrystal, whereby the above-mentioned object is achieved.
【０００８】ここで、絶縁層と第１の非晶質薄膜と第２
の非晶質薄膜とが下層からこの順に積層されて設けられ
ていても良いし、逆に、第２の非晶質薄膜と第１の非晶
質薄膜と絶縁層とが下層から順次積層されて設けられて
いても良い。Here, the insulating layer, the first amorphous thin film, and the second
The amorphous thin film may be laminated in this order from the lower layer, or conversely, the second amorphous thin film, the first amorphous thin film and the insulating layer may be sequentially laminated from the lower layer. May be provided.
【０００９】さらに、好ましくは、本発明の半導体装置
における第１の薄膜および第２の薄膜は同一材料の非晶
質から多結晶化されている。また、好ましくは、本発明
の半導体装置における多結晶化されている第１の薄膜お
よび第２の薄膜は多結晶シリコン膜で構成されている。
さらに、好ましくは、本発明の半導体装置における請求
項１の絶縁層はガラス基板で構成される。さらに、本発
明の半導体装置における多結晶薄膜はトランジスタのチ
ャネル部を構成してもよい。Further, preferably, the first thin film and the second thin film in the semiconductor device of the present invention are polycrystallized from amorphous of the same material. Further, preferably, the polycrystallized first thin film and second polycrystalline thin film in the semiconductor device of the present invention are composed of polycrystalline silicon films.
Further, preferably, the insulating layer according to claim 1 in the semiconductor device of the present invention is composed of a glass substrate. Further, the polycrystalline thin film in the semiconductor device of the present invention may form a channel portion of a transistor.
【００１０】また、本発明の半導体装置の多結晶薄膜製
造方法は、絶縁層と第１の非晶質薄膜、および、第２の
非晶質薄膜に比べて結晶核の発生密度の高い第１の非晶
質薄膜と該第２の非晶質薄膜がそれぞれ界面を接するよ
うに堆積し、少なくとも該第１の非晶質薄膜および第２
の非晶質薄膜にエネルギーを加えて多結晶化させて多結
晶薄膜とするものであり、そのことにより上記目的が達
成される。また、本発明の半導体装置の多結晶薄膜製造
方法は、絶縁性基板上に、絶縁層と第１の非晶質薄膜、
および、第２の非晶質薄膜に比べて結晶核の発生密度の
高い第１の非晶質薄膜と該第２の非晶質薄膜がそれぞれ
界面を接するように堆積し、少なくとも該第１の非晶質
薄膜および第２の非晶質薄膜にエネルギーを加えて多結
晶化させて多結晶薄膜とするものであり、そのことによ
り上記目的が達成される。Further, according to the method of manufacturing a polycrystalline thin film of a semiconductor device of the present invention, the first density of crystal nuclei is higher than that of the insulating layer, the first amorphous thin film, and the second amorphous thin film. The amorphous thin film and the second amorphous thin film are deposited so that their interfaces are in contact with each other, and at least the first amorphous thin film and the second amorphous thin film are deposited.
The amorphous thin film is polycrystallized by applying energy to obtain a polycrystalline thin film, and the above object is achieved thereby. A method for manufacturing a polycrystalline thin film of a semiconductor device according to the present invention is a method for producing a polycrystalline thin film on an insulating substrate,
Further, the first amorphous thin film having a higher generation density of crystal nuclei than the second amorphous thin film and the second amorphous thin film are deposited such that their interfaces are in contact with each other, and at least the first amorphous thin film is deposited. Energy is applied to the amorphous thin film and the second amorphous thin film to polycrystallize the amorphous thin film and the second amorphous thin film to form a polycrystalline thin film, thereby achieving the above object.
【００１１】ここで、絶縁層と第１の非晶質薄膜と第２
の非晶質薄膜とがこの順に積層されても良いし、逆に、
第２の非晶質薄膜と第１の非晶質薄膜と絶縁層とが順次
積層されても良い。Here, the insulating layer, the first amorphous thin film, and the second
The amorphous thin film may be laminated in this order, or conversely,
The second amorphous thin film, the first amorphous thin film, and the insulating layer may be sequentially stacked.
【００１２】さらに、好ましくは、本発明の半導体装置
の多結晶薄膜製造方法において、第１の非晶質薄膜にお
ける結晶核の発生密度は、該第１の非晶質薄膜の堆積温
度、成膜圧力、原料ガス流量およびプラズマ電力のうち
少なくともいずれかにより制御される。さらに、好まし
くは、本発明の半導体装置の多結晶薄膜製造方法におけ
る第１の非晶質薄膜の堆積温度を５００〜５７０℃に設
定し、多結晶化させる温度を５８０℃〜６４０℃に設定
する。Further preferably, in the method for producing a polycrystalline thin film of a semiconductor device according to the present invention, the generation density of crystal nuclei in the first amorphous thin film is determined by the deposition temperature of the first amorphous thin film and the film formation. It is controlled by at least one of pressure, raw material gas flow rate, and plasma power. Further, preferably, in the method for producing a polycrystalline thin film of a semiconductor device of the present invention, the deposition temperature of the first amorphous thin film is set to 500 to 570 ° C, and the temperature for polycrystallization is set to 580 ° C to 640 ° C. .
【００１３】[0013]
【作用】非晶質薄膜が固相成長により結晶化する場合、
固相成長中に結晶粒の種となる結晶核の発生する密度
（結晶核発生密度）と各結晶粒の成長する速度（結晶成
長速度）の２つの要素により、結晶粒径や結晶成長に要
する時間が決定されるが、本発明者等は、絶縁層に界面
が接する非晶質薄膜の形成条件としての堆積温度や成膜
圧力などに対する結晶核発生密度の変化が、結晶成長速
度の変化に比べて大きいことから、結晶核発生密度が重
要な要素になっていることを発見した。この結晶核発生
密度が大きくなれば、固相成長後の結晶粒径は小さくな
るが、結晶成長に要する時間は短くなる。[Operation] When an amorphous thin film is crystallized by solid phase growth,
The crystal grain size and the crystal growth are required depending on two factors, that is, the density at which crystal nuclei that become seeds of crystal grains are generated during solid phase growth (crystal nucleus generation density) and the growth rate of each crystal grain (crystal growth rate). Although the time is determined, the present inventors have found that the change in the crystal nucleus generation density with respect to the deposition temperature and the film forming pressure as the formation conditions of the amorphous thin film whose interface is in contact with the insulating layer causes the change in the crystal growth rate. It was found that the crystal nucleus generation density is an important factor because it is larger than the above. If the crystal nucleus generation density increases, the crystal grain size after solid phase growth decreases, but the time required for crystal growth decreases.
【００１４】一方、非晶質薄膜が固相成長により結晶化
する過程において、結晶の種となる結晶核は絶縁層と非
晶質薄膜の界面から発生する特性を有している。そこ
で、結晶核の発生密度は絶縁層と接する側の非晶質薄膜
の堆積温度や成膜圧力などの形成条件により制御するこ
とで、目的とする多結晶薄膜を得る母材としての非晶質
薄膜よりも結晶核の発生密度が高い非晶質薄膜となるよ
うな非晶質薄膜を形成する。このように、結晶核の発生
密度は絶縁層と接する側の非晶質薄膜の堆積温度や成膜
圧力などの形成条件により制御し、固相成長後の多結晶
薄膜の特性は、目的とする多結晶薄膜を得る母材として
の非晶質薄膜の堆積温度条件により制御する。これらの
非晶質薄膜に熱などのエネルギーを加えて固相成長させ
るので、低温度処理の下でも、固相成長時間は短縮さ
れ、使用目的とする部分の多結晶薄膜の特性も良好なも
のとなる。On the other hand, in the process in which the amorphous thin film is crystallized by solid phase growth, crystal nuclei as seeds of crystals have a characteristic of being generated from the interface between the insulating layer and the amorphous thin film. Therefore, the generation density of crystal nuclei is controlled by forming conditions such as the deposition temperature and film forming pressure of the amorphous thin film on the side in contact with the insulating layer, so that the amorphous thin film as the base material from which the desired polycrystalline thin film is obtained. An amorphous thin film is formed such that the generation density of crystal nuclei is higher than that of the thin film. Thus, the generation density of crystal nuclei is controlled by forming conditions such as the deposition temperature and film forming pressure of the amorphous thin film on the side in contact with the insulating layer, and the characteristics of the polycrystalline thin film after solid phase growth are set to the desired values. It is controlled by the deposition temperature condition of the amorphous thin film as the base material for obtaining the polycrystalline thin film. Since solid phase growth is performed by applying energy such as heat to these amorphous thin films, the solid phase growth time is shortened even under low temperature treatment, and the characteristics of the polycrystalline thin film of the intended part are also good. Becomes
【００１５】また、これら非晶質薄膜が同一の非晶質材
料であれば、成膜条件だけを変えて一連の工程で簡便に
２層構造の非晶質薄膜を成膜可能となる。If these amorphous thin films are made of the same amorphous material, it is possible to easily form an amorphous thin film having a two-layer structure in a series of steps by changing only the film forming conditions.
【００１６】さらに、これら多結晶薄膜が多結晶シリコ
ン膜の場合には、上記効果が容易に確実に得られる。Further, when the polycrystalline thin film is a polycrystalline silicon film, the above effect can be easily and surely obtained.
【００１７】さらに、低温度で処理可能であるので、安
価なガラス基板を変質および変形なく用いられる。Furthermore, since it can be processed at a low temperature, an inexpensive glass substrate can be used without alteration or deformation.
【００１８】さらに、上記多結晶薄膜をトランジスタの
チャネル部に用いると、低温度処理の下、移動度や閾値
電圧などのトランジスタ特性を維持しつつ、固相成長時
間を短縮することができる。Further, when the above polycrystalline thin film is used for the channel portion of a transistor, the solid phase growth time can be shortened while maintaining the transistor characteristics such as mobility and threshold voltage under low temperature treatment.
【００１９】さらに、第１の非晶質薄膜における結晶核
の発生密度は、第１の非晶質薄膜の堆積温度、成膜圧
力、原料ガス流量またはプラズマ電力により制御され、
これら制御ファクターを複数用いるとより一層容易に制
御可能となる。Further, the generation density of crystal nuclei in the first amorphous thin film is controlled by the deposition temperature of the first amorphous thin film, the film forming pressure, the raw material gas flow rate or the plasma power,
If a plurality of these control factors are used, the control becomes easier.
【００２０】さらに、絶縁層と接する側の非晶質薄膜の
堆積温度を５００〜５７０℃に設定し、多結晶化させる
温度を５８０℃〜６４０℃に設定すれば、低温度処理の
下、固相成長時間の短縮、および多結晶薄膜の特性がよ
り良好なものとなる。Further, if the deposition temperature of the amorphous thin film on the side in contact with the insulating layer is set to 500 to 570 ° C. and the temperature for polycrystallizing is set to 580 ° C. to 640 ° C., it will be solidified under low temperature treatment. The phase growth time is shortened and the characteristics of the polycrystalline thin film are improved.
【００２１】[0021]
【実施例】以下、本発明の実施例について説明する。Embodiments of the present invention will be described below.
【００２２】図１は本発明の一実施例を示す半導体装置
の多結晶膜製造工程における一部断面図である。図１に
おいて、絶縁層としてのガラス基板１上に非晶質薄膜２
が設けられ、この非晶質薄膜２上に非晶質薄膜３が設け
られている。これら非晶質薄膜２と非晶質薄膜３は同一
非晶質材料からなり、非晶質薄膜３に比べて結晶核の発
生密度が高くなるように、非晶質薄膜２の堆積温度また
は成膜圧力などの成膜条件を制御する。これらの非晶質
薄膜２および非晶質薄膜３が、例えば非晶質シリコン膜
の場合は、多結晶化されて多結晶シリコン膜となる。FIG. 1 is a partial cross-sectional view in the manufacturing process of a polycrystalline film of a semiconductor device showing an embodiment of the present invention. In FIG. 1, an amorphous thin film 2 is formed on a glass substrate 1 as an insulating layer.
Is provided, and the amorphous thin film 3 is provided on the amorphous thin film 2. The amorphous thin film 2 and the amorphous thin film 3 are made of the same amorphous material, and the deposition temperature or the deposition temperature of the amorphous thin film 2 is set so that the generation density of crystal nuclei is higher than that of the amorphous thin film 3. Control film forming conditions such as film pressure. When the amorphous thin film 2 and the amorphous thin film 3 are, for example, amorphous silicon films, they are polycrystallized to be polycrystalline silicon films.
【００２３】この場合、絶縁層としてのガラス基板１と
非晶質薄膜２の界面から主たる結晶核が成長するが、結
晶核発生層として絶縁層が良く、例えば、ＳｉＯ2、Ｓ
ｉxＮy、ＴｉＮなどの金属窒化物、ＴｉＯ2などの金属
酸化物などを用いることができる。In this case, the main crystal nuclei grow from the interface between the glass substrate 1 as the insulating layer and the amorphous thin film 2, but the insulating layer is preferable as the crystal nucleus generating layer, for example, SiO 2 , S.
Metal nitrides such as i x N y and TiN, metal oxides such as TiO 2 can be used.
【００２４】上記構成の多結晶薄膜の製造工程について
具体的に説明する。The manufacturing process of the polycrystalline thin film having the above structure will be specifically described.
【００２５】絶縁性基板として、歪み温度が約６４０℃
の高歪点ガラス基板１を用いる。このガラス基板１上に
界面が接するように、下層の非晶質薄膜２として、純ジ
シランガスを原料として基板温度４５０〜６００℃、圧
力０．１〜０．４Ｔｏｒｒの減圧気相化学成長（略して
ＬＰＣＶＤ）法により、膜厚２０ｎｍ堆積する。続い
て、非晶質薄膜２上に界面が接するように、上層の非晶
質薄膜３として、同じく、純ジシランガスを原料として
圧力０．４Ｔｏｒｒ、基板温度４５０℃のＬＰＣＶＤ法
により、膜厚１００ｎｍ堆積し、２層構造の非晶質薄膜
とする。ただし、下層の堆積温度が６００℃の場合には
堆積時に多結晶薄膜となるため、多結晶−非晶質の２層
構造になる。As an insulating substrate, the strain temperature is about 640 ° C.
The high strain point glass substrate 1 is used. As a lower layer amorphous thin film 2, pure disilane gas is used as a raw material so that the interface is in contact with the glass substrate 1, and the substrate temperature is 450 to 600 ° C. and the pressure is 0.1 to 0.4 Torr. A film thickness of 20 nm is deposited by the LPCVD method. Then, a 100 nm-thick film is deposited as an upper amorphous thin film 3 by an LPCVD method using pure disilane gas as a raw material at a pressure of 0.4 Torr and a substrate temperature of 450 ° C. so that the interface is in contact with the amorphous thin film 2. To form an amorphous thin film having a two-layer structure. However, when the deposition temperature of the lower layer is 600 ° C., a polycrystalline thin film is formed at the time of deposition, and thus a polycrystalline-amorphous two-layer structure is formed.
【００２６】次に、上記したように製造された多結晶薄
膜をチャネルの活性層に用いたトランジスタの製造工程
について具体的に説明する。Next, the manufacturing process of the transistor using the polycrystalline thin film manufactured as described above for the active layer of the channel will be specifically described.
【００２７】図２は図１の多結晶薄膜を用いた薄膜トラ
ンジスタ製造工程における一部断面図である。図２ａの
状態は、上記したように、ガラス基板１上に堆積した上
下層の非晶質薄膜２，３に熱を加えて固相成長させ多結
晶化し、多結晶薄膜２’，３’が形成された状態であ
る。図２ｂに示すように、この多結晶薄膜２’，３’を
パターニングして所定形状にし、所定形状の多結晶薄膜
２’，３’およびガラス基板１上に、４５０℃でＡＰＣ
ＶＤ法によりＳｉＯ2からなるゲート酸化膜４を堆積さ
せる。さらに、図２ｃに示すように、この多結晶薄膜
２’，３’上のゲート酸化膜４の中央部にアルミニウム
（Ａｌ）からなるゲート電極５を形成し、このゲート電
極５をマスクとして多結晶薄膜２’，３’にゲート酸化
膜４を介して、ｐ型不純物としてボロン（Ｂ+）、ｎ型
不純物としてリン（Ｐ+）をイオンドーピングし、トラ
ンジスタのソースＳおよびドレインＤを多結晶薄膜
２’，３’内に作る。さらに、図２ｄに示すように、ゲ
ート酸化膜４およびゲート電極５上に絶縁膜６を形成
し、ソースＳおよびドレインＤ上をそれぞれ開口する。
この絶縁膜６上に開口部を介してソースＳに接するよう
にアルミニウム配線７を形成するとともに、絶縁膜６上
に開口部を介してドレインＤに接するようにアルミニウ
ム配線８を形成する。以上によりトップゲート構造の薄
膜トランジスタ９が形成され、ソースＳとドレインＤ間
の多結晶薄膜２’，３’はトランジスタのチャネルとし
て用いられることになる。FIG. 2 is a partial cross-sectional view in a thin film transistor manufacturing process using the polycrystalline thin film of FIG. In the state of FIG. 2a, as described above, the upper and lower amorphous thin films 2 and 3 deposited on the glass substrate 1 are heated to solid-phase-growth to be polycrystallized. It is in a formed state. As shown in FIG. 2b, the polycrystalline thin films 2 ′ and 3 ′ are patterned to have a predetermined shape, and the polycrystalline thin films 2 ′ and 3 ′ having a predetermined shape and the glass substrate 1 are subjected to APC at 450 ° C.
A gate oxide film 4 made of SiO 2 is deposited by the VD method. Further, as shown in FIG. 2c, a gate electrode 5 made of aluminum (Al) is formed at the center of the gate oxide film 4 on the polycrystalline thin films 2'and 3 ', and the polycrystalline silicon is formed using this gate electrode 5 as a mask. The thin films 2'and 3'are ion-doped with boron (B + ) as a p-type impurity and phosphorus (P + ) as an n-type impurity through the gate oxide film 4, and the source S and drain D of the transistor are polycrystalline thin films. Make it in 2'and 3 '. Further, as shown in FIG. 2d, an insulating film 6 is formed on the gate oxide film 4 and the gate electrode 5, and openings are formed on the source S and the drain D, respectively.
An aluminum wiring 7 is formed on the insulating film 6 so as to be in contact with the source S through the opening, and an aluminum wiring 8 is formed on the insulating film 6 so as to be in contact with the drain D through the opening. As described above, the thin film transistor 9 having the top gate structure is formed, and the polycrystalline thin films 2 ′ and 3 ′ between the source S and the drain D are used as the channel of the transistor.
【００２８】上記構成により、以下、その作用を説明す
る。The operation of the above structure will be described below.
【００２９】まず、熱処理して固相成長させると、核発
生層である絶縁層としてのガラス基板１と非晶質薄膜２
との界面から主たる核発生が始まり、非晶質薄膜３の方
向へと核の成長が引き継がれていく。そして、この非晶
質薄膜３は非晶質薄膜２の結晶成長を引き継いで結晶成
長を行う。First, when heat treatment is carried out for solid phase growth, the glass substrate 1 and the amorphous thin film 2 as an insulating layer which is a nucleation layer.
Main nucleation starts from the interface with and the growth of nuclei continues in the direction of the amorphous thin film 3. Then, this amorphous thin film 3 continues the crystal growth of the amorphous thin film 2 to perform crystal growth.
【００３０】このとき、非晶質薄膜２は非晶質薄膜３よ
り核発生密度が大きいので、同じ厚さの非晶質薄膜３が
単独であるのと比較して非晶質薄膜３の結晶成長時間は
短くなる。こうして得られる非晶質薄膜３が結晶化して
得られた多結晶薄膜３’の結晶粒径は、非晶質薄膜２の
影響を受けて単独の場合に比べて小さくなる。このよう
に、結晶粒径が小さくなることから非晶質薄膜３から得
られる多結晶薄膜３’の特性も非晶質薄膜２の影響を受
けて同様に非晶質薄膜３単独の場合とは異なると考えら
れる。例えば、移動度などのトランジスタ特性を考えた
場合、結晶粒径が小さくなると、移動度などのトランジ
スタ特性も小さくなると考えられる。At this time, since the amorphous thin film 2 has a higher nucleus generation density than the amorphous thin film 3, the crystal of the amorphous thin film 3 is different from that of the single amorphous thin film 3 having the same thickness. Growth time will be shorter. The crystal grain size of the polycrystalline thin film 3 ′ obtained by crystallization of the amorphous thin film 3 thus obtained is influenced by the amorphous thin film 2 and becomes smaller than that of a single case. As described above, since the crystal grain size is small, the characteristics of the polycrystalline thin film 3 ′ obtained from the amorphous thin film 3 are also influenced by the amorphous thin film 2 and similarly the case of the amorphous thin film 3 alone. Considered different. For example, considering the transistor characteristics such as mobility, it is considered that the transistor characteristics such as mobility become smaller as the crystal grain size becomes smaller.
【００３１】しかしながら、本発明で得られる非晶質薄
膜３からの多結晶薄膜３’の特性は粒径が小さくなるに
もかかわらず、その特性は変化しない。即ち、非晶質薄
膜２は成長時間を短縮させる働きをし、しかも、この非
晶質薄膜２は非晶質薄膜３の特性に影響を与えず、非晶
質薄膜３の特性はその成膜条件で処理することができ
る。However, the characteristics of the polycrystalline thin film 3'from the amorphous thin film 3 obtained in the present invention do not change even though the grain size becomes small. That is, the amorphous thin film 2 has a function of shortening the growth time, and the amorphous thin film 2 does not affect the characteristics of the amorphous thin film 3, and the characteristics of the amorphous thin film 3 are its film formation. It can be processed according to the conditions.
【００３２】ここで、具体的に具体例と比較例を挙げて
詳しく説明する。Here, a concrete example and a comparative example will be specifically described.
【００３３】上記実施例に対する比較例として、上記下
層の非晶質薄膜２と同じ成膜条件で、膜厚１２０ｎｍ堆
積した１層構造の非晶質薄膜を得る。ただし、この場合
にも堆積温度が６００℃の場合は堆積時に多結晶薄膜と
なる。As a comparative example to the above embodiment, a single-layer structure amorphous thin film having a film thickness of 120 nm is obtained under the same film forming conditions as the lower amorphous thin film 2. However, also in this case, when the deposition temperature is 600 ° C., a polycrystalline thin film is formed at the time of deposition.
【００３４】これら上記実施例の２層構造の非晶質薄膜
と、比較例の１層構造の非晶質薄膜を、純窒素ガス雰囲
気中で６００℃に加熱し、固相成長による結晶化を行う
ことにより多結晶薄膜とする。これらの実施例および比
較例の多結晶薄膜について、透過電子顕微鏡（ＴＥＭ）
による観察により固相成長途中の結晶の比率の変化、固
相成長後の結晶の粒径や結晶性、および固相成長完了時
間を調べ、また、実施例および比較例の多結晶薄膜がチ
ャンネル部となる薄膜トランジスタ（ＴＦＴ）を作成し
て、電界効果移動度や閾値電圧としての電気的特性を調
べた。これらの実施例および比較例の結果を表１に示し
ている。このとき、結晶密度は、透過電子顕微鏡（ＴＥ
Ｍ）による観察により、所定面積中に発生する結晶粒の
数を数えて密度を出している。The two-layered amorphous thin film of the above example and the one-layered amorphous thin film of the comparative example were heated to 600 ° C. in a pure nitrogen gas atmosphere to be crystallized by solid phase growth. By doing so, a polycrystalline thin film is formed. Transmission electron microscopy (TEM) of the polycrystalline thin films of these examples and comparative examples
The change in the ratio of crystals during solid phase growth, the crystal grain size and crystallinity of the crystals after solid phase growth, and the solid phase growth completion time were examined by observation with the. Then, a thin film transistor (TFT) was prepared, and the electric characteristics such as field effect mobility and threshold voltage were examined. The results of these Examples and Comparative Examples are shown in Table 1. At this time, the crystal density is determined by a transmission electron microscope (TE
By observation with M), the density is obtained by counting the number of crystal grains generated in a predetermined area.
【００３５】[0035]
【表１】 [Table 1]
【００３６】ここで、まず、本実施例における２層構造
膜の固相成長時間に対する結晶化の割合の変化を図３に
示す。図３に示すように、下層の非晶質薄膜２の堆積温
度の条件により結晶核の発生密度を制御してやることに
より、結晶化の完了時間が変化しており、下層の非晶質
薄膜２の堆積温度が高いほど固相成長による結晶化時間
を短くすることができる。ここで、結晶体積比率とは単
位体積当りの結晶の占める率である。First, FIG. 3 shows the change in the crystallization ratio with respect to the solid phase growth time of the two-layer structure film in this example. As shown in FIG. 3, the crystallization completion time is changed by controlling the generation density of crystal nuclei according to the condition of the deposition temperature of the lower amorphous thin film 2 and the amorphous thin film 2 of the lower layer is changed. The higher the deposition temperature, the shorter the crystallization time by solid phase growth. Here, the crystal volume ratio is a ratio of crystals per unit volume.
【００３７】次に、下層の非晶質薄膜２の堆積温度の違
いにより結晶化後の多結晶薄膜３’の結晶粒径が変化す
ることを示すため、表１における下層の非晶質薄膜２の
堆積温度と結晶粒径との関係を図４に示しており、本発
明の２層構造の非晶質薄膜２，３を結晶化した場合を●
印で示し、比較例の１層構造の非晶質薄膜を結晶化した
場合を▲印で示している。図４に示すように、本実施例
の２層構造の場合には、上層の非晶質薄膜３も含めて結
晶化が起こるため、比較例の下層の非晶質薄膜単独で結
晶化した多結晶薄膜の結晶粒径よりも本実施例の多結晶
薄膜３’の結晶粒径の方がやや大きくなっているが、こ
れは下層の非晶質薄膜２の堆積温度条件により多結晶薄
膜３’の結晶粒径が制御されていることを示している。Next, in order to show that the crystal grain size of the polycrystalline thin film 3'after crystallization changes depending on the difference in the deposition temperature of the lower amorphous thin film 2, the lower amorphous thin film 2 in Table 1 is shown. 4 shows the relationship between the deposition temperature and the crystal grain size, and shows the case where the amorphous thin films 2 and 3 having a two-layer structure of the present invention are crystallized.
The symbol ∘ indicates the case where the amorphous thin film having the one-layer structure of the comparative example was crystallized. As shown in FIG. 4, in the case of the two-layer structure of the present embodiment, crystallization occurs in the upper amorphous thin film 3 as well, so that the lower amorphous thin film of the comparative example is often crystallized. The crystal grain size of the polycrystalline thin film 3'of this embodiment is slightly larger than the crystal grain size of the crystalline thin film. This depends on the deposition temperature condition of the amorphous thin film 2 of the lower layer. It is shown that the crystal grain size of is controlled.
【００３８】この原因を明らかにするため、非晶質薄膜
２，３の固相成長による結晶化の過程を透過電子顕微鏡
（ＴＥＭ）による詳細な観察、特に膜断面方向の観察、
および、高倍率での観察を行った結果、非晶質薄膜２，
３の形成条件により結晶粒の種となる結晶核の発生密度
が上層と下層で異なっていること、および、下層の非晶
質薄膜２の結晶化を引き継ぎ、上層の非晶質薄膜３の結
晶化が進行していることが明らかになった。したがっ
て、比較例よりも本実施例の多結晶薄膜３’の結晶粒径
の方がやや大きくなるわけである。また、本実施例の２
層構造による多結晶薄膜２’，３’の観察より、下層の
核発生密度の方が上層よりも大きく、その下層の核発生
密度に合わせて上層の非晶質薄膜３が結晶成長すること
により、上層の非晶質薄膜３が単独で結晶成長した場合
よりも結晶の粒径が小さくなるが、このことが逆に、無
理な結晶成長を抑え結晶の粒内の双晶などの欠陥を少な
くしていることが明らかになった。In order to clarify the cause of this, the crystallization process of the amorphous thin films 2 and 3 by solid phase growth is observed in detail by a transmission electron microscope (TEM), especially in the cross-sectional direction of the film.
As a result of observation at high magnification, the amorphous thin film 2.
3. The generation density of crystal nuclei as seeds of crystal grains is different between the upper layer and the lower layer depending on the formation conditions of No. 3, and the crystallization of the amorphous thin film 2 of the lower layer is succeeded to the crystal of the amorphous thin film 3 of the upper layer. It has become clear that the progress is being made. Therefore, the crystal grain size of the polycrystalline thin film 3'of this example is slightly larger than that of the comparative example. In addition, 2 of the present embodiment
According to the observation of the polycrystalline thin films 2 ′ and 3 ′ having the layer structure, the nucleation density of the lower layer is higher than that of the upper layer, and the amorphous thin film 3 of the upper layer is crystal-grown according to the nucleation density of the lower layer. The grain size of the crystal is smaller than that in the case where the upper amorphous thin film 3 grows alone. However, on the contrary, the crystal growth is suppressed and defects such as twins in the grain are reduced. It became clear that they are doing.
【００３９】なお、図４に示すように、下層の非晶質薄
膜２の堆積温度が６００℃の場合の結果において、▲印
で示される比較例の単層の場合と、●印で示される本実
施例の２層構造の場合とで結晶の粒径が大きく異なって
いるが、これは、堆積温度が６００℃の場合、堆積した
時点で多結晶薄膜になるため、上層の非晶質薄膜３単独
で固相による結晶化が起こったためである。このことに
より、本実施例では、下層および上層ともに同一材料の
非晶質薄膜であることが重要となる。As shown in FIG. 4, the results obtained when the deposition temperature of the lower amorphous thin film 2 is 600 ° C. are shown by the black triangles of the comparative example and by the black circles. Although the grain size of the crystal is largely different from that of the two-layer structure of this embodiment, this is because when the deposition temperature is 600 ° C., a polycrystalline thin film is formed at the time of deposition, and thus the upper amorphous thin film is formed. This is because crystallization by the solid phase occurred in 3 alone. Therefore, in this embodiment, it is important that the lower layer and the upper layer are amorphous thin films made of the same material.
【００４０】さらに、下層の非晶質薄膜２の堆積温度の
違いによるトランジスタ特性としてのＮチャネル移動度
（ｃｍ2／Ｖ・ｓ）の変化を図５に示している。図５に
示すように、比較例の１層構造の場合、非晶質薄膜の堆
積温度が４７０℃以上では、堆積温度の上昇とともに、
Ｎチャネル移動度（ｃｍ2／Ｖ・ｓ）は低下している。
これにより、比較例の１層構造の場合、堆積温度が高い
ほど固相成長時間が短縮できたとしても、電界効果移動
度（ｃｍ2／Ｖ・ｓ）や閾値電圧のトランジスタ特性が
低下することを示している。Further, FIG. 5 shows a change in N-channel mobility (cm 2 / V · s) as a transistor characteristic due to a difference in deposition temperature of the lower amorphous thin film 2. As shown in FIG. 5, in the case of the single-layer structure of the comparative example, when the deposition temperature of the amorphous thin film was 470 ° C. or higher, the deposition temperature increased and
The N channel mobility (cm 2 / V · s) is lowered.
As a result, in the case of the one-layer structure of the comparative example, the transistor characteristics of the field effect mobility (cm 2 / V · s) and the threshold voltage are deteriorated even if the solid-phase growth time can be shortened as the deposition temperature becomes higher. Is shown.
【００４１】一方、本実施例の２層構造の場合、下層の
非晶質薄膜２の堆積温度が高い場合でも、比較例の１層
構造の堆積温度４５０℃の場合と、ほぼ同じトランジス
タ特性を示している。これは、薄膜トランジスタ（ＴＦ
Ｔ）ではチャネル部として動作する活性層部分は多結晶
薄膜の表面の数１０ｎｍの部分であり、電気的には、上
層の非晶質薄膜３を結晶化した多結晶薄膜３’の特性を
引き継いでいることを示しているとともに、上記理由に
より、結晶粒内の欠陥も少なくなっているための結果で
ある。On the other hand, in the case of the two-layer structure of this embodiment, even when the deposition temperature of the lower amorphous thin film 2 is high, the transistor characteristics are almost the same as those of the one-layer structure of the comparative example where the deposition temperature is 450 ° C. Shows. This is a thin film transistor (TF
In T), the active layer portion that operates as a channel portion is a portion of several tens of nm on the surface of the polycrystalline thin film, and electrically, the characteristics of the polycrystalline thin film 3 ′ obtained by crystallizing the upper amorphous thin film 3 are taken over. This is because the number of defects in the crystal grains is reduced due to the above reason.
【００４２】以上により本実施例の具体例１〜８によれ
ば、純ジシランガスを原料として、ＬＰＣＶＤ法によ
り、非晶質薄膜２，３を堆積し、非晶質薄膜２，３を安
価なガラス基板１が変質なく使える低温熱処理の６００
℃で固相成長させて多結晶薄膜２’，３’とする場合、
下層の非晶質薄膜２の堆積温度を５００〜５７０℃、上
層の非晶質薄膜３の堆積温度を４５０℃とすることによ
り、固相成長時間を従来８時間であったものを６時間以
下に短縮することができ、併せて、トランジスタなどの
電気的特性が良好な多結晶薄膜２’，３’を得ることが
できる。As described above, according to specific examples 1 to 8 of the present embodiment, the amorphous thin films 2 and 3 are deposited by the LPCVD method using pure disilane gas as a raw material, and the amorphous thin films 2 and 3 are made of inexpensive glass. 600 of low temperature heat treatment that substrate 1 can be used without deterioration
In the case of solid phase growth at ℃ to form polycrystalline thin films 2'and 3 ',
By setting the deposition temperature of the lower amorphous thin film 2 to 500 to 570 ° C. and the deposition temperature of the upper amorphous thin film 3 to 450 ° C., the solid-phase growth time which was 8 hours in the past was 6 hours or less. In addition, it is possible to obtain the polycrystalline thin films 2'and 3'having good electrical characteristics such as transistors.
【００４３】次に、成膜圧力により結晶核の発生密度を
制御する場合について説明する。Next, the case where the generation density of crystal nuclei is controlled by the film formation pressure will be described.
【００４４】図６は結晶核発生速度（×１０6／ｃｍ2・
ｈ）と結晶粒成長速度（μｍ／ｈ）の成膜圧力（ＴＯＲ
Ｒ）依存性を示すグラフである。図６において、○印は
結晶核発生速度の成膜圧力依存性を示しており、□印は
結晶粒成長速度の成膜圧力依存性を示している。結晶核
発生速度による結晶核発生密度は成膜圧力が高くなるに
したがって急激に低下するが、結晶粒成長速度は成膜圧
力が高くなっても殆ど一定である。これにより、成膜圧
力を変化させることで結晶核の発生密度を制御して上層
の非晶質薄膜３に比べて結晶核の発生密度の高い下層の
非晶質薄膜２を堆積させることができる。FIG. 6 shows the crystal nucleus generation rate (× 10 6 / cm 2 ·
h) and the film growth pressure (TOR) of the crystal grain growth rate (μm / h)
R) is a graph showing dependency. In FIG. 6, the mark ◯ indicates the dependency of the crystal nucleus generation rate on the film formation pressure, and the symbol □ indicates the dependence of the crystal grain growth rate on the film formation pressure. The crystal nucleus generation density due to the crystal nucleus generation rate sharply decreases as the film forming pressure increases, but the crystal grain growth rate is almost constant even when the film forming pressure increases. Thereby, by changing the film forming pressure, the generation density of crystal nuclei can be controlled to deposit the lower amorphous thin film 2 having a higher generation density of crystal nuclei than the upper amorphous thin film 3. .
【００４５】したがって、結晶核発生密度の制御パラメ
ータが堆積温度と成膜圧力の違いはあるが、本実施例の
具体例１〜８と同様に、固相成長前の非晶質薄膜２，３
の２層構造として、最上層は目的とする特性をもつ多結
晶薄膜３’を得るための母材としての非晶質薄膜３を所
定成膜圧力条件で作成し、その下層は上層に比べて結晶
核発生密度が高くなる成膜圧力条件で非晶質薄膜２を絶
縁層としてのガラス基板１と界面を接するように作成
し、これら上層と下層の非晶質薄膜２，３に熱を加えて
絶縁層としてのガラス基板１と非晶質薄膜２の界面から
固相成長させて多結晶膜２’，３’を得る。これによ
り、本実施例の具体例１〜８と同様に、結晶核の発生密
度は下層となる非晶質薄膜２の成膜圧力条件により制御
し、固相成長後の多結晶薄膜２’，３’の特性は上層の
非晶質薄膜３の成膜圧力条件により制御することにな
り、目的とする良好な膜特性を有する多結晶薄膜３’を
短時間で得ることができる。Therefore, although the control parameters of the crystal nucleus generation density differ between the deposition temperature and the film formation pressure, the amorphous thin films 2 and 3 before solid phase growth are the same as in Examples 1 to 8 of this embodiment.
As a two-layer structure of the above, the uppermost layer is an amorphous thin film 3 as a base material for obtaining a polycrystalline thin film 3 ′ having desired characteristics, which is formed under a predetermined film forming pressure condition, and the lower layer thereof is higher than the upper layer. The amorphous thin film 2 is formed so that the interface with the glass substrate 1 as an insulating layer is in contact with the amorphous thin films 2 and 3 under the film forming pressure condition where the crystal nucleus generation density becomes high, and heat is applied to these upper and lower amorphous thin films 2 and 3. Then, solid phase growth is performed from the interface between the glass substrate 1 as an insulating layer and the amorphous thin film 2 to obtain polycrystalline films 2'and 3 '. With this, similarly to the specific examples 1 to 8 of the present embodiment, the generation density of crystal nuclei is controlled by the film forming pressure condition of the amorphous thin film 2 as the lower layer, and the polycrystalline thin film 2 ′ after solid phase growth, The characteristic of 3'is controlled by the film forming pressure condition of the upper amorphous thin film 3, so that the polycrystalline thin film 3'having desired desired film characteristics can be obtained in a short time.
【００４６】ここで、図７に結晶粒径（μｍ）の成膜圧
力（ＴＯＲＲ）依存性を示しており、シミュレーション
による結晶化完了時の平均粒径と最大粒径を示してい
る。図７において、■印は最大粒径を示し、◆印は平均
粒径を示しているが、成膜圧力が大きくなるにしたがっ
て、特に最大粒径において、結晶粒径が大きくなること
がわかる。Here, FIG. 7 shows the dependency of the crystal grain size (μm) on the film forming pressure (TORR), and shows the average grain size and the maximum grain size at the completion of crystallization by simulation. In FIG. 7, the mark ■ indicates the maximum grain size, and the mark ◆ indicates the average grain size. It can be seen that the crystal grain size increases particularly with the maximum grain size as the film forming pressure increases.
【００４７】なお、本実施例の具体例１〜８では、絶縁
層としてのガラス基板１上に非晶質薄膜２，３を設けた
２層構造について説明したが、次の表２の具体例９，１
０のように非晶質薄膜の層構造を３層構造または４層構
造としてもよく、この場合、各層において段階的に堆積
温度条件を順次変化させる。In addition, in the specific examples 1 to 8 of this embodiment, the two-layer structure in which the amorphous thin films 2 and 3 are provided on the glass substrate 1 as the insulating layer has been described. 9, 1
The layer structure of the amorphous thin film may be a three-layer structure or a four-layer structure such as 0. In this case, the deposition temperature conditions are sequentially changed in each layer.
【００４８】[0048]
【表２】 [Table 2]
【００４９】例えば、具体例９において、最下層が堆積
温度５５０℃と第３層が堆積温度４５０℃であり、その
間に堆積温度５１０℃の第２層を設けて、段階的に堆積
温度条件を順次変化させている。この場合、２層構造の
上記実施例の下層の非晶質薄膜２の堆積温度５５０℃の
場合の結果とほぼ同じ結果を示す。このように、非晶質
薄膜の構造を多層構造とし、段階的に堆積温度条件を順
次変化させても上記実施例と同じ効果が得られる。ま
た、段階的に堆積温度条件を順次変化させるのではなく
連続的に変化させた構造においても上記実施例と同じ効
果を得ることができる。For example, in Example 9, the lowermost layer has a deposition temperature of 550 ° C. and the third layer has a deposition temperature of 450 ° C., and a second layer having a deposition temperature of 510 ° C. is provided between them, and the deposition temperature conditions are set stepwise. It is changing sequentially. In this case, the result is almost the same as the result when the deposition temperature of the lower amorphous thin film 2 of the above-mentioned embodiment having the two-layer structure is 550 ° C. Thus, even if the amorphous thin film has a multi-layered structure and the deposition temperature conditions are changed step by step, the same effect as that of the above embodiment can be obtained. Further, the same effect as that of the above-described embodiment can be obtained even in the structure in which the deposition temperature condition is not changed stepwise but continuously changed.
【００５０】このことは、結晶核の発生密度に関して
は、ガラス基板に対して直上の非晶質薄膜の形成条件に
より決まり、また、トランジスタ特性に関しては最上層
の非晶質薄膜の形成条件により決まることを示してい
る。したがって、上層の非晶質薄膜に比べてその下の非
晶質薄膜の結晶核の発生密度が段階的または連続的に高
くなるように積層された非晶質薄膜を固相成長させるこ
とにより、６００℃程度の低温の熱処理で、固相による
結晶化時間を短縮でき、かつ電気的に良好な特性をもつ
多結晶薄膜を得ることができる。This is because the generation density of crystal nuclei is determined by the formation condition of the amorphous thin film directly above the glass substrate, and the transistor characteristics are determined by the formation condition of the uppermost amorphous thin film. It is shown that. Therefore, by solid-phase growing an amorphous thin film that is laminated so that the generation density of crystal nuclei in the underlying amorphous thin film is increased stepwise or continuously as compared with the upper amorphous thin film, By heat treatment at a low temperature of about 600 ° C., it is possible to shorten the crystallization time by the solid phase and obtain a polycrystalline thin film having electrically good characteristics.
【００５１】このように、段階的または連続的に堆積温
度条件を順次変化させた場合には、多層構造の非晶質薄
膜は同一材料であるので、上記効果に付け加えて、一連
の成膜工程で行うことができ、製造工程を単純化するこ
とができるという効果を得ることができる。つまり、多
層構造の非晶質薄膜を堆積温度条件を変化させて成膜す
る場合、堆積温度に差が有ればあるほど半導体装置を入
れるチャンバーの温度を冷やす必要があり、その冷却時
間もかかるが、堆積温度に差があまり無いか、または、
堆積温度が一連に変化する場合には、シーケンサーなど
によって温度制御すれば、多層構造の非晶質薄膜の成膜
が一連の製造工程とすることができる。In this way, when the deposition temperature conditions are sequentially changed stepwise or continuously, since the amorphous thin film having the multilayer structure is the same material, in addition to the above effects, a series of film forming steps is performed. It is possible to obtain the effect that the manufacturing process can be simplified. That is, when forming an amorphous thin film having a multi-layer structure by changing the deposition temperature condition, the temperature of the chamber in which the semiconductor device is placed needs to be cooled as the deposition temperature varies, and it takes a cooling time. However, there is not much difference in the deposition temperature, or
When the deposition temperature changes in series, the temperature can be controlled by a sequencer or the like to form a multi-layered amorphous thin film as a series of manufacturing steps.
【００５２】また、本実施例では、絶縁層としてのガラ
ス基板１の表面から結晶核を発生させる場合について示
したが、多層構造の非晶質薄膜の上層に酸化膜や窒化膜
などの絶縁層としての絶縁性膜を形成した後に固相成長
させる場合、多層構造の非晶質薄膜とその上部の絶縁性
膜と界面から結晶核が発生する特性を有していることか
ら、絶縁性膜を非晶質薄膜の上部に設ける場合、結晶核
発生密度の高い膜を多層構造の非晶質薄膜のうち上層膜
とすることにより、本実施例と同様の効果が得られ、逆
スタガー構造の薄膜トランジスタなどに応用することが
できる。Further, in this embodiment, the case where crystal nuclei are generated from the surface of the glass substrate 1 as an insulating layer has been described. When solid phase growth is performed after forming the insulating film as described above, the insulating film has a characteristic that crystal nuclei are generated from the interface between the amorphous thin film having the multilayer structure and the insulating film above it. When it is provided on the amorphous thin film, the same effect as that of the present embodiment can be obtained by forming the film having a high crystal nucleus generation density as the upper layer film of the amorphous thin film having the multilayer structure. It can be applied to
【００５３】例えば、図８に本発明の他の実施例の上記
薄膜トランジスタに用いる多結晶薄膜の製造工程におけ
る断面図を示している。図８に示すように、ガラス基板
２１上の中央部にＴａまたはＡｌからなるゲート電極２
２が設けられ、このゲート電極２２上にＴａ2Ｏ5または
Ａｌ2Ｏ5からなるゲート酸化膜２３が設けられる。この
ゲート酸化膜２３およびガラス基板２１上にＳｉＯ2ま
たはＳｉＮxからなるゲート絶縁膜２４が設けられる。
さらに、ゲート絶縁膜２４上に非晶質薄膜２５を所定堆
積温度条件にて設け、非晶質薄膜２５上に、非晶質薄膜
２５よりも核発生密度の高い堆積温度条件にて非晶質薄
膜２６を設ける。さらに、非晶質薄膜２６上に界面を接
するように、ＳｉＯ2またはＳｉＮxからなる結晶核発生
層としての絶縁層２７が設けられる。この基板部を熱処
理することにより、上記絶縁層２７と非晶質薄膜２６の
界面から固相成長させて非晶質薄膜２６，２５を多結晶
化する。即ち、上下両面に結晶核を発生させる界面が存
在するが、この場合、絶縁層２７と非晶質薄膜２６の界
面における結晶核発生密度が、ゲート絶縁膜２４と非晶
質薄膜２５の界面よりも高くなって優先的に結晶化が進
む。以上によりボトムゲート構成の薄膜トランジスタの
多結晶薄膜が形成されることになる。For example, FIG. 8 shows a sectional view in a manufacturing process of a polycrystalline thin film used for the thin film transistor of another embodiment of the present invention. As shown in FIG. 8, the gate electrode 2 made of Ta or Al is formed in the center of the glass substrate 21.
2 is provided, and a gate oxide film 23 made of Ta 2 O 5 or Al 2 O 5 is provided on the gate electrode 22. A gate insulating film 24 made of SiO 2 or SiN x is provided on the gate oxide film 23 and the glass substrate 21.
Further, an amorphous thin film 25 is provided on the gate insulating film 24 under a predetermined deposition temperature condition, and an amorphous thin film 25 is deposited on the amorphous thin film 25 under a deposition temperature condition in which nucleation density is higher than that of the amorphous thin film 25. A thin film 26 is provided. Further, an insulating layer 27 made of SiO 2 or SiN x as a crystal nucleus generating layer is provided on the amorphous thin film 26 so as to contact the interface. By heat-treating this substrate portion, solid phase growth is performed from the interface between the insulating layer 27 and the amorphous thin film 26 to polycrystallize the amorphous thin films 26 and 25. That is, there are interfaces that generate crystal nuclei on both the upper and lower sides. In this case, the density of crystal nuclei generation at the interface between the insulating layer 27 and the amorphous thin film 26 is higher than that at the interface between the gate insulating film 24 and the amorphous thin film 25. Becomes higher and crystallization preferentially progresses. As described above, a polycrystalline thin film of a bottom gate type thin film transistor is formed.
【００５４】この場合は、図１の実施例におけるガラス
基板１、第１の非晶質薄膜２および第２の非晶質薄膜３
の構成と上下が逆になっているだけであり、結晶核の発
生密度は上層となる非晶質薄膜２６の堆積温度形成条件
により制御し、固相成長後の多結晶薄膜の特性は下層の
非晶質薄膜２５の堆積温度条件により制御する。これに
より、６００℃程度の固相成長の熱処理温度下で目的と
する良好な膜特性を有する多結晶薄膜を短時間で得るこ
とができる。In this case, the glass substrate 1, the first amorphous thin film 2 and the second amorphous thin film 3 in the embodiment of FIG.
However, the generation density of crystal nuclei is controlled by the deposition temperature forming condition of the amorphous thin film 26 which is the upper layer, and the characteristics of the polycrystalline thin film after solid phase growth are the same as those of the lower layer. It is controlled by the deposition temperature condition of the amorphous thin film 25. As a result, a polycrystalline thin film having desired desired film characteristics can be obtained in a short time at a heat treatment temperature of solid phase growth of about 600 ° C.
【００５５】なお、上記各実施例では、上下層の非晶質
薄膜の成膜は、純ジシランガスを原料としてＬＰＣＶＤ
法にて行ったが、プラズマＣＶＤ法、常圧ＡＰＣＶＤ
法、スパッタ法または蒸着電子ビーム法によっても上下
層の非晶質薄膜の成膜をすることができ、また、純ジシ
ランガスの代わりにモノシランガスまたはトリシランガ
スを原料とすることもできる。In each of the above embodiments, the upper and lower amorphous thin films are formed by LPCVD using pure disilane gas as a raw material.
Method, plasma CVD method, atmospheric pressure APCVD
The upper and lower amorphous thin films can be formed by a sputtering method, a sputtering method, or a vapor deposition electron beam method, and monosilane gas or trisilane gas can be used as a raw material instead of pure disilane gas.
【００５６】また、上記各実施例では、多結晶薄膜
２’，３’をトランジスタのチャネル、ソースＳおよび
ドレインＤなどのチャネル部として用いたが、半導体装
置における抵抗体およびフローティングゲート部（キャ
パシタ電極）などとして用いることも可能である。Further, in each of the above embodiments, the polycrystalline thin films 2'and 3'are used as the channel portion of the transistor and the channel portion such as the source S and the drain D. However, the resistor and floating gate portion (capacitor electrode) in the semiconductor device are used. ) And the like.
【００５７】さらに、上記各実施例では、絶縁層に接す
る側の非晶質薄膜における結晶核発生密度の制御は、こ
の非晶質薄膜の堆積温度および成膜圧力のいずれかによ
り行ったが、堆積温度および成膜圧力を同時に制御して
所定の結晶核発生密度としてもよい。また、この結晶核
発生密度の制御は、絶縁層に接する側の非晶質薄膜の堆
積温度および成膜圧力のいずれかにより行ったが、堆積
温度および成膜圧力の他に原料ガス流量やプラズマ電力
などを可変することにより行うことができる。Further, in each of the above-mentioned examples, the control of the crystal nucleus generation density in the amorphous thin film on the side in contact with the insulating layer was performed by either the deposition temperature or the film forming pressure of this amorphous thin film. The deposition temperature and the film formation pressure may be controlled simultaneously to obtain a predetermined crystal nucleus generation density. The crystal nucleus generation density was controlled by either the deposition temperature or the deposition pressure of the amorphous thin film on the side in contact with the insulating layer. It can be performed by changing the electric power.
【００５８】[0058]
【発明の効果】以上のように本発明によれば、第２の非
晶質薄膜に比べて結晶核の発生密度が高い第１の非晶質
薄膜と第２の非晶質薄膜を界面が接するように設け、か
つ絶縁層と界面が接する第１の非晶質薄膜を設け、この
第１の非晶質薄膜を出発材料として固相成長させること
により、低い熱処理温度下であっても電気的に良好な多
結晶薄膜の特性を維持しつつ、固相による結晶化時間を
短縮することができる。As described above, according to the present invention, the interface between the first amorphous thin film and the second amorphous thin film, which has a higher generation density of crystal nuclei than the second amorphous thin film, is formed. By providing a first amorphous thin film that is provided so as to be in contact with the insulating layer and has an interface in contact with the insulating layer, and solid-phase growth is performed using this first amorphous thin film as a starting material, it is possible to obtain electrical conductivity even at a low heat treatment temperature. It is possible to shorten the crystallization time by the solid phase while maintaining the characteristics of the polycrystalline thin film which is excellent in view of the solid phase.
【００５９】これら非晶質薄膜は同一の非晶質材料であ
るため、成膜条件だけを変えて一連の工程で簡便に行う
ことができ。Since these amorphous thin films are made of the same amorphous material, they can be easily formed in a series of steps by changing only the film forming conditions.
【００６０】さらに、これら多結晶薄膜が多結晶シリコ
ン膜であれば、上記効果を容易に確実に得ることができ
る。Furthermore, if these polycrystalline thin films are polycrystalline silicon films, the above effects can be easily and reliably obtained.
【００６１】さらに、安価なガラス基板を用いることが
できる６００℃程度の低温度で処理可能であるので、ガ
ラス基板の変質および変形なく行うことができる。Furthermore, since it is possible to process at a low temperature of about 600 ° C., which allows the use of an inexpensive glass substrate, it is possible to carry out without alteration or deformation of the glass substrate.
【００６２】さらに、上記多結晶薄膜をトランジスタの
チャネル部に用いると、低温度処理の下、移動度や閾値
電圧などのトランジスタ特性を維持しつつ、固相成長時
間を短縮することができる。Furthermore, when the above-mentioned polycrystalline thin film is used for the channel portion of a transistor, the solid phase growth time can be shortened while maintaining transistor characteristics such as mobility and threshold voltage under low temperature treatment.
【００６３】さらに、絶縁層と接する側の非晶質薄膜の
堆積温度を５００〜５７０℃に設定し、多結晶化させる
温度を５８０℃〜６４０℃に設定すれば、低温度処理の
下、固相成長時間の短縮、および多結晶薄膜の特性をよ
り良好なものとすることができる。Further, if the deposition temperature of the amorphous thin film on the side in contact with the insulating layer is set to 500 to 570 ° C. and the temperature for polycrystallization is set to 580 ° C. to 640 ° C., it will be solidified under low temperature treatment. The phase growth time can be shortened and the characteristics of the polycrystalline thin film can be improved.
【図１】本発明の一実施例を示す半導体装置の多結晶膜
製造工程における一部断面図である。FIG. 1 is a partial cross-sectional view in a manufacturing process of a polycrystalline film of a semiconductor device showing an embodiment of the present invention.
【図２】図１の多結晶薄膜を用いたトランジスタ製造工
程における一部断面図である。2 is a partial cross-sectional view in a transistor manufacturing process using the polycrystalline thin film of FIG.
【図３】図１における２層構造膜の熱処理時間に対する
結晶化の割合の変化を示すグラフである。FIG. 3 is a graph showing changes in the crystallization rate with respect to the heat treatment time of the two-layer structure film in FIG.
【図４】図１の下層の非晶質薄膜２の堆積温度と結晶粒
径との関係を示すグラフである。FIG. 4 is a graph showing the relationship between the deposition temperature and the crystal grain size of the lower amorphous thin film 2 of FIG.
【図５】図１の下層の非晶質薄膜２の堆積温度とトラン
ジスタ特性としてのＮチャネル移動度との関係を示すグ
ラフである。5 is a graph showing the relationship between the deposition temperature of the lower amorphous thin film 2 in FIG. 1 and N-channel mobility as a transistor characteristic.
【図６】結晶核発生速度と結晶粒成長速度の成膜圧力依
存性を示すグラフである。FIG. 6 is a graph showing the dependency of the crystal nucleus generation rate and the crystal grain growth rate on the film formation pressure.
【図７】結晶粒径の成膜圧力依存性を示すグラフであ
る。FIG. 7 is a graph showing the dependency of crystal grain size on film forming pressure.
【図８】本発明の他の実施例を示す薄膜トランジスタに
用いる多結晶薄膜の製造工程における断面図である。FIG. 8 is a cross-sectional view in a manufacturing process of a polycrystalline thin film used for a thin film transistor showing another embodiment of the present invention.
１ 絶縁性基板 ２，３，２５，２６ 非晶質薄膜 ２’，３’ 多結晶薄膜 ９ 薄膜トランジスタ ２７ 結晶核発生層 1 Insulating Substrate 2, 3, 25, 26 Amorphous Thin Film 2 ', 3'Polycrystalline Thin Film 9 Thin Film Transistor 27 Crystal Nucleation Layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/336 (72)発明者 大野 栄三 大阪府大阪市阿倍野区長池町22番22号 シ ャープ株式会社内─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 6 Identification number Internal reference number FI Technical indication location H01L 21/336 (72) Inventor Eizo Ohno 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Prefecture Sharp Shares In the company
Claims (7)
膜に比べて結晶核の発生密度の高い該第１の薄膜と第２
の薄膜がそれぞれ界面を接するように設けられ、かつ該
第１の薄膜および第２の薄膜が非晶質から多結晶化され
ている半導体装置の多結晶薄膜。1. An insulating layer and a first thin film, and the first thin film and the second thin film having a higher generation density of crystal nuclei than the second thin film.
Of the semiconductor device, wherein the first thin film and the second thin film are polycrystallized from amorphous to polycrystal.
材料の非晶質から多結晶化されている請求項１記載の半
導体装置の多結晶薄膜。2. The polycrystalline thin film of a semiconductor device according to claim 1, wherein the first thin film and the second thin film are polycrystallized from amorphous of the same material.
び第２の薄膜は多結晶シリコン膜で構成されている請求
項１記載の半導体装置の多結晶薄膜。3. The polycrystalline thin film of a semiconductor device according to claim 1, wherein the first thin film and the second thin film which are polycrystallized are composed of a polycrystalline silicon film.
ランジスタのチャネル部を構成している請求項１記載の
半導体装置の多結晶薄膜。4. The polycrystalline thin film of a semiconductor device according to claim 1, wherein the polycrystalline thin film which is polycrystallized constitutes a channel portion of a transistor.
２の非晶質薄膜に比べて結晶核の発生密度の高い第１の
非晶質薄膜と該第２の非晶質薄膜がそれぞれ界面を接す
るように堆積し、少なくとも該第１の非晶質薄膜および
第２の非晶質薄膜にエネルギーを加えて多結晶化させて
多結晶薄膜とする半導体装置の多結晶薄膜製造方法。5. An insulating layer and a first amorphous thin film, and a first amorphous thin film having a higher generation density of crystal nuclei than the second amorphous thin film and the second amorphous thin film. Polycrystalline thin film manufacturing of semiconductor device in which thin films are deposited so that their interfaces are in contact with each other, and at least the first amorphous thin film and the second amorphous thin film are polycrystallized by applying energy to form a polycrystalline thin film Method.
発生密度は、該第１の非晶質薄膜の堆積温度、成膜圧
力、原料ガス流量およびプラズマ電力のうち少なくとも
いずれかにより制御される請求項５記載の半導体装置の
多結晶薄膜製造方法。6. The generation density of crystal nuclei in the first amorphous thin film is controlled by at least one of the deposition temperature of the first amorphous thin film, the film forming pressure, the raw material gas flow rate, and the plasma power. The method for producing a polycrystalline thin film of a semiconductor device according to claim 5, wherein
０〜５７０℃に設定し、前記多結晶化させる温度を５８
０℃〜６４０℃に設定する請求項５記載の半導体装置の
多結晶薄膜製造方法。7. The deposition temperature of the first amorphous thin film is set to 50.
The temperature for polycrystallization is set to 0 to 570 ° C.
The method for producing a polycrystalline thin film of a semiconductor device according to claim 5, wherein the temperature is set to 0 ° C to 640 ° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15117094A JPH0817730A (en) | 1994-07-01 | 1994-07-01 | Polycrystal thin film of semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15117094A JPH0817730A (en) | 1994-07-01 | 1994-07-01 | Polycrystal thin film of semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0817730A true JPH0817730A (en) | 1996-01-19 |
Family
ID=15512851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15117094A Withdrawn JPH0817730A (en) | 1994-07-01 | 1994-07-01 | Polycrystal thin film of semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0817730A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006528427A (en) * | 2003-07-18 | 2006-12-14 | コーニング インコーポレイテッド | Silicon crystallization using self-assembled monolayers |
| WO2011142443A1 (en) * | 2010-05-14 | 2011-11-17 | Semiconductor Energy Laboratory Co., Ltd. | Microcrystalline silicon film, manufacturing method thereof, semiconductor device, and manufacturing method thereof |
-
1994
- 1994-07-01 JP JP15117094A patent/JPH0817730A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006528427A (en) * | 2003-07-18 | 2006-12-14 | コーニング インコーポレイテッド | Silicon crystallization using self-assembled monolayers |
| WO2011142443A1 (en) * | 2010-05-14 | 2011-11-17 | Semiconductor Energy Laboratory Co., Ltd. | Microcrystalline silicon film, manufacturing method thereof, semiconductor device, and manufacturing method thereof |
| US8884297B2 (en) | 2010-05-14 | 2014-11-11 | Semiconductor Energy Laboratory Co., Ltd. | Microcrystalline silicon film, manufacturing method thereof, semiconductor device, and manufacturing method thereof |
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