JPH08125023A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH08125023A JPH08125023A JP26582294A JP26582294A JPH08125023A JP H08125023 A JPH08125023 A JP H08125023A JP 26582294 A JP26582294 A JP 26582294A JP 26582294 A JP26582294 A JP 26582294A JP H08125023 A JPH08125023 A JP H08125023A
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- Japan
- Prior art keywords
- fuse
- film
- thickness
- layer
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置の製造方法
に係り、特にレーザによる溶断を行って使用するフュー
ズを配した半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a fuse to be used after being fused by a laser.
【０００２】[0002]
【従来の技術】多層配線層を有する半導体装置、特に半
導体記憶装置（メモリ）において、不良回路が発生した
場合に、予め冗長回路として形成されたフューズを切断
して不良回路に置き換えて使用される。2. Description of the Related Art When a defective circuit occurs in a semiconductor device having a multi-layered wiring layer, especially in a semiconductor memory device (memory), a fuse previously formed as a redundant circuit is cut and used as a defective circuit. .
【０００３】多層配線における第１層目としてのＰｏｌ
ｙ−Ｓｉ配線層と第２層目としての例えばＡｌ配線層を
有する半導体装置で、第１層Ｐｏｌｙ−Ｓｉ配線層によ
りフューズ（Ｆｕｓｅ）素子を形成する場合を例にと
り、図５および図６に示した従来例を説明する。Pol as the first layer in multilayer wiring
5 and 6 show a semiconductor device having a y-Si wiring layer and, for example, an Al wiring layer as the second layer, in which a fuse element is formed by the first-layer Poly-Si wiring layer. The conventional example shown will be described.
【０００４】まず、図５（ａ）に示したように、ｎ型シ
リコン（Ｓｉ）基板１上に熱酸化により厚さ４００ｎｍ
のＳｉＯ2からなるフィールド酸化膜３を形成し、その
上に１層目の配線の厚さ２００ｎｍのＰｏｌｙ−Ｓｉ配
線層５を形成する。First, as shown in FIG. 5A, a thickness of 400 nm is formed on an n-type silicon (Si) substrate 1 by thermal oxidation.
The field oxide film 3 made of SiO 2 is formed, and the Poly-Si wiring layer 5 having a thickness of 200 nm of the first wiring is formed thereon.
【０００５】次に、図５（ｂ）に示すように、Ｐｏｌｙ
−Ｓｉ配線層５上に層間絶縁膜として厚さ４００ｎｍの
ＢＰＳＧ膜６を堆積し、９００℃の温度で２０分間熱処
理を施してＢＰＳＧ膜６の表面を平滑化する。その後、
２層目の配線の厚さ５００ｎｍのＡｌ配線層７を形成す
る。Next, as shown in FIG.
A 400 nm-thick BPSG film 6 is deposited on the -Si wiring layer 5 as an interlayer insulating film, and a heat treatment is performed at a temperature of 900 ° C. for 20 minutes to smooth the surface of the BPSG film 6. afterwards,
An Al wiring layer 7 having a thickness of 500 nm of the second layer wiring is formed.
【０００６】その後、図５（ｃ）に示すように、得られ
たウェハ全面に厚さ４００ｎｍのＰ（プラズマ）−ＴＥ
ＯＳ（テトラエチルオルソシラン）膜８を形成し、その
上方から更に厚さ６００ｎｍの有機ＳＯＧ（シリコンオ
ングラス）をコーティングし、エッチバックすることに
よってＳＯＧ膜９を形成してＡｌ配線層７による段差を
平坦化する。Thereafter, as shown in FIG. 5C, a P (plasma) -TE film having a thickness of 400 nm is formed on the entire surface of the obtained wafer.
An OS (tetraethylorthosilane) film 8 is formed, an organic SOG (silicon on glass) having a thickness of 600 nm is further coated from above, and an SOG film 9 is formed by etching back to form a step due to the Al wiring layer 7. Flatten.
【０００７】次に、図６（ａ）に示すように、得られた
ウェハ全面に厚さ３００ｎｍのＰ−ＴＥＯＳ膜１０を形
成し、厚さ８００ｎｍのＡｌ配線層１２を形成する。Next, as shown in FIG. 6A, a P-TEOS film 10 having a thickness of 300 nm is formed on the entire surface of the obtained wafer, and an Al wiring layer 12 having a thickness of 800 nm is formed.
【０００８】次に、図６（ｂ）に示すように、オーバコ
ート膜として厚さ４００ｎｍのＰ−ＳｉＮ膜１４を堆
積、形成した後、フューズ部１５の窓開けを行う。この
ような状態でレーザがフューズとしてのＰｏｌｙ−Ｓｉ
配線層５に当てられ溶断される。Next, as shown in FIG. 6B, a P-SiN film 14 having a thickness of 400 nm is deposited and formed as an overcoat film, and then the fuse portion 15 is opened. In such a state, the laser is a Poly-Si as a fuse.
The wiring layer 5 is applied and blown.
【０００９】最後に、図６（ｃ）に示すように、最終の
オーバコート膜としてＰ−ＳｉＮ膜１７を形成した後、
パッド部の窓開けを行う。このＰ−ＳｉＮ膜１７によっ
てフューズ上部は蓋をされて、その部位からの汚染が抑
制される。Finally, as shown in FIG. 6C, after a P-SiN film 17 is formed as a final overcoat film,
Open the pad window. The P-SiN film 17 covers the upper part of the fuse to suppress contamination from that part.
【００１０】このようにして第１層Ｐｏｌｙ−Ｓｉ層５
をフューズとする多層配線層が得られる。Thus, the first layer Poly-Si layer 5 is formed.
A multi-layered wiring layer having a fuse as a fuse is obtained.
【００１１】[0011]
【発明が解決しようとする課題】ところで、上述のフュ
ーズを有する多層配線層の形成では、Ａｌ配線層７によ
る段差を平坦化するための平坦化プロセスにおける膜
厚、特にＰ−ＴＥＯＳ膜８の膜厚のばらつきとエッチバ
ックのばらつきによって最終的に層間膜厚において大き
なばらつきを生じる場合があった。By the way, in the formation of the above-mentioned multi-layered wiring layer having the fuse, the film thickness in the flattening process for flattening the step due to the Al wiring layer 7, especially the film of the P-TEOS film 8 is formed. In some cases, a large variation in the interlayer film thickness may occur eventually due to the variation in thickness and the variation in etchback.
【００１２】その場合、膜厚がばらついた層間膜を通し
てフューズ溶断のためのレーザ照射がなされる。従っ
て、照射量のばらつきも膜厚のばらつきに対応して大き
くなり、照射量が最適値よりも大きい方にばらつくとフ
ューズの下地にまでフューズ溶断時のダメージが与えら
れてフューズ部と下地Ｓｉとの間でリーク電流が発生し
たり、逆に照射量が最適値よりも小さい方にばらつくと
所定のフューズが溶断されないという問題があった。In that case, laser irradiation for fusing the fuse is performed through an interlayer film having a varied thickness. Therefore, the variation of the irradiation amount also increases corresponding to the variation of the film thickness, and when the irradiation amount varies to a larger value than the optimum value, the base of the fuse is damaged when the fuse is blown, and the fuse portion and the base Si are separated. There is a problem that a predetermined fuse will not be blown if a leak current is generated between them, or conversely, if the irradiation amount is smaller than the optimum value.
【００１３】そこでこの発明は上述の課題を考慮して、
フューズ上部の層間絶縁膜の膜厚がばらついても安定し
てフューズを溶断できる半導体装置の製造方法を提供す
ることを目的とする。Therefore, the present invention has been made in consideration of the above problems.
An object of the present invention is to provide a method of manufacturing a semiconductor device, which can stably blow out the fuse even if the film thickness of the interlayer insulating film above the fuse varies.
【００１４】[0014]
【課題を解決するための手段】上述の課題を解決するた
めに本発明の請求項１においては、半導体記憶装置のフ
ューズを形成する方法であって、フューズを所定部位に
第１配線層により形成した後、フューズ上方にエッチン
グストッパ層を形成し、エッチングストッパ層上に形成
された層間絶縁膜とエッチングストッパ層を順次除去す
る工程を有することを特徴とする。In order to solve the above-mentioned problems, according to a first aspect of the present invention, there is provided a method of forming a fuse of a semiconductor memory device, wherein the fuse is formed at a predetermined portion by a first wiring layer. After that, an etching stopper layer is formed above the fuse, and the interlayer insulating film and the etching stopper layer formed on the etching stopper layer are sequentially removed.
【００１５】また、本発明の請求項２によれば請求項１
において、エッチングストッパ層は、フューズ上方の第
２配線層と同一材料からなり、第２配線層形成時に形成
されることを特徴とする。According to claim 2 of the present invention, claim 1
In the above, the etching stopper layer is made of the same material as the second wiring layer above the fuse, and is formed when the second wiring layer is formed.
【００１６】[0016]
【作用】本発明によれば、フューズ５上方の膜厚がばら
つく層間絶縁膜を、層間絶縁膜下にエッチングストッパ
層７ａを設けることにより、エッチング除去し、その後
にエッチングストッパ層７ａが除去される。そのような
状態でフューズ５にレーザが照射されるため層間膜厚の
ばらつきの影響を受けず、安定なフューズ溶断が可能と
なる。According to the present invention, the interlayer insulating film having a variable film thickness above the fuse 5 is removed by etching by providing the etching stopper layer 7a under the interlayer insulating film, and then the etching stopper layer 7a is removed. . Since the fuse 5 is irradiated with the laser in such a state, it is possible to stably fuse the fuse without being affected by the variation in the interlayer film thickness.
【００１７】また、本発明ではエッチングストッパ層と
して第２層目の配線材料が用いられるため工程数の増加
もない。Further, in the present invention, since the second layer wiring material is used as the etching stopper layer, the number of steps is not increased.
【００１８】[0018]
【実施例】以下、本発明の実施例を図面に基づいて詳細
に説明する。図１及び図２は本発明の半導体装置、特に
欠陥回路の置き換え用フューズを配した半導体記憶装置
の製造方法の第１実施例を示す工程断面図である。Embodiments of the present invention will be described below in detail with reference to the drawings. 1 and 2 are process cross-sectional views showing a first embodiment of a method of manufacturing a semiconductor device of the present invention, particularly a semiconductor memory device having a defective circuit replacement fuse.
【００１９】本例も従来例と同様に１層配線のＰｏｌｙ
−Ｓｉ配線層にフューズ素子を形成する場合を示す。ま
た、本第１実施例ではエッチングストッパ層として２層
目配線としての第１のＡｌ配線層を用いた。In this example as well, as in the conventional example, a single-layer wiring poly
A case where a fuse element is formed on a -Si wiring layer is shown. Further, in the first embodiment, the first Al wiring layer as the second wiring layer is used as the etching stopper layer.
【００２０】まず、図１（ａ）に示すように、従来と同
様にｎ型シリコン（Ｓｉ）基板１上に厚さ４００ｎｍの
フィールド酸化膜３を形成し、その上に１層目の厚さ２
００ｎｍのＰｏｌｙ−Ｓｉ配線層５を形成する。First, as shown in FIG. 1A, a field oxide film 3 having a thickness of 400 nm is formed on an n-type silicon (Si) substrate 1 as in the conventional case, and the thickness of the first layer is formed thereon. Two
A 00 nm Poly-Si wiring layer 5 is formed.
【００２１】次に、図１（ｂ）に示すように、Ｐｏｌｙ
−Ｓｉ配線層５上に層間絶縁膜として厚さ４００ｎｍの
ＢＰＳＧ膜６を堆積形成し、９００℃の温度で２０分間
熱処理を施してＢＰＳＧ膜６の表面を平滑化する。その
後、２層目配線として厚さ５００ｎｍのＡｌ配線層７を
形成する。この工程ではフューズ上部にもＡｌ配線層７
と同一の材料でＡｌパターン（７ａ）を配してエッチン
グストッパ用の金属層を形成する。Next, as shown in FIG.
A 400 nm-thick BPSG film 6 is deposited and formed on the -Si wiring layer 5 as an interlayer insulating film, and heat treatment is performed at a temperature of 900 ° C. for 20 minutes to smooth the surface of the BPSG film 6. After that, an Al wiring layer 7 having a thickness of 500 nm is formed as the second layer wiring. In this process, the Al wiring layer 7 is also formed on the fuse.
An Al pattern (7a) is arranged with the same material as the above to form a metal layer for an etching stopper.
【００２２】その後、図１（ｃ）に示すように、得られ
たウェハ全面に厚さ４００ｎｍのＰ（プラズマ）−ＴＥ
ＯＳ（テトラエチルオルソシラン）膜８を形成し、その
上方から更に厚さ６００ｎｍの有機ＳＯＧ（シリコンオ
ングラス）をコーティングし、エッチバックすることに
よってＳＯＧ膜９を形成してＡｌ配線層７による段差を
平坦化する。Then, as shown in FIG. 1C, P (plasma) -TE having a thickness of 400 nm is formed on the entire surface of the obtained wafer.
An OS (tetraethylorthosilane) film 8 is formed, an organic SOG (silicon on glass) having a thickness of 600 nm is further coated from above, and an SOG film 9 is formed by etching back to form a step due to the Al wiring layer 7. Flatten.
【００２３】次に、図２（ａ）に示すように、得られた
ウェハ全面に厚さ３００ｎｍのＰ−ＴＥＯＳ膜１０を形
成し、更にその上に２層目配線の厚さ８００ｎｍのＡｌ
配線層１２を形成する。Next, as shown in FIG. 2A, a P-TEOS film 10 having a thickness of 300 nm is formed on the entire surface of the obtained wafer, and an Al layer having a thickness of 800 nm for the second layer wiring is further formed thereon.
The wiring layer 12 is formed.
【００２４】次に、オーバコート膜として厚さ４００ｎ
ｍのＰ−ＳｉＮ膜１４を堆積、形成した後、フューズ部
１５の窓開けを行う。この窓開け工程では、まず図２
（ｂ）に示すように、Ｐ−ＳｉＮ膜１４とＰ−ＴＥＯＳ
間１０の層間膜を全て除去する。この際、適当なオーバ
エッチを加えれば、Ｐ−ＳｉＮ膜１４とＰ−ＴＥＯＳ間
１０の層間膜の膜厚がばらついたとしてもフューズ上部
の層間膜１０はエッチングされ、確実にＡｌパターン７
ａ表面でエッチングストップされる。この時のエッチン
グ条件はエッチングストッパ層（Ａｌ）に対して選択比
のあるエッチング条件とする。Next, an overcoat film having a thickness of 400 n
After depositing and forming the P-SiN film 14 of m, the window of the fuse portion 15 is opened. In this window opening process, first, as shown in FIG.
As shown in (b), P-SiN film 14 and P-TEOS
The interlayer film in the space 10 is entirely removed. At this time, if appropriate over-etching is applied, even if the film thickness of the interlayer film between the P-SiN film 14 and the P-TEOS 10 varies, the interlayer film 10 above the fuse is etched and the Al pattern 7 is surely formed.
Etching is stopped at the surface a. The etching conditions at this time are such that the etching stopper layer (Al) has a selective ratio.
【００２５】その後、他のエッチング条件でＡｌエッチ
ングを行い、フューズ上のＡｌパターン７ａを除去す
る。フューズとしてのＰｏｌｙ−Ｓｉ配線層５上にＢＰ
ＳＧ膜６を配した状態でレーザを用いてフューズのブロ
ウ（Ｂｌｏｗ）を行い、所定部位を溶断する。次に、最
終のオーバコート膜として厚さ５００ｎｍのＰ−ＳｉＮ
膜１７を堆積形成後（図２（ｃ））、パッド部の窓開け
を行う。最終のオーバコート膜Ｐ−ＳｉＮ膜１７によっ
てフューズ上部は蓋をされて、その部位からの汚染が抑
制される。After that, Al etching is performed under other etching conditions to remove the Al pattern 7a on the fuse. BP on the Poly-Si wiring layer 5 as a fuse
The blow of the fuse is performed by using a laser with the SG film 6 arranged, and the predetermined portion is melted. Next, as a final overcoat film, P-SiN having a thickness of 500 nm is formed.
After depositing and forming the film 17 (FIG. 2C), the window of the pad portion is opened. The final overcoat film P-SiN film 17 covers the upper part of the fuse to suppress contamination from that part.
【００２６】このようにして形成されたフューズ部１５
上方では、膜厚がばらつくＰ−ＴＥＯＳ膜１０が除去さ
れた状態でレーザによるフューズの溶断がなされるた
め、フューズ部１５上方の層間絶縁膜がばらついても安
定したフューズ（Ｐｏｌｙ−Ｓｉ配線層５）の溶断を行
うことができる。The fuse portion 15 thus formed
Since the fuse is blown by the laser above the P-TEOS film 10 of which the film thickness varies, the fuse (poly-Si wiring layer 5) is stable even if the interlayer insulating film above the fuse portion 15 varies. ) Melting can be performed.
【００２７】次に、本発明の第２実施例を図３及び図４
に示した工程断面図に基づいて説明する。Next, a second embodiment of the present invention will be described with reference to FIGS.
It will be described based on the process cross-sectional views shown in FIG.
【００２８】本例も従来例と同様に１層配線のＰｏｌｙ
−Ｓｉ配線層にフューズ素子を形成する場合を示す。ま
た本第２実施例ではエッチングストッパ層として第２の
Ｐｏｌｙ−Ｓｉ配線層を用いた。In this example as well, as in the conventional example, a single-layer wiring poly
A case where a fuse element is formed on a -Si wiring layer is shown. In the second embodiment, the second Poly-Si wiring layer is used as the etching stopper layer.
【００２９】まず、図３（ａ）に示すように、第１実施
例と同様にｎ型シリコン（Ｓｉ）基板１上に厚さ４００
ｎｍのフィールド酸化膜３を形成し、その上に１層目の
厚さ２００ｎｍのＰｏｌｙ−Ｓｉ配線層５を形成する。First, as shown in FIG. 3A, the thickness 400 is formed on the n-type silicon (Si) substrate 1 as in the first embodiment.
The field oxide film 3 having a thickness of 10 nm is formed, and the first layer of the Poly-Si wiring layer 5 having a thickness of 200 nm is formed thereon.
【００３０】次に、図３（ｂ）に示すように、Ｐｏｌｙ
−Ｓｉ配線層５上に層間絶縁膜として厚さ２００ｎｍの
ＳｉＯ2膜３ａを形成した後、２層目の厚さ１００ｎｍ
のＰｏｌｙ−Ｓｉ配線層（図示せず）を形成する。この
時、エッチングストッパ用のＰｏｌｙ−Ｓｉパターン５
ａをフューズ上部に形成する。Next, as shown in FIG.
After forming a 200 nm thick SiO 2 film 3a as an interlayer insulating film on the Si wiring layer 5, the second layer has a thickness of 100 nm.
Poly-Si wiring layer (not shown) is formed. At this time, the Poly-Si pattern 5 for the etching stopper is used.
a is formed on the upper part of the fuse.
【００３１】次に、図３（ｃ）に示すように、ウェハ全
面に層間絶縁膜としての厚さ４００ｎｍのＢＰＳＧ膜６
を堆積形成し、９００℃の温度で２０分間熱処理を施し
てＢＰＳＧ膜６の表面を平滑化する。その後、厚さ５０
０ｎｍのＡｌ配線層７ａを形成する。Next, as shown in FIG. 3C, a BPSG film 6 having a thickness of 400 nm as an interlayer insulating film is formed on the entire surface of the wafer.
Are deposited and heat-treated at a temperature of 900 ° C. for 20 minutes to smooth the surface of the BPSG film 6. Then the thickness 50
An Al wiring layer 7a of 0 nm is formed.
【００３２】その後、図４（ａ）に示すように、得られ
たウェハ全面に厚さ４００ｎｍのＰ（プラズマ）−ＴＥ
ＯＳ（テトラエチルオルソシラン）膜８を形成し、その
上方から更に厚さ６００ｎｍの有機ＳＯＧ（シリコンオ
ングラス）をコーティングし、エッチバックすることに
よってＳＯＧ膜９を形成してＡｌ配線層７ａによる段差
を平坦化する。その後、得られたウェハ全面に厚さ３０
０ｎｍのＰ−ＴＥＯＳ膜１０を形成し、厚さ８００ｎｍ
のＡｌ配線層１２を形成する。After that, as shown in FIG. 4A, P (plasma) -TE having a thickness of 400 nm is formed on the entire surface of the obtained wafer.
An OS (tetraethylorthosilane) film 8 is formed, organic SOG (silicon on glass) having a thickness of 600 nm is further coated from above, and an SOG film 9 is formed by etching back to form a step due to the Al wiring layer 7a. Flatten. After that, a thickness of 30 is obtained on the entire surface of the obtained wafer.
The P-TEOS film 10 having a thickness of 0 nm is formed, and the thickness is 800 nm.
The Al wiring layer 12 is formed.
【００３３】次に、オーバコート膜として厚さ４００ｎ
ｍのＰ−ＳｉＮ膜１４を堆積、形成した後、フューズ部
１５の窓開けを行う。この窓開け工程では、まず図４
（ｂ）に示すようにＰ−ＳｉＮ膜４とＰ−ＴＥＯＳ間１
０の層間膜及びＢＰＳＧ膜６を全て除去する。この際、
Ｐｏｌｙ−Ｓｉに対して１０程度以上の選択比のある条
件で適当なオーバエッチを加えれば、Ｐ−ＳｉＮ膜１４
とＰ−ＴＥＯＳ間１０の層間膜及びＢＰＳＧ膜６の膜厚
がばらついたとしてもフューズ上部の層間膜１０，１４
及びＢＰＳＧ膜６がエッチングされ、確実にＰｏｌｙ−
Ｓｉパターン５ａ表面でエッチングストップされる。Next, an overcoat film having a thickness of 400 n is formed.
After depositing and forming the P-SiN film 14 of m, the window of the fuse portion 15 is opened. In this window opening process, first, as shown in FIG.
As shown in (b), between the P-SiN film 4 and P-TEOS 1
The interlayer film of 0 and the BPSG film 6 are all removed. On this occasion,
If an appropriate overetch is applied under the condition that the selection ratio of Poly-Si is about 10 or more, the P-SiN film 14 is formed.
Even if the film thickness of the BPSG film 6 and the interlayer film between the P-TEOS 10 and the P-TEOS 10 varies, the interlayer films 10 and 14 above the fuses
And the BPSG film 6 is etched and surely Poly-
Etching is stopped at the surface of the Si pattern 5a.
【００３４】その後、他のエッチング条件でＰｏｌｙ−
Ｓｉエッチングを行い、フューズ上のＰｏｌｙ−Ｓｉパ
ターン５ａを除去する。フューズとしてのＰｏｌｙ−Ｓ
ｉ配線層５上にＢＰＳＧ膜６を配した状態でレーザを用
いてフューズのブロウ（Ｂｌｏｗ）を行い、所定部位を
溶断する。Then, under other etching conditions, Poly-
Si etching is performed to remove the Poly-Si pattern 5a on the fuse. Poly-S as a fuse
With the BPSG film 6 disposed on the i wiring layer 5, the fuse is blown using a laser to blow a predetermined portion.
【００３５】次に、最終のオーバコート膜として厚さ５
００ｎｍのＰ−ＳｉＮ膜１７を堆積形成後、パッド部の
窓開けを行う。最終のオーバコート膜Ｐ−ＳｉＮ膜１７
によってフューズ上部は蓋をされて、その部位からの汚
染が抑制される。Next, a final overcoat film having a thickness of 5 is formed.
After the P-SiN film 17 of 00 nm is deposited and formed, the window of the pad portion is opened. Final overcoat film P-SiN film 17
As a result, the upper part of the fuse is covered and the contamination from the part is suppressed.
【００３６】このように、本第２実施例においても上述
の第１実施例と同様にフューズ部１５上方の層間絶縁膜
がばらついても安定したフューズ（Ｐｏｌｙ−Ｓｉ配線
層５）の溶断を行うことができる。In this way, in the second embodiment as well, similar to the first embodiment described above, stable fusing of the fuse (Poly-Si wiring layer 5) is performed even if the interlayer insulating film above the fuse portion 15 varies. be able to.
【００３７】[0037]
【発明の効果】以上説明したように本発明によれば、フ
ューズ上の厚さがばらつく層間絶縁膜を取り除いた状態
でレーザを照射することができるため照射量のばらつき
が抑制され、安定した所定部位のフューズの溶断を行う
ことができる。As described above, according to the present invention, it is possible to irradiate the laser in a state where the interlayer insulating film having a variable thickness on the fuse is removed, so that the variation of the irradiation amount is suppressed and the stable predetermined value is obtained. The fuse of the part can be blown out.
【図１】本発明の半導体装置の製造方法の第１実施例を
示す工程断面図（Ｉ）である。FIG. 1 is a process sectional view (I) showing a first embodiment of a method for manufacturing a semiconductor device of the present invention.
【図２】本発明の半導体装置の製造方法の第１実施例を
示す工程断面図（II）である。FIG. 2 is a process sectional view (II) showing the first embodiment of the method for manufacturing a semiconductor device of the present invention.
【図３】本発明の半導体装置の製造方法の第２実施例を
示す工程断面図（Ｉ）である。FIG. 3 is a process sectional view (I) showing a second embodiment of the method for manufacturing a semiconductor device of the present invention.
【図４】本発明の半導体装置の製造方法の第２実施例を
示す工程断面図（II）である。FIG. 4 is a process sectional view (II) showing a second embodiment of the method for manufacturing a semiconductor device of the present invention.
【図５】従来法を説明するための工程断面図（Ｉ）であ
る。FIG. 5 is a process sectional view (I) for explaining the conventional method.
【図６】従来法を説明するための工程断面図（II）であ
る。FIG. 6 is a process sectional view (II) for explaining the conventional method.
１ ｎ型シリコン基板 ３ フィールド酸化膜 ５ Ｐｏｌｙ−Ｓｉ配線層（フューズ） ５ａ Ｐｏｌｙ−Ｓｉパターン ６ ＢＰＳＧ膜 ７，１２ Ａｌ配線層 ７ａ Ａｌパターン ８ Ｐ−ＴＥＯＳ膜 ９ ＳＯＧ膜 １０ Ｐ−ＴＥＯＳ膜 １４，１７ Ｐ−ＳｉＮ膜 １５ フューズ部 1 n-type silicon substrate 3 field oxide film 5 Poly-Si wiring layer (fuse) 5a Poly-Si pattern 6 BPSG film 7, 12 Al wiring layer 7a Al pattern 8 P-TEOS film 9 SOG film 10 P-TEOS film 14, 17 P-SiN film 15 Fuse part
Claims (2)
法であって、 上記フューズを所定部位に第１配線層により形成した
後、該フューズ上方にエッチングストッパ層を形成し、
上記エッチングストッパ層上に形成された層間絶縁膜と
上記エッチングストッパ層を順次除去する工程を有する
ことを特徴とする半導体装置の製造方法。1. A method of forming a fuse of a semiconductor memory device, comprising forming the fuse by a first wiring layer at a predetermined portion, and then forming an etching stopper layer above the fuse,
A method of manufacturing a semiconductor device, comprising a step of sequentially removing the interlayer insulating film formed on the etching stopper layer and the etching stopper layer.
上方の第２配線層と同一材料からなり、該第２配線層形
成時に形成されることを特徴とする請求項１記載の半導
体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching stopper layer is made of the same material as the second wiring layer above the fuse and is formed when the second wiring layer is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26582294A JPH08125023A (en) | 1994-10-28 | 1994-10-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26582294A JPH08125023A (en) | 1994-10-28 | 1994-10-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08125023A true JPH08125023A (en) | 1996-05-17 |
Family
ID=17422545
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26582294A Pending JPH08125023A (en) | 1994-10-28 | 1994-10-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08125023A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100336952B1 (en) * | 1998-11-20 | 2002-05-15 | 가네꼬 히사시 | Semiconductor memory device with fuse cutting performance improved |
| JP2006148021A (en) * | 2004-11-24 | 2006-06-08 | Matsushita Electric Ind Co Ltd | Semiconductor circuit device and manufacturing method thereof |
| JP2013077771A (en) * | 2011-09-30 | 2013-04-25 | Seiko Instruments Inc | Semiconductor device |
| JP2014160801A (en) * | 2013-01-25 | 2014-09-04 | Seiko Instruments Inc | Semiconductor device |
-
1994
- 1994-10-28 JP JP26582294A patent/JPH08125023A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100336952B1 (en) * | 1998-11-20 | 2002-05-15 | 가네꼬 히사시 | Semiconductor memory device with fuse cutting performance improved |
| JP2006148021A (en) * | 2004-11-24 | 2006-06-08 | Matsushita Electric Ind Co Ltd | Semiconductor circuit device and manufacturing method thereof |
| JP4504791B2 (en) * | 2004-11-24 | 2010-07-14 | パナソニック株式会社 | Semiconductor circuit device and manufacturing method thereof |
| JP2013077771A (en) * | 2011-09-30 | 2013-04-25 | Seiko Instruments Inc | Semiconductor device |
| JP2014160801A (en) * | 2013-01-25 | 2014-09-04 | Seiko Instruments Inc | Semiconductor device |
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