JPH08116024A - Connecting method of bypass capacitor - Google Patents

Connecting method of bypass capacitor

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Publication number
JPH08116024A
JPH08116024A JP25037294A JP25037294A JPH08116024A JP H08116024 A JPH08116024 A JP H08116024A JP 25037294 A JP25037294 A JP 25037294A JP 25037294 A JP25037294 A JP 25037294A JP H08116024 A JPH08116024 A JP H08116024A
Authority
JP
Japan
Prior art keywords
integrated circuit
thin film
bypass capacitor
power supply
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25037294A
Other languages
Japanese (ja)
Other versions
JP3283709B2 (en
Inventor
Masayoshi Yagyu
正義 柳生
Masahide Tokuda
正秀 徳田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP25037294A priority Critical patent/JP3283709B2/en
Publication of JPH08116024A publication Critical patent/JPH08116024A/en
Application granted granted Critical
Publication of JP3283709B2 publication Critical patent/JP3283709B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE: To enable a bypass capacitor in sufficient capacity without deteriorating the package density to be arranged near the power supply terminal electrode of a circuit by a method wherein a transistor for constituting the capacitor of a bypass capacitor or a wired thin film is arranged on the surface of an integrated circuit. CONSTITUTION: On an integrated circuit and a thin film 2, the power supply terminals VDD, GND made on the integrated circuit 1 and the terminals 16, 17 formed on the surface of the thin film 2 are respectively and electrically connected by pressure fixing step, etc. Besides, the other terminals 6, 7 are respectively connected to wiring pattern 4 while a capacitor 3 of bypass capacitor is formed between wirings 4, 5. In such a constitution, the bypass capacitor is formed not on the integrated circuit but on the thin film 2. Accordingly, the bypass capacitor in the sufficient capacity can be arranged not affected by the integration degree of the integrated circuit 1 thereby enabling the circuit operation to be stabilized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は高速に動作する回路装置
に係り、特に、回路の電源電圧揺れ等の電気的なノイズ
を防ぐために用いるバイパスコンデンサの接続方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit device which operates at high speed, and more particularly to a method for connecting a bypass capacitor used to prevent electrical noise such as power supply voltage fluctuation of the circuit.

【０００２】[0002]

【従来の技術】半導体集積回路は電子計算機，パソコ
ン，携帯電話等、非常に多くの装置に組み込まれて利用
されている。特に、電子計算機に代表される高速に信号
を処理する装置では、その高機能化とも相まって、非常
に動作速度が速くまた回路数が多い半導体集積回路が使
われる。この様な半導体集積回路では、回路がスイッチ
ング動作する時にその切り替わり電流に起因する電気的
ノイズ、すなわち、電源電圧揺れが発生する。この電源
電圧揺れは回路動作速度が速いほど、また同時に切り替
わる回路数が多いほど大きくなる。回路の電源電圧が変
動すると回路の動作速度の劣化や誤動作等の問題を引き
起こす。この為、電源電圧揺れが大きくならないような
工夫が従来から取られている。最も代表的な対策は回路
の電源端子間にバイパスコンデンサを接続する方法であ
る。2. Description of the Related Art Semiconductor integrated circuits are used by being incorporated in numerous devices such as electronic computers, personal computers, and mobile phones. In particular, in a device that processes a signal at a high speed, which is represented by an electronic computer, a semiconductor integrated circuit which has a very high operation speed and a large number of circuits is used in combination with its high functionality. In such a semiconductor integrated circuit, when the circuit performs a switching operation, electrical noise caused by the switching current, that is, power supply voltage fluctuation occurs. This fluctuation of the power supply voltage increases as the circuit operating speed increases and the number of circuits that switch at the same time increases. When the power supply voltage of the circuit fluctuates, it causes problems such as deterioration of the operating speed of the circuit and malfunction. Therefore, conventional measures have been taken to prevent the power supply voltage fluctuation from increasing. The most typical measure is to connect a bypass capacitor between the power terminals of the circuit.

【０００３】図６に示す従来例は、集積回路１の正側お
よび負側電源端子ＶＤＤ，ＧＮＤ間にバイパスコンデン
サ１０３を接続した状態を示している。電源端子ＶＤ
Ｄ，ＧＮＤはまず基板１００に接続され、基板１００内
に配置されたスルーホールと電源層１０１，１０２を介
してバイパスコンデンサに接続される。The conventional example shown in FIG. 6 shows a state in which a bypass capacitor 103 is connected between the positive and negative power supply terminals VDD and GND of the integrated circuit 1. Power supply terminal VD
First, D and GND are connected to the substrate 100, and are connected to the bypass capacitor via the through holes arranged in the substrate 100 and the power supply layers 101 and 102.

【０００４】図７は、バイパスコンデンサを接続するた
めの他の従来例である。集積回路１はこれを保持および
持ち運ぶための小さな支持基板１０４に接続される。小
さな支持基板１０４は一般にチップキャリア等の名称で
呼ばれることが多い。この従来例でのバイパスコンデン
サは、チップキャリア１０４内の二つの電源層１０５，
１０６間に発生する静電容量が利用される。チップキャ
リア１０４は集積回路１のハンドリング性を良くするた
めのものであるので、数mm程度の厚さを有することが一
般的である。また、集積回路１の劣化と機械的損傷とを
防ぐ目的で蓋１０７を有していることが多い。FIG. 7 shows another conventional example for connecting a bypass capacitor. The integrated circuit 1 is connected to a small supporting substrate 104 for holding and carrying it. The small support substrate 104 is generally called by a name such as a chip carrier. The bypass capacitor in this conventional example is composed of two power supply layers 105 in the chip carrier 104,
The capacitance generated between 106 is used. Since the chip carrier 104 is for improving the handleability of the integrated circuit 1, it generally has a thickness of about several mm. Further, the integrated circuit 1 is often provided with a lid 107 for the purpose of preventing deterioration and mechanical damage.

【０００５】図８は、バイパスコンデンサを接続するた
めの、更に他の従来例である。この技術は、例えば、ア
イ イー イー イー ジャーナル オブ ソリッド
ステート サーキッツ，ボリューム２５，ナンバー５，
オクトーバ １９９０（IEEEJOURNAL OF SOLID-STATE C
IRCUITS,VOL.25,NO.5,OCTOBER 1990）の１１６６頁から
１１７７頁で紹介されている。集積回路１上にレイアウ
トされたチップ内電源線１１２，１１３間に、チップ上
に作られた論理回路群１１４が接続されている。この図
では、１１２が正側電源ＶＤＤに、１１３が負側電源Ｇ
ＮＤに対応する。この従来例では、チップ上に作られて
おりチップ内電源線間に接続されているｐチャンネルＭ
ＯＳトランジスタ１１０と、ｎチャンネルＭＯＳトラン
ジスタ１１１の、ゲート・ソース間，ゲート・ドレイン
間の寄生容量とソース，ドレインの接合容量がバイパス
コンデンサの機能を有する。図ではバイパスコンデンサ
用のトランジスタを２個しか示していないが、一般には
チップ上で回路用の素子をレイアウトした後の空き領域
のほぼ全面に渡ってバイパスコンデンサ用のトランジス
タを作り込むことで、バイパスコンデンサの容量が大き
くなるように設計する。FIG. 8 shows still another conventional example for connecting a bypass capacitor. This technology is used, for example, in the IE Journal of Solids.
State Circuits, Volume 25, Number 5,
Oktober 1990 (IEEE JOURNAL OF SOLID-STATE C
IRCUITS, VOL.25, NO.5, OCTOBER 1990), pages 1166 to 1177. A logic circuit group 114 formed on the chip is connected between the in-chip power supply lines 112 and 113 laid out on the integrated circuit 1. In this figure, 112 is the positive power supply VDD and 113 is the negative power supply G.
Corresponds to ND. In this conventional example, a p-channel M formed on the chip and connected between power lines in the chip
The parasitic capacitance between the gate and the source and between the gate and the drain and the junction capacitance between the source and the drain of the OS transistor 110 and the n-channel MOS transistor 111 have a function of a bypass capacitor. Although only two transistors for the bypass capacitor are shown in the figure, generally, by arranging the transistor for the bypass capacitor over almost the entire empty area after laying out the elements for the circuit on the chip, the bypass capacitor is formed. Design so that the capacitance of the capacitor is large.

【０００６】[0006]

【発明が解決しようとする課題】図６では、集積回路の
電源端子からバイパスコンデンサに至る配線が長く、回
路が高速に動作する場合は特に、配線に生じる寄生自己
インダクタンスの影響でバイパスコンデンサが有効に機
能しないという問題がある。例えば、この配線の長さを
５mm程度にできた場合、スルーホールの直径が１００μ
ｍとすると、寄生自己インダクタンスは約４ｎＨにな
る。更に図６では、集積回路が占める部分とは別にバイ
パスコンデンサを実装するための面積が必要であるの
で、バイパスコンデンサを接続することによって実装密
度が低下するという別の問題もある。In FIG. 6, the wiring from the power supply terminal of the integrated circuit to the bypass capacitor is long, and the bypass capacitor is effective due to the parasitic self-inductance generated in the wiring especially when the circuit operates at high speed. There is a problem that does not work. For example, if the length of this wiring can be set to about 5 mm, the diameter of the through hole is 100 μm.
When m, the parasitic self-inductance is about 4 nH. Further, in FIG. 6, since an area for mounting the bypass capacitor is required in addition to the portion occupied by the integrated circuit, there is another problem that the mounting density is reduced by connecting the bypass capacitor.

【０００７】図７も、図６と同様の問題を有している。
集積回路の電源端子からチップキャリア内の電源層まで
の長さが、例えば、１mmの場合、スルーホール直径１０
０μｍの配線の寄生自己インダクタンスは約０.５ｎＨ
である。更に、チップキャリアに蓋をするための余白部
分が集積回路の周囲に数mm程度ずつ必要で、チップキャ
リアの面積は集積回路の面積よりも大きくなる。従っ
て、実装密度が低下する。FIG. 7 also has the same problem as FIG.
If the length from the power supply terminal of the integrated circuit to the power supply layer in the chip carrier is 1 mm, the through hole diameter is 10
The parasitic self-inductance of 0 μm wiring is about 0.5 nH
Is. Further, a blank space for covering the chip carrier is required around the integrated circuit by several mm, and the area of the chip carrier becomes larger than the area of the integrated circuit. Therefore, the mounting density is reduced.

【０００８】図８では、バイパスコンデンサは集積回路
内に作られているので、図６，図７の様な寄生自己イン
ダクタンスの問題と実装密度の問題は無い。しかしバイ
パスコンデンサ用のトランジスタをチップ内の空き領域
にレイアウトするため、集積回路上にたくさんのゲート
を作り込む場合には空き領域が小さくなり、バイパスコ
ンデンサの容量を充分確保できないという別の問題があ
る。In FIG. 8, since the bypass capacitor is formed in the integrated circuit, there are no problems of parasitic self-inductance and packaging density as shown in FIGS. However, since the transistors for the bypass capacitors are laid out in the vacant area of the chip, there is another problem that the vacant area becomes small when a large number of gates are built in the integrated circuit, and the capacity of the bypass capacitor cannot be secured sufficiently. .

【０００９】本発明の目的は、電源端子からバイパスコ
ンデンサまでの寄生自己インダクタンスが小さく、実装
密度の劣化を伴わず、更に充分な容量を確保できるバイ
パスコンデンサの接続方法を提供することにある。An object of the present invention is to provide a method of connecting a bypass capacitor, which has a small parasitic self-inductance from a power supply terminal to a bypass capacitor, is not accompanied by deterioration of mounting density, and can secure a sufficient capacity.

【００１０】[0010]

【課題を解決するための手段】本発明の目的は、バイパ
スコンデンサの容量を構成するためのトランジスタまた
は配線を作り込んだ薄膜を集積回路の表面に配置するこ
とで達成できる。The object of the present invention can be achieved by arranging a thin film having a transistor or wiring for forming the capacitance of a bypass capacitor on the surface of an integrated circuit.

【００１１】[0011]

【作用】薄膜の厚さは約１０μｍ程度に薄くでき、さら
に薄膜は回路の電源端子の極近傍に配置できるので、電
源端子からバイパスコンデンサまでの配線の寄生インダ
クタンスは約０.０００２ｎＨ 程度になる。The thickness of the thin film can be reduced to about 10 μm, and since the thin film can be arranged in the immediate vicinity of the power supply terminal of the circuit, the parasitic inductance of the wiring from the power supply terminal to the bypass capacitor is about 0.0002 nH.

【００１２】また薄膜は、集積回路の面積と同じかそれ
よりも小さくて良いので、集積回路の面積が増加せず、
実装密度も劣化しない。Since the thin film may have the same area as or smaller than the area of the integrated circuit, the area of the integrated circuit does not increase,
The mounting density does not deteriorate.

【００１３】容量を構成するための素子は薄膜上に作ら
れるので、集積回路のゲートの使用率で決まる集積回路
チップの空き面積とは独立に、容量を決定できる。Since the element for forming the capacitance is formed on the thin film, the capacitance can be determined independently of the vacant area of the integrated circuit chip determined by the usage rate of the gate of the integrated circuit.

【００１４】[0014]

【実施例】図１は、本発明の第１の実施例である。半導
体集積回路チップ１の表面に薄膜２が接続された状態の
一部分を示す断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a first embodiment of the present invention. 3 is a cross-sectional view showing a part of a state where the thin film 2 is connected to the surface of the semiconductor integrated circuit chip 1. FIG.

【００１５】集積回路１と薄膜２とは、集積回路１上に
作られた電源端子ＶＤＤ，ＧＮＤと薄膜２の表面に作ら
れた端子１６，１７とがそれぞれ圧着等の手段により電
気的に接続される。薄膜上に作られた端子６と７は、集
積回路１の電源端子ＶＤＤ，ＧＮＤとそれぞれ同電位で
あるので、集積回路１と薄膜２が一体となった状態のチ
ップを更に基板，パッケージ等に実装する場合は、端子
６，７から電力を供給すれば良いことは明らかである。
同様に集積回路上の信号端子ＳＩＧは薄膜に作られたス
ルーホールを介して端子１１に接続されるので、端子１
１への信号の入出力は集積回路の信号端子ＳＩＧへのア
クセスと等価である。The integrated circuit 1 and the thin film 2 are electrically connected to the power supply terminals VDD and GND formed on the integrated circuit 1 and the terminals 16 and 17 formed on the surface of the thin film 2 by means of crimping or the like. To be done. Since the terminals 6 and 7 formed on the thin film have the same potentials as the power supply terminals VDD and GND of the integrated circuit 1, the chip in which the integrated circuit 1 and the thin film 2 are integrated is further mounted on a substrate, a package or the like. When mounting, it is clear that power may be supplied from the terminals 6 and 7.
Similarly, since the signal terminal SIG on the integrated circuit is connected to the terminal 11 through the through hole formed in the thin film, the terminal 1
Inputting / outputting a signal to / from 1 is equivalent to accessing the signal terminal SIG of the integrated circuit.

【００１６】薄膜２上には更に、端子６，７にそれぞれ
接続している配線パターン４，５がある。配線４，５の
間にバイパスコンデンサの容量３が作られている。容量
３を実現する方法は、例えば、図７で述べたように、薄
膜上にトランジスタ（図７では、１１０，１１１で表
示）を形成し、それらのトランジスタを図７のチップ内
電源線１１２，１１３がそれぞれ図１の配線４，５に対
応するように接続すれば可能である。On the thin film 2, there are further wiring patterns 4 and 5 connected to the terminals 6 and 7, respectively. The capacitance 3 of the bypass capacitor is formed between the wirings 4 and 5. A method of realizing the capacitor 3 is, for example, as described with reference to FIG. 7, forming transistors (indicated by 110 and 111 in FIG. 7) on a thin film, and forming these transistors in the chip power supply line 112 in FIG. This can be done by connecting 113 so as to correspond to the wirings 4 and 5 of FIG.

【００１７】表面と裏面とに電極を有し、トランジスタ
と配線とを含んだ、厚さ１０μｍ程度の薄膜は、例え
ば、アイ イー イー イー トランザクションズ オ
ンＣＨＭＴ，ボリューム１６，ナンバー７，ノーベンバ
ー １９９３(IEEE Trans.ON CHMT，VOL.16，NO.7，NOV
EMBER 1993）の６１０頁から６１４頁に記載された公知
の技術により得られる。A thin film having a thickness of about 10 μm, which has electrodes on the front surface and the back surface and includes a transistor and wiring, is, for example, IE Transactions on CHMT, volume 16, number 7, Novenver 1993 (IEEE). Trans.ON CHMT, VOL.16, NO.7, NOV
EMBER 1993), pages 610 to 614, by known techniques.

【００１８】図２は、図１で示した薄膜付集積回路チッ
プの上面図である。図１は集積回路チップの一部分を拡
大した断面図であったが、図２の上面図はチップ全体を
表わしている。集積回路１に設けられる電源端子ＶＤ
Ｄ，ＧＮＤはそれぞれ複数個ずつ用意されるのが一般的
である。図２にはＶＤＤ，ＧＮＤに対応する薄膜上の端
子を複数個ずつ示しており、同電位であるものをまとめ
て６，７の番号で表わした。信号端子も同様に複数本を
まとめて１１と表示した。ＶＤＤに対応する端子６は薄
膜上で互いに接続されている。ＧＮＤに対応する端子７
も同様に薄膜上で互いに接続されており、バイパスコン
デンサを形成するためのトランジスタは６，７それぞれ
を互いに接続した配線に並列に配置される。なお、図２
ではトランジスタの記号が描かれているが、実際には容
量として機能するので、図１と同様に３の番号で表わし
てある。FIG. 2 is a top view of the integrated circuit chip with a thin film shown in FIG. 1 is an enlarged sectional view of a part of the integrated circuit chip, the top view of FIG. 2 shows the entire chip. Power supply terminal VD provided in integrated circuit 1
It is general that a plurality of D and GND are prepared. FIG. 2 shows a plurality of terminals on the thin film corresponding to VDD and GND, and those having the same potential are collectively represented by the numbers 6 and 7. Similarly, a plurality of signal terminals are collectively labeled as 11. The terminals 6 corresponding to VDD are connected to each other on the thin film. Terminal 7 corresponding to GND
Are also connected to each other on the thin film, and the transistors for forming the bypass capacitors are arranged in parallel to the wirings in which 6 and 7 are connected to each other. Note that FIG.
In the drawing, the symbol of the transistor is drawn, but since it actually functions as a capacitor, it is represented by the number 3 as in FIG.

【００１９】本発明では、薄膜上のトランジスタはその
寄生容量をバイパスコンデンサの容量として利用するた
めにだけ用い、能動素子として回路のスイッチング動作
に使うことはない。従って薄膜上にｐチャンネルトラン
ジスタとｎチャンネルトランジスタの両方を同時につく
り込む必要はなく、どちらか一種類だけでも良い。この
様な薄膜は２種類のトランジスタを作り込む場合よりも
製造プロセスが簡単になり、システムのコスト低減が図
れる。In the present invention, the transistor on the thin film is used only to utilize its parasitic capacitance as the capacitance of the bypass capacitor, and is not used as an active element for the switching operation of the circuit. Therefore, it is not necessary to simultaneously form both the p-channel transistor and the n-channel transistor on the thin film, and only one of them may be formed. Such a thin film has a simpler manufacturing process than the case where two types of transistors are formed, and the cost of the system can be reduced.

【００２０】図３は、本発明の他の実施例である。この
例では、バイパスコンデンサの容量は薄膜上に形成され
た配線パターン９，１０間の静電容量が利用される。配
線９，１０はそれぞれ集積回路１の電源端子ＶＤＤ，Ｇ
ＮＤに接続しているので、配線間の静電容量は集積回路
１の電源端子ＶＤＤ，ＧＮＤ間のバイパスコンデンサと
して作用する。配線間静電容量は配線９，１０が向かい
合う面積と、配線間の層間絶縁膜８の厚さと、層間絶縁
膜８の誘電率とから決まる。従って配線の対向面積を大
きくし、層間絶縁膜８を薄くし、層間絶縁膜として誘電
率が高い材料を使用することはバイパスコンデンサの容
量を大きくすることに効果がある。FIG. 3 shows another embodiment of the present invention. In this example, the capacitance of the bypass capacitor uses the capacitance between the wiring patterns 9 and 10 formed on the thin film. The wirings 9 and 10 are power supply terminals VDD and G of the integrated circuit 1, respectively.
Since it is connected to ND, the capacitance between the wirings acts as a bypass capacitor between the power supply terminals VDD and GND of the integrated circuit 1. The inter-wiring capacitance is determined by the area where the wirings 9 and 10 face each other, the thickness of the interlayer insulating film 8 between the wirings, and the dielectric constant of the interlayer insulating film 8. Therefore, increasing the opposing area of the wiring, thinning the interlayer insulating film 8 and using a material having a high dielectric constant as the interlayer insulating film is effective in increasing the capacitance of the bypass capacitor.

【００２１】本実施例でも、第１の実施例の図２と同様
に、複数の電源端子間（すなわち複数のＶＤＤ端子に対
応する複数の端子６間、同様に端子７間）を薄膜上で相
互に接続して容量を構成しても良いことは明らかであ
り、その様子を示したものが図４である。図４は薄膜を
上から見た図であるので、バイパスコンデンサの下側の
電極である配線１０はもう一方の電極である配線９にか
くれて一部分しか見えていない。Also in this embodiment, as in FIG. 2 of the first embodiment, a plurality of power supply terminals (that is, a plurality of terminals 6 corresponding to a plurality of VDD terminals, similarly terminals 7) are formed on a thin film. It is clear that the capacitors may be connected to each other to form a capacitor, and FIG. 4 shows the situation. Since FIG. 4 is a view of the thin film viewed from above, the wiring 10 that is the lower electrode of the bypass capacitor is hidden behind the wiring 9 that is the other electrode, and only a part of it is visible.

【００２２】本実施例では、薄膜上にバイパスコンデン
サを形成するための製造プロセスは集積回路１の製造時
には現れない。従って、集積回路１上の配線間にバイパ
スコンデンサを作り込む場合よりも集積回路１の製造歩
留まりを良くできる。In this embodiment, the manufacturing process for forming the bypass capacitor on the thin film does not appear when the integrated circuit 1 is manufactured. Therefore, the manufacturing yield of the integrated circuit 1 can be improved as compared with the case where the bypass capacitor is formed between the wirings on the integrated circuit 1.

【００２３】本実施例では、薄膜２上にトランジスタを
形成する必要が無い。従って本発明の第１の実施例とは
異なり、薄膜２の材料はシリコン等の半導体である必要
が無く、例えば、ガラスエポキシやポリイミドを用いた
フィルムが利用できる。この様なフィルムを使用した場
合は、フィルムの両面を接続するためのスルーホール配
線は、例えば、ドリル加工やレーザ光線による加工で形
成した穴にメッキ等により導電性の金属を充填すること
で得られる。In this embodiment, it is not necessary to form a transistor on the thin film 2. Therefore, unlike the first embodiment of the present invention, the material of the thin film 2 does not need to be a semiconductor such as silicon, and for example, a film using glass epoxy or polyimide can be used. When such a film is used, the through-hole wiring for connecting both sides of the film can be obtained, for example, by filling a hole formed by drilling or laser beam processing with a conductive metal by plating or the like. To be

【００２４】以上の二つの実施例において、薄膜２の厚
さはおよそ１０μｍ程度にできる。ＶＤＤおよびＧＮＤ
につながる薄膜内のスルーホールの直径を１００μｍに
設計した場合、集積回路１の電源端子から最も近いバイ
パスコンデンサまでの配線に生じる寄生自己インダクタ
ンスはおよそ０.０００２ｎＨ 程度になるので、寄生自
己インダクタンスによるバイパスコンデンサの効果の劣
化は図６，図７に示した従来例と比べて無視できる程度
に少ない。In the above two embodiments, the thickness of the thin film 2 can be about 10 μm. VDD and GND
If the diameter of the through hole in the thin film connected to is designed to be 100 μm, the parasitic self-inductance generated in the wiring from the power supply terminal of the integrated circuit 1 to the closest bypass capacitor will be about 0.0002 nH, so the parasitic self-inductance bypass The deterioration of the effect of the capacitor is negligibly small as compared with the conventional example shown in FIGS.

【００２５】本発明の目的は集積回路の電源端子間にバ
イパスコンデンサを接続することであるので、集積回路
上の電源揺れが問題になる電源端子が存在する部分をカ
バーするように薄膜を配置すれば良い。従って図２およ
び図４に示すように、薄膜２の面積は集積回路１の面積
と同じかそれよりも小さくてよいので、バイパスコンデ
ンサを配置したことによる実装密度の低下は無い。Since the object of the present invention is to connect a bypass capacitor between the power supply terminals of the integrated circuit, it is necessary to arrange the thin film so as to cover the portion on the integrated circuit where the power supply terminal in which the power supply fluctuation becomes a problem exists. Good. Therefore, as shown in FIGS. 2 and 4, the area of the thin film 2 may be the same as or smaller than the area of the integrated circuit 1, so that the mounting density is not reduced by disposing the bypass capacitor.

【００２６】図５は、本発明の第３の実施例である。図
５に示した薄膜２には、図１，図３の薄膜とは異なり、
集積回路１に面した側にしか端子が存在しない。薄膜２
の端子は集積回路１上に設けられた、バイパスコンデン
サを接続するための電源端子ＶＤＤ１，ＧＮＤ１と、そ
れぞれ接している。集積回路１への電力の供給は、集積
回路上で薄膜２の下に隠れない場所に作られた別の電源
端子ＶＤＤ，ＧＮＤを介して行う。信号入出力用の端子
ＳＩＧも薄膜２の下に隠れない場所に作られ、薄膜２内
のスルーホールを介さずに直接、基板，パッケージ等の
信号用端子と接続される。ＶＤＤ１とＶＤＤ間，ＧＮＤ
１とＧＮＤ間はそれぞれ集積回路１上に作られた配線に
よって電気的な導通があるので、本図に示した構成でも
ＶＤＤ，ＧＮＤ間にバイパスコンデンサを接続できる。FIG. 5 shows a third embodiment of the present invention. Unlike the thin films of FIGS. 1 and 3, the thin film 2 shown in FIG.
The terminals are present only on the side facing the integrated circuit 1. Thin film 2
Are connected to power supply terminals VDD1 and GND1 provided on the integrated circuit 1 for connecting bypass capacitors. The power is supplied to the integrated circuit 1 via the other power supply terminals VDD and GND which are formed on the integrated circuit under the thin film 2 so as not to be hidden. The signal input / output terminal SIG is also formed in a place not hidden under the thin film 2, and is directly connected to the signal terminal of the substrate, the package or the like without passing through the through hole in the thin film 2. Between VDD1 and VDD, GND
1 and GND are electrically connected to each other by the wiring formed on the integrated circuit 1, so that a bypass capacitor can be connected between VDD and GND even in the configuration shown in this figure.

【００２７】この新たな実施例では、薄膜２には表面と
裏面とをつなぐスルーホール配線を作る必要が無いので
薄膜２の製造プロセスが簡単になり、システムのコスト
を下げることができる。なお、図５に示した薄膜２のバ
イパスコンデンサの形成方法は図１に示したものと同様
の方法を用いているが、バイパスコンデンサの形成方法
として図３に示した、配線間の静電容量を用いる方法を
使っても本発明の本質を損なわない。In this new embodiment, since it is not necessary to form through-hole wiring for connecting the front surface and the back surface of the thin film 2, the manufacturing process of the thin film 2 can be simplified and the system cost can be reduced. The method of forming the bypass capacitor of the thin film 2 shown in FIG. 5 is the same as that shown in FIG. 1, but the capacitance between the wirings shown in FIG. 3 is used as the method of forming the bypass capacitor. The use of the method does not impair the essence of the present invention.

【００２８】図５に示した実施例でも、第１および第２
の実施例と同様に、集積回路の電源端子からバイパスコ
ンデンサまでの配線に生じる寄生自己インダクタンスは
従来例と比べて非常に小さい。また薄膜は、集積回路上
に設けられたバイパスコンデンサを接続するための電源
端子を覆うように配置すれば良いので、薄膜の面積は集
積回路の面積よりも小さくでき、集積回路の実装密度が
低下しない。Also in the embodiment shown in FIG. 5, the first and second
Similar to the embodiment described above, the parasitic self-inductance generated in the wiring from the power supply terminal of the integrated circuit to the bypass capacitor is much smaller than that of the conventional example. Since the thin film can be placed so as to cover the power supply terminal for connecting the bypass capacitor provided on the integrated circuit, the area of the thin film can be made smaller than the area of the integrated circuit, which reduces the packaging density of the integrated circuit. do not do.

【００２９】本発明の第１から第３の実施例において、
バイパスコンデンサは集積回路上ではなく、薄膜上に作
られている。従って、図８の従来例が有していた、ゲー
ト使用率が高い集積回路はチップ上の空き領域が少なく
なり、充分な個数のトランジスタ、すなわち、充分な容
量のバイパスコンデンサを作り込めないという問題は解
決されている。更に本発明の第１および第２の実施例
は、集積回路上に薄膜を２枚以上積み重ねることによっ
て、回路動作を安定させるのに必要な容量のバイパスコ
ンデンサを接続できる。In the first to third embodiments of the present invention,
Bypass capacitors are made on thin films, not on integrated circuits. Therefore, the integrated circuit with a high gate usage rate, which the conventional example of FIG. 8 has, has a small free area on the chip, and a sufficient number of transistors, that is, a bypass capacitor having a sufficient capacity cannot be created. Has been resolved. Furthermore, in the first and second embodiments of the present invention, by stacking two or more thin films on the integrated circuit, a bypass capacitor having a capacitance necessary for stabilizing the circuit operation can be connected.

【００３０】[0030]

【発明の効果】本発明によれば、回路の電源端子の極近
傍に、回路装置の実装密度を劣化させることなく、回路
の集積度に影響を受けないで充分な容量のバイパスコン
デンサを配置することができるので、回路動作の安定化
が図れる。According to the present invention, a bypass capacitor having a sufficient capacity is arranged in the immediate vicinity of the power supply terminal of the circuit without deteriorating the packaging density of the circuit device and being influenced by the degree of integration of the circuit. Therefore, the circuit operation can be stabilized.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例を示す断面図。FIG. 1 is a sectional view showing a first embodiment of the present invention.

【図２】第１の実施例の上面図。FIG. 2 is a top view of the first embodiment.

【図３】本発明の第２の実施例を示す断面図。FIG. 3 is a sectional view showing a second embodiment of the present invention.

【図４】第２の実施例の上面図。FIG. 4 is a top view of the second embodiment.

【図５】本発明の第３の実施例を示す断面図。FIG. 5 is a sectional view showing a third embodiment of the present invention.

【図６】バイパスコンデンサの実装方法を示す第１の従
来例を示す説明図。FIG. 6 is an explanatory view showing a first conventional example showing a mounting method of a bypass capacitor.

【図７】バイパスコンデンサの実装方法を示す第２の従
来例を示す説明図。FIG. 7 is an explanatory view showing a second conventional example showing a mounting method of a bypass capacitor.

【図８】バイパスコンデンサの実装方法を示す第３の従
来例を示す説明図。FIG. 8 is an explanatory view showing a third conventional example showing a mounting method of a bypass capacitor.

【符号の説明】[Explanation of symbols]

１…集積回路、２…薄膜、３…容量、４，５…配線、Ｖ
ＤＤ，ＧＮＤ，６，７，１６，１７…電源端子、ＳＩ
Ｇ，１１…信号端子。1 ... Integrated circuit, 2 ... Thin film, 3 ... Capacitance, 4, 5 ... Wiring, V
DD, GND, 6, 7, 16, 17 ... Power supply terminal, SI
G, 11 ... Signal terminals.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】集積回路チップと薄膜とが積層されてお
り、前記薄膜上に作られた複数の電極端子が集積回路上
に作られた複数の電極端子と電気的に接続されており、
前記薄膜上の複数の電極間に接続されるように前記薄膜
上にコンデンサが形成されていることを特徴とするバイ
パスコンデンサの接続方法。1. An integrated circuit chip and a thin film are laminated, and a plurality of electrode terminals formed on the thin film are electrically connected to a plurality of electrode terminals formed on the integrated circuit,
A method of connecting a bypass capacitor, wherein a capacitor is formed on the thin film so as to be connected between a plurality of electrodes on the thin film. 【請求項２】請求項１において、前記コンデンサは、前
記薄膜上に作られたトランジスタの寄生容量と接合容量
で構成されているバイパスコンデンサの接続方法。2. The method for connecting a bypass capacitor according to claim 1, wherein the capacitor is composed of a parasitic capacitance and a junction capacitance of a transistor formed on the thin film. 【請求項３】請求項１において、前記コンデンサは、前
記薄膜上に構成した配線間の静電容量で構成されている
バイパスコンデンサの接続方法。3. The method for connecting a bypass capacitor according to claim 1, wherein the capacitor is composed of capacitance between wirings formed on the thin film. 【請求項４】請求項１，２または３において、前記薄膜
上の複数の電極は、バイパスコンデンサを接続するため
に集積回路に設けられた複数の電源端子にそれぞれ接続
されており、前記集積回路への電力の供給は前記集積回
路に設けられた別の電源端子から行われるバイパスコン
デンサの接続方法。4. The integrated circuit according to claim 1, wherein the plurality of electrodes on the thin film are respectively connected to a plurality of power supply terminals provided in the integrated circuit for connecting a bypass capacitor. A method of connecting a bypass capacitor, wherein power is supplied to the integrated circuit from another power supply terminal provided in the integrated circuit.
JP25037294A 1994-10-17 1994-10-17 Connection method of bypass capacitor Expired - Fee Related JP3283709B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25037294A JP3283709B2 (en) 1994-10-17 1994-10-17 Connection method of bypass capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25037294A JP3283709B2 (en) 1994-10-17 1994-10-17 Connection method of bypass capacitor

Publications (2)

Publication Number Publication Date
JPH08116024A true JPH08116024A (en) 1996-05-07
JP3283709B2 JP3283709B2 (en) 2002-05-20

Family

ID=17206946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25037294A Expired - Fee Related JP3283709B2 (en) 1994-10-17 1994-10-17 Connection method of bypass capacitor

Country Status (1)

Country Link
JP (1) JP3283709B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023022047A1 (en) * 2021-08-20 2023-02-23 株式会社村田製作所 High-frequency module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023022047A1 (en) * 2021-08-20 2023-02-23 株式会社村田製作所 High-frequency module

Also Published As

Publication number Publication date
JP3283709B2 (en) 2002-05-20

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