JPH0810737B2 - Chip carrier and manufacturing method thereof - Google Patents
Chip carrier and manufacturing method thereofInfo
- Publication number
- JPH0810737B2 JPH0810737B2 JP5019149A JP1914993A JPH0810737B2 JP H0810737 B2 JPH0810737 B2 JP H0810737B2 JP 5019149 A JP5019149 A JP 5019149A JP 1914993 A JP1914993 A JP 1914993A JP H0810737 B2 JPH0810737 B2 JP H0810737B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- cap
- ceramic substrate
- metal frame
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はチップキャリアに関し、
特にセラミック基板上に搭載されたＩＣチップを封止す
るためのチップキャリアに関する。FIELD OF THE INVENTION The present invention relates to a chip carrier,
In particular, it relates to a chip carrier for encapsulating an IC chip mounted on a ceramic substrate.
【０００２】[0002]
【従来の技術】従来、この種のチップキャリアにおいて
は、図３に示すように、セラミック基板１上に設置され
たパッド１ｃとＩＣチップ４に設けられたリード８とが
接続されている。このＩＣチップ４を封止するためのキ
ャップ１０は放熱板１０ａに金属枠１０ｂを銀ロー１０
ｃで接合して構成されている。ＩＣチップ４の封止はキ
ャップ１０の金属枠１０ｂと、セラミック基板１に銀ロ
ー９で接着された金属枠２とをローラー電極７を用いた
シーム溶接やレーザ溶接などで密着させることによって
行う。2. Description of the Related Art Conventionally, in this type of chip carrier, as shown in FIG. 3, a pad 1c provided on a ceramic substrate 1 and a lead 8 provided on an IC chip 4 are connected. The cap 10 for sealing the IC chip 4 includes a heat sink 10a, a metal frame 10b, and a silver braze 10.
It is configured by joining with c. The IC chip 4 is sealed by bringing the metal frame 10b of the cap 10 and the metal frame 2 adhered to the ceramic substrate 1 with silver bra 9 into close contact by seam welding using the roller electrode 7, laser welding, or the like.
【０００３】このＩＣチップ４をキャップ１０で封止す
る場合、放熱板１０ａにＩＣチップ４を熱伝導性の接着
剤５で接着させる。これによって、ＩＣチップ４で発生
する熱が放熱板１０ａに伝導され、放熱板１０ａから外
部に放散される。なお、上述したＩＣチップの封止技術
については特開平１−１５０３４３号公報に詳述されて
いる。When the IC chip 4 is sealed with the cap 10, the IC chip 4 is adhered to the heat dissipation plate 10a with the heat conductive adhesive 5. As a result, the heat generated in the IC chip 4 is conducted to the heat dissipation plate 10a and dissipated to the outside from the heat dissipation plate 10a. The IC chip sealing technique described above is described in detail in Japanese Patent Application Laid-Open No. 1-150343.
【０００４】[0004]
【発明が解決しようとする課題】以上説明した従来のチ
ップキャリアでは、ＩＣチップ４をセラミック基板１上
に実装する際、リード８の長さや、リード８とＩＣチッ
プ４との接着あるいはリード８とセラミック基板１上の
パッド１ｃとの接着が均一になりにくいため、ＩＣチッ
プ４をセラミック基板１に対して平行に取り付けること
が困難となり、またＩＣチップ４をセラミック基板１に
取り付けた状態でＩＣチップ４の高さにバラツキが生じ
る。この状態で、キャップ封止をしようとすると、キャ
ップ１０の放熱板１０ａとＩＣチップ４とのギャップが
不均一となったり、キャップ１０の金属枠１０ｂとセラ
ミック基板１の金属枠２との間にギャップが発生してし
まうという問題がある。In the conventional chip carrier described above, when the IC chip 4 is mounted on the ceramic substrate 1, the length of the lead 8 or the adhesion between the lead 8 and the IC chip 4 or the lead 8 is not required. It is difficult to attach the IC chip 4 in parallel to the ceramic substrate 1 because the adhesion with the pad 1c on the ceramic substrate 1 is difficult to be made uniform. There are variations in the height of 4. If cap sealing is attempted in this state, the gap between the heat dissipation plate 10a of the cap 10 and the IC chip 4 becomes uneven, or the gap between the metal frame 10b of the cap 10 and the metal frame 2 of the ceramic substrate 1 is increased. There is a problem that a gap occurs.
【０００５】放熱板１０ａとＩＣチップ４とのギャップ
が不均一になると、放熱板１０ａとＩＣチップ４とを接
着させるための接着剤５の量のコントロールが困難とな
る。接着剤の量が少ないと接着剤５中に気泡が発生し、
ＩＣチップ４と放熱板１０ａとの間の接着強度が得られ
ない。また接着剤５中の気泡によって熱抵抗が大きくな
り、要求された放熱能力が得られず、ひどい場合にはＩ
Ｃチップ４の動作中に発生する熱によって熱応力が発生
し、ＩＣチップ４が割れるという問題もある。If the gap between the heat sink 10a and the IC chip 4 becomes uneven, it becomes difficult to control the amount of the adhesive 5 for bonding the heat sink 10a and the IC chip 4 together. If the amount of adhesive is small, bubbles will be generated in the adhesive 5,
Adhesive strength between the IC chip 4 and the heat sink 10a cannot be obtained. Further, the air bubbles in the adhesive 5 increase the thermal resistance, and the required heat dissipation ability cannot be obtained.
There is also a problem that thermal stress is generated by the heat generated during the operation of the C chip 4, and the IC chip 4 is cracked.
【０００６】また、キャップ１０の金属枠１０ｂとセラ
ミック基板１の金属枠２との間にギャップが発生してし
まうと、シーム溶接のためにローラー電極７でキャップ
１０の金属枠１０ｂを上から押さえつけたときにキャッ
プ１０やＩＣチップ４に機械応力が加わり、キャップ１
０やＩＣチップ４を破壊してしまうという問題がある。When a gap is generated between the metal frame 10b of the cap 10 and the metal frame 2 of the ceramic substrate 1, the metal frame 10b of the cap 10 is pressed from above by the roller electrode 7 for seam welding. Mechanical stress is applied to the cap 10 and IC chip 4 when the cap 1
There is a problem that 0 or the IC chip 4 is destroyed.
【０００７】[0007]
【課題を解決するための手段】本発明によるチップキャ
リアは、ＩＣチップを搭載したセラミック基板と、下面
が前記ＩＣチップの上面に接着された放熱板と、前記セ
ラミック基板の外側面に固着された金属枠と、上部の内
面が前記放熱板の外側面に固着され下部の内面が前記金
属枠の外周側面にシーム溶接されたキャップ枠とを備え
ている。A chip carrier according to the present invention has a ceramic substrate on which an IC chip is mounted, a heat dissipation plate having a lower surface bonded to the upper surface of the IC chip, and an outer surface of the ceramic substrate. It comprises a metal frame and a cap frame whose inner surface is fixed to the outer surface of the heat sink and whose inner surface is seam-welded to the outer peripheral side surface of the metal frame.
【０００８】[0008]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【０００９】図１は本発明の一実施例を示す縦断面図で
あり、図２は本実施例の斜視図である。これらの図にお
いて、ＩＣチップ４はセラミック基板１の上面に設けら
れた接続パッド１ｃにＳｎ／Ｐｂ（６３／３７ｗｔ％）
等の半田のバンプ３で接続することで、セラミック基板
１上に搭載されている。接続パッド１Ｃはセラミック基
板１の内部の導体配線層１ａを介してセラミック基板１
の下面に設けられた入出力パッド１ｂに接続されてい
る。FIG. 1 is a vertical sectional view showing an embodiment of the present invention, and FIG. 2 is a perspective view of this embodiment. In these figures, the IC chip 4 has Sn / Pb (63/37 wt%) on the connection pad 1c provided on the upper surface of the ceramic substrate 1.
It is mounted on the ceramic substrate 1 by connecting the solder bumps 3 of the same type. The connection pad 1C is formed on the ceramic substrate 1 via the conductor wiring layer 1a inside the ceramic substrate 1.
Is connected to the input / output pad 1b provided on the lower surface of the.
【００１０】キャップ６は放熱板６ａの外周側面に金属
性のキャップ枠６ｃの上部をロー材６ｂで固着して構成
されている。このキャップ６のキャップ枠６ｃの内側開
口部の大きさは、セラミック基板１の外側面にロー材
（図に示していない）等により接着された金属枠２の外
形より若干大きく構成されている。このキャップ６は、
ＩＣチップ４の搭載されたセラミック基板１にＩＣチッ
プ４側からかぶせて、キャップ６の放熱板６ａの下面と
ＩＣチップ４の上面とを熱伝導性の接着剤５にて固着す
る構造となっている。このとき、キャップ６のキャップ
枠６ｃの下端がセラミック基板１の下面とほぼ同じ面に
来るように構成されており、セラミック基板１に接着さ
れた金属枠２の外周側面と、キャップ６のキャップ枠６
ｃの下部内壁とを、キャップ枠６ｃの外側からローラー
電極７によってシーム溶接で接合することによってＩＣ
チップ４の気密封止が行われる。キャップ枠６ｃの厚さ
はこのシーム溶接時のローラー電極７の圧力である程度
変形するだけの厚さに構成されている。ＩＣチップ４は
キャップ６の放熱板６ａに熱伝導性の接着剤５で十分に
固着されているため、ＩＣチップ４で発生する熱はキャ
ップ６の放熱板６ａに伝導され、放熱板６ａから外部に
放出される。The cap 6 is constructed by fixing the upper portion of a metallic cap frame 6c to the outer peripheral surface of the heat dissipation plate 6a with a brazing material 6b. The size of the inner opening of the cap frame 6c of the cap 6 is slightly larger than the outer shape of the metal frame 2 adhered to the outer surface of the ceramic substrate 1 by a brazing material (not shown) or the like. This cap 6
The ceramic substrate 1 on which the IC chip 4 is mounted is covered from the IC chip 4 side, and the lower surface of the heat dissipation plate 6a of the cap 6 and the upper surface of the IC chip 4 are fixed with a heat conductive adhesive 5. There is. At this time, the lower end of the cap frame 6c of the cap 6 is arranged to be substantially on the same surface as the lower surface of the ceramic substrate 1, and the outer peripheral side surface of the metal frame 2 adhered to the ceramic substrate 1 and the cap frame of the cap 6 are arranged. 6
The lower inner wall of c is joined to the IC by seam welding from the outside of the cap frame 6c by the roller electrode 7.
The chip 4 is hermetically sealed. The thickness of the cap frame 6c is such that it is deformed to some extent by the pressure of the roller electrode 7 during seam welding. Since the IC chip 4 is sufficiently fixed to the heat dissipation plate 6a of the cap 6 with the heat conductive adhesive 5, the heat generated in the IC chip 4 is conducted to the heat dissipation plate 6a of the cap 6, and the heat is dissipated from the heat dissipation plate 6a to the outside. Is released to.
【００１１】ＩＣチップ４がセラミック基板１上の接続
パッド１ｃの半田のバンプ３で接続されるとき、バンプ
３の大きさの違い、あるいはセラミック基板１の接続パ
ッド１ｃの形状や寸法の相違、ＩＣチップ４の搭載時の
位置ずれなどによってＩＣチップ４が傾いたり、高さが
ばらついたりした状態でセラミック基板１上に搭載され
てしまうことがある。この傾いたり、高さがばらついた
りした状態のＩＣチップ４が搭載されたセラミック基板
１上にキャップ６をかぶせてＩＣチップ４を気密封止す
るのであるが、キャップ６をＩＣチップ４の搭載された
セラミック基板１上にかぶせたとき、キャップ６の放熱
板６ａが接着剤５を介してＩＣチップ４に付き当てられ
るため、キャップ６はＩＣチップ４の傾きにならい、キ
ャップ６の放熱板６ａとＩＣチップ４とのギャップが均
一となる。ギャップが均一になることによって、キャッ
プ６の放熱板６ａとＩＣチップ４との間に接着剤５を均
一に充填することができるので、放熱板６ａとＩＣチッ
プ４とが十分に接着され、適当な強度および熱伝導性が
得られる。When the IC chip 4 is connected by the solder bump 3 of the connection pad 1c on the ceramic substrate 1, the size of the bump 3 is different, or the shape and size of the connection pad 1c of the ceramic substrate 1 is different, IC The IC chip 4 may be mounted on the ceramic substrate 1 in a state in which the IC chip 4 is tilted or the height is varied due to a positional deviation when the chip 4 is mounted. The IC chip 4 is mounted on the ceramic substrate 1 on which the IC chip 4 in the tilted or the height is varied is covered by the cap 6 to hermetically seal the IC chip 4. When it is put on the ceramic substrate 1, the heat dissipation plate 6a of the cap 6 is abutted against the IC chip 4 via the adhesive 5, so that the cap 6 follows the inclination of the IC chip 4 and the heat dissipation plate 6a of the cap 6 The gap with the IC chip 4 becomes uniform. Since the gap is made uniform, the adhesive 5 can be uniformly filled between the heat sink 6a of the cap 6 and the IC chip 4, so that the heat sink 6a and the IC chip 4 are sufficiently adhered to each other. Good strength and thermal conductivity are obtained.
【００１２】この状態で、セラミック基板１の金属枠２
の外周側面と、キャップ６のキャップ枠６ｃの内壁と
を、キャップ枠６ｃの外側からローラー電極７によって
シーム溶接で接合することによってＩＣチップ４の気密
封止が行われ、チップキャリアの信頼性を向上させるこ
とができる。放熱板６ａをＩＣチップ４に突き当てて接
着することにより、キャップ枠６ｃと金属枠２の間には
一般にギャップが生じるが、これらをローラー電極７で
シーム溶接する特にキャップ枠６ｃが変形し、金属枠２
に密着させられるためＩＣチップの封止について問題は
ない。In this state, the metal frame 2 of the ceramic substrate 1
The IC chip 4 is hermetically sealed by joining the outer peripheral side surface of the cap 6 and the inner wall of the cap frame 6c of the cap 6 by seam welding from the outside of the cap frame 6c by the roller electrode 7 to improve the reliability of the chip carrier. Can be improved. A gap is generally created between the cap frame 6c and the metal frame 2 by abutting and adhering the heat sink 6a to the IC chip 4, but seam welding of these with the roller electrode 7 especially the cap frame 6c is deformed, Metal frame 2
There is no problem in sealing the IC chip because it is closely attached to the.
【００１３】[0013]
【発明の効果】以上説明したように本発明によれば、放
熱板とＩＣチップとのギャップを均一に保って適度な接
着を得ながら、かつ放熱板及びキャップ枠からなるキャ
ップやＩＣチップに必要以上の機械応力を加えることな
くキャップ封止を行うことができ、放熱板とＩＣチップ
とを密着するための接着剤の量の管理を容易に行うこと
ができるとともに、ＩＣチップの動作中に発生する熱に
よる熱応力の発生を減少させることができるという効果
がある。As described above, according to the present invention, the gap between the heat sink and the IC chip is kept uniform, and proper adhesion is obtained, and it is necessary for the cap including the heat sink and the cap frame and the IC chip. Cap sealing can be performed without applying the above mechanical stress, the amount of adhesive for adhering the heat dissipation plate and the IC chip can be easily controlled, and this occurs during operation of the IC chip. There is an effect that it is possible to reduce the generation of thermal stress due to the applied heat.
【図１】本発明のチップキャリアの一実施例を示す縦断
面図である。FIG. 1 is a vertical sectional view showing an embodiment of a chip carrier of the present invention.
【図２】図１に示す実施例の斜視図である。FIG. 2 is a perspective view of the embodiment shown in FIG.
【図３】従来のチップキャリアを示す縦断面図である。FIG. 3 is a vertical sectional view showing a conventional chip carrier.
１ セラミック基板 １ａ 導体配線層 １ｂ 入出力パッド １ｃ 接続パッド ２ 金属枠 ３ バンプ ４ ＩＣチップ ５ 接着剤 ６ キャップ ６ａ 放熱板 ６ｂ ロー材 ６ｃ キャップ枠 ７ ローラー電極 ８ リード ９ ロー材 １０ キャップ １０ａ 放熱板 １０ｂ 金属枠 １０ｃ ロー材 1 Ceramic Substrate 1a Conductor Wiring Layer 1b Input / Output Pad 1c Connection Pad 2 Metal Frame 3 Bump 4 IC Chip 5 Adhesive 6 Cap 6a Heat Sink 6b Brazing Material 6c Cap Frame 7 Roller Electrode 8 Lead 9 Brazing Material 10 Cap 10a Radiating Board 10b Metal frame 10c Low material
Claims (3)
と、下面が前記ＩＣチップの上面に接着された放熱板
と、前記セラミック基板の外側面に固着された金属枠
と、上部の内面が前記放熱板の外側面に固着され下部の
内面が前記金属枠の外周側面にシーム溶接されたキャッ
プ枠とを含むことを特徴とするチップキャリア。1. A ceramic substrate on which an IC chip is mounted, a heat dissipation plate whose lower surface is adhered to the upper surface of the IC chip, a metal frame fixed to the outer surface of the ceramic substrate, and an inner surface of the upper part is the heat dissipation plate. A chip carrier fixed to the outer surface of the metal frame and having a lower inner surface seam-welded to the outer peripheral side surface of the metal frame.
面にロー付けされた請求項１記載のチップキャリア。2. The chip carrier according to claim 1, wherein the upper inner surface of the cap frame is brazed to the outer surface of the heat dissipation plate.
の上面に外側面にキャップ枠の上部の内面が固着された
放熱板の下面を突き当てて接着した後に前記セラミック
基板の外側面に固着された金属枠に前記キャップ枠の下
部の内面をシーム溶接することを特徴とするチップキャ
リアの製造方法。3. An IC chip mounted on a ceramic substrate is affixed to the outer surface of the ceramic substrate after the lower surface of a heat radiating plate having the inner surface of the upper portion of the cap frame fixed to the outer surface is abutted and bonded. A method of manufacturing a chip carrier, comprising seam-welding a lower inner surface of the cap frame to a metal frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5019149A JPH0810737B2 (en) | 1993-02-08 | 1993-02-08 | Chip carrier and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5019149A JPH0810737B2 (en) | 1993-02-08 | 1993-02-08 | Chip carrier and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06232289A JPH06232289A (en) | 1994-08-19 |
| JPH0810737B2 true JPH0810737B2 (en) | 1996-01-31 |
Family
ID=11991387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5019149A Expired - Fee Related JPH0810737B2 (en) | 1993-02-08 | 1993-02-08 | Chip carrier and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810737B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0989981A (en) * | 1995-09-28 | 1997-04-04 | Nec Corp | Chip carrier |
| KR100258854B1 (en) * | 1996-12-31 | 2000-06-15 | 김영환 | Area array semiconductor package and manufacturing method thereof |
| US6104093A (en) * | 1997-04-24 | 2000-08-15 | International Business Machines Corporation | Thermally enhanced and mechanically balanced flip chip package and method of forming |
| CN100373599C (en) * | 2005-09-29 | 2008-03-05 | 威盛电子股份有限公司 | Non-lug type chip encapsulation |
-
1993
- 1993-02-08 JP JP5019149A patent/JPH0810737B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06232289A (en) | 1994-08-19 |
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