JPH08107167A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08107167A JPH08107167A JP6240098A JP24009894A JPH08107167A JP H08107167 A JPH08107167 A JP H08107167A JP 6240098 A JP6240098 A JP 6240098A JP 24009894 A JP24009894 A JP 24009894A JP H08107167 A JPH08107167 A JP H08107167A
- Authority
- JP
- Japan
- Prior art keywords
- light receiving
- receiving element
- semiconductor device
- semiconductor
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、基体の表裏に第一の半
導体素子と第二の半導体素子とを配置した半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a first semiconductor element and a second semiconductor element are arranged on the front and back of a base.
【０００２】[0002]
【従来の技術】ＣＣＤシステムは、一般にイメージセン
サ部、シンクシグナルジェネレーター（Sync signal ge
nerator ）部、タイミングジェネレーター（Timing gen
erator）部、さらには駆動部、信号プロセッサー部、エ
ンコーダー部等から構成されている。ところで、このＣ
ＣＤシステムにおいては、イメージセンサ部以外の他の
周辺半導体素子はエポキシモールドパッケージで封止さ
れて形成されるものの、イメージセンサ部はセラミック
又はモールド樹脂中空パッケージ又はクリアモールドパ
ッケージで封止されており、この状態でそれぞれが同一
プリント回路基板（ＰＣＢ）上にマウント化されて構成
されている。2. Description of the Related Art A CCD system generally includes an image sensor unit and a sync signal generator.
nerator) Timing generator (Timing gen)
erator) section, and further includes a drive section, a signal processor section, an encoder section, and the like. By the way, this C
In the CD system, peripheral semiconductor elements other than the image sensor unit are formed by being sealed with an epoxy mold package, but the image sensor unit is sealed with a ceramic or mold resin hollow package or a clear mold package. In this state, they are mounted on the same printed circuit board (PCB).
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、イメー
ジセンサ部以外のチップはＢｉｐＩＣやＭＯＳＩＣであ
り、前述したようにエポキシモールドパッケージで封止
されていることから、同一プリント回路基板内でのベア
チップ化、つまりハイブリッドＩＣ化が可能であるもの
の、イメージセンサ部のチップはその光学特性上の問題
やゴミによる画質欠陥等の問題によってベアチップマウ
ントが困難になっており、このため中空パッケージ又は
クリアモールドパッケージで封止されていることから、
システム全体の小型化、軽量化、コストダウン化が損な
われている。また、ＣＣＤシステムに限ることなく、半
導体装置全般にわたってその小型化、軽量化や高性能化
が望まれており、このように小型化等を実現し得る技術
の提供が望まれている。However, since the chips other than the image sensor portion are BipIC or MOSIC and are sealed with the epoxy mold package as described above, they are formed into bare chips in the same printed circuit board. In other words, although a hybrid IC is possible, bare chip mounting is difficult for the chip of the image sensor part due to problems with its optical characteristics and image quality defects due to dust. Therefore, it is sealed with a hollow package or a clear mold package. Because it is stopped,
The miniaturization, weight reduction, and cost reduction of the entire system are impaired. Further, not only the CCD system but also semiconductor devices in general are desired to be reduced in size, weight, and higher in performance, and it is desired to provide a technique capable of realizing such reduction in size.
【０００４】[0004]
【課題を解決するための手段】本発明の半導体装置では
前記課題を達成すべく、表裏面を有する基体の一方の面
側に中空部を形成し、該中空部内に第一の半導体素子を
設け、該第一の半導体素子の裏側に第二の半導体素子を
設けている。In the semiconductor device of the present invention, in order to achieve the above object, a hollow portion is formed on one surface side of a substrate having front and back surfaces, and a first semiconductor element is provided in the hollow portion. A second semiconductor element is provided on the back side of the first semiconductor element.
【０００５】[0005]
【作用】本発明の半導体装置によれば、基体の表裏両側
にそれぞれ半導体素子を設け、しかも基体の一方の面側
には中空部を形成してこの中空部内に第一の半導体素子
を設け、該第一の半導体素子の裏側に第二の半導体素子
を設けているので、半導体装置全体が小型化、軽量化さ
れたものとなる。また、前記第一の半導体素子を受光素
子面を有した受光素子とし、前記第二の半導体素子を前
記受光素子を駆動するための駆動素子とすれば、該半導
体装置が受光素子、すなわちイメージセンサと、これを
駆動する素子をマウントしたものとなり、したがって例
えばこれを用いたＣＣＤシステムの小型化、軽量化が可
能になる。また、前記第一の半導体素子を受光素子面を
有した受光素子とし、前記第二の半導体素子をペルチェ
素子とすれば、前述したものと同様にこれを用いたＣＣ
Ｄシステムの小型化、軽量化が可能になるとともに、ペ
ルチェ素子の冷却効果によって前記受光素子がその動作
に伴い発熱し、特性が低下するのが防止される。According to the semiconductor device of the present invention, semiconductor elements are provided on both front and back sides of the substrate, and a hollow portion is formed on one surface side of the substrate, and the first semiconductor element is provided in the hollow portion. Since the second semiconductor element is provided on the back side of the first semiconductor element, the entire semiconductor device can be made smaller and lighter. Further, when the first semiconductor element is a light receiving element having a light receiving element surface and the second semiconductor element is a driving element for driving the light receiving element, the semiconductor device is a light receiving element, that is, an image sensor. Then, an element for driving the same is mounted, so that, for example, the size and weight of a CCD system using the same can be reduced. If the first semiconductor element is a light receiving element having a light receiving element surface and the second semiconductor element is a Peltier element, a CC using the same is used as described above.
The D system can be reduced in size and weight, and the cooling effect of the Peltier element can prevent the light receiving element from generating heat due to its operation and deteriorating the characteristics.
【０００６】[0006]
【実施例】以下、本発明の半導体装置を詳しく説明す
る。図１は本発明の半導体装置の第一実施例を示す図で
ある。図１に示した半導体装置は、本発明をＣＣＤシス
テムにおけるイメージセンサに適用した場合の実施例で
あり、図１において符号１はエポキシ樹脂等のモールド
樹脂からなる基体である。この基体１には表裏面が形成
されており、その一方の面側には凹部２が形成され、こ
の凹部２には第一の半導体素子、この実施例では受光素
子３（すなわちＣＣＤイメージセンサチップ）が設けら
れている。この受光素子３は、その受光素子面３ａを外
側に向けて前記凹部２内に配置されたものである。ま
た、該凹部２には、受光素子３の受光素子面３ａを封止
するようにして凹部２の開口部に透明シールガラス４が
設けられており、これによって該凹部３は中空部となっ
ている。The semiconductor device of the present invention will be described in detail below. FIG. 1 is a diagram showing a first embodiment of a semiconductor device of the present invention. The semiconductor device shown in FIG. 1 is an embodiment in which the present invention is applied to an image sensor in a CCD system. In FIG. 1, reference numeral 1 is a base made of a mold resin such as epoxy resin. The substrate 1 is formed with front and back surfaces, and a concave portion 2 is formed on one surface side thereof. The concave portion 2 has a first semiconductor element, in this embodiment, a light receiving element 3 (that is, a CCD image sensor chip). ) Is provided. The light receiving element 3 is arranged in the recess 2 with the light receiving element surface 3a facing outward. The recess 2 is provided with a transparent sealing glass 4 in the opening of the recess 2 so as to seal the light receiving element surface 3a of the light receiving element 3, whereby the recess 3 becomes a hollow portion. There is.
【０００７】また、受光素子３の裏面側には第二の半導
体素子、この実施例では前記受光素子３を駆動するため
の駆動素子５が基体１中に埋設されている。この駆動素
子５は、リードフレーム材６のダイパッド７上に配置固
定され、さらにリードフレーム６のインナーリード部８
ａにボンディングワイヤ９を介して接続されたもので、
後述するようにリードフレーム材６とともにこれが埋設
されるよう樹脂成形がなされ、基体１が形成されること
によって同時に駆動素子５が基体１に固定されたもので
ある。A second semiconductor element, which is a drive element 5 for driving the light receiving element 3 in this embodiment, is embedded in the substrate 1 on the back surface side of the light receiving element 3. The drive element 5 is arranged and fixed on the die pad 7 of the lead frame material 6, and the inner lead portion 8 of the lead frame 6 is further provided.
which is connected to a through a bonding wire 9,
As will be described later, resin molding is performed so that the lead frame material 6 and the lead frame material 6 are embedded, and the drive element 5 is simultaneously fixed to the base body 1 by forming the base body 1.
【０００８】また、受光素子３には、その受光素子面３
ａ側にＴＡＢリード１０が接続されており、このＴＡＢ
リード１０は前記リードフレーム材６のアウターリード
８に接続されている。そして、これにより受光素子３と
アウターリード８とは、ＴＡＢリード１０によって電気
的かつ機械的に接続されたものとなっている。なお、こ
のＴＡＢリード１０の接続については、後述するように
ＴＡＢ（TapeAutomated Bonding ）によってなされてい
る。The light receiving element 3 has a light receiving element surface 3
The TAB lead 10 is connected to the a side,
The lead 10 is connected to the outer lead 8 of the lead frame material 6. As a result, the light receiving element 3 and the outer lead 8 are electrically and mechanically connected by the TAB lead 10. The TAB lead 10 is connected by TAB (Tape Automated Bonding) as described later.
【０００９】このような構成の半導体装置を製造するに
は、まず、図２（ａ）に示すようにリードフレーム材６
を用意し、これのダイパッド７上に駆動素子５をダイボ
ンディングし、さらに該駆動素子５とリードフレーム材
６のインナーリード部８ａとをボンディングワイヤ９に
よって接続する。ここで、リードフレーム材６として
は、厚さが０．１５ｍｍの４２アロイ（鉄−ニッケル４
２％合金）にＰｄ−Ｎｉメッキを０．５μｍ程度の厚さ
に施したものが好適に用いられる。また、ダイボンディ
ングについては、例えばエポキシ系Ａｇペーストを用
い、１５０℃、１時間のキュアで行う。さらに、ボンデ
ィングワイヤ９としては、外径２３〜２５μｍ程度のＡ
ｕワイヤを用い、その接続についてはチップの実温で２
５０℃程度にて行う。In order to manufacture a semiconductor device having such a structure, first, as shown in FIG.
Then, the drive element 5 is die-bonded onto the die pad 7 thereof, and the drive element 5 and the inner lead portion 8a of the lead frame material 6 are connected by a bonding wire 9. Here, as the lead frame material 6, 42 alloy (iron-nickel 4
2% alloy) plated with Pd-Ni to a thickness of about 0.5 μm is preferably used. The die bonding is performed by using an epoxy-based Ag paste and curing at 150 ° C. for 1 hour. Further, as the bonding wire 9, an A having an outer diameter of about 23 to 25 μm is used.
Use u-wires and connect them at the actual temperature of the chip.
Perform at about 50 ° C.
【００１０】次に、得られたリードフレーム材６上の駆
動素子５が内部に埋設されるようにしてトランスファー
モールドを行い、図２（ｂ）に示すように駆動素子５お
よびリードフレーム材６を固定した基体１を成形する。
ここで、基体１の材質としては例えばエポキシ樹脂が用
いられ、また、成形に際しては例えば１７５℃、４時間
のポストキュアを行う。次いで、ダムおよびレジンカッ
トを行って基体１の所定位置、すなわち駆動素子５の裏
面側に凹部２を形成する。なお、凹部２については、そ
の中に受光素子３を十分な余裕をもって収納できるよう
な大きさとする。Next, transfer molding is performed so that the driving element 5 on the obtained lead frame material 6 is embedded inside, and the driving element 5 and the lead frame material 6 are formed as shown in FIG. 2B. The fixed base 1 is molded.
Here, for example, an epoxy resin is used as the material of the base body 1, and post-curing is performed at 175 ° C. for 4 hours during molding. Next, a dam and a resin cut are performed to form the recess 2 at a predetermined position of the base 1, that is, on the back surface side of the drive element 5. The concave portion 2 has a size such that the light receiving element 3 can be accommodated therein with a sufficient margin.
【００１１】次いで、図２（ｃ）に示すように前記凹部
２内に、受光素子面３ａが凹部２の開口部側に向くよう
にして受光素子３を収納配置し、該受光素子３を基体１
にダイボンディングする。ダイボンディングについて
は、前記駆動素子５の場合と同様にエポキシ系絶縁性ペ
ーストを用い、１５０℃、１時間のキュアで行う。次い
で、図２（ｄ）に示すようにＴＡＢボンディングを行
い、受光素子３とリードフレーム材６のアウターリード
８とをＴＡＢリード１０によって接続し、さらにその接
続部上を保護用樹脂１１で被覆する。ここで、この接続
において、該ＴＡＢリード１０と受光素子３との接続に
ついてはシングルポイントボンドによって行い、アウタ
ーリード８との接続についてはシングルポイントボン
ド、あるいは異方性導電膜を介したギャングボンドによ
って行う。また、保護用樹脂１１を被覆するにあたり、
特にアウターリード８とＴＡＢリード１０との接続部に
おいてはポッティングにより保護用樹脂１１を被覆固定
する。この保護用樹脂は、アクリル系又はエポキシ系接
着剤が適当であり、熱硬化（１２０〜１５０℃、１〜２
時間）、又は紫外線照射硬化（１０００〜２０００ｍＪ
／ｃｍ2 ）、又は紫外線照射＋熱硬化（１０００〜２０
００ｍＪ／ｃｍ2 ＋１２０〜１５０℃、１時間）処理す
る。この処理は後のシールガラス時のキュアと一緒にし
てもよい。Next, as shown in FIG. 2 (c), the light receiving element 3 is housed in the concave portion 2 so that the light receiving element surface 3a faces the opening side of the concave portion 2, and the light receiving element 3 is placed on the base body. 1
Die bond to. Die bonding is performed by using an epoxy-based insulating paste and curing at 150 ° C. for 1 hour as in the case of the driving element 5. Next, as shown in FIG. 2D, TAB bonding is performed to connect the light receiving element 3 and the outer lead 8 of the lead frame material 6 with the TAB lead 10, and further cover the connecting portion with the protective resin 11. . Here, in this connection, the TAB lead 10 and the light receiving element 3 are connected by a single point bond, and the outer lead 8 is connected by a single point bond or a gang bond via an anisotropic conductive film. To do. Moreover, in coating the protective resin 11,
In particular, the protective resin 11 is covered and fixed by potting at the connecting portion between the outer lead 8 and the TAB lead 10. Acrylic or epoxy adhesives are suitable for this protective resin, and they are thermoset (120 to 150 ° C., 1 to 2).
Time) or UV irradiation curing (1000-2000 mJ
/ Cm 2 ) or ultraviolet irradiation + heat curing (1000 to 20 )
00 mJ / cm 2 +120 to 150 ° C., 1 hour). This treatment may be combined with the curing at the time of sealing glass later.
【００１２】次いで、図１に示すように凹部２の開口部
を透明シールガラス４で覆って凹部２内を封止し、これ
により凹部２内を中空部とする。なお、透明シールガラ
ス４のシーリングについては、Ａステージシーラーまた
はＢステージシーラーを用い、１５０℃、２時間のキュ
アによって行う。その後、リードフレーム材６のアウタ
ーリード８を所定角度に曲げ、ステイカットして本実施
例の半導体装置を得る。Then, as shown in FIG. 1, the opening of the recess 2 is covered with a transparent sealing glass 4 to seal the inside of the recess 2 and thereby make the inside of the recess 2 a hollow portion. The transparent seal glass 4 is sealed by using an A stage sealer or a B stage sealer and curing at 150 ° C. for 2 hours. After that, the outer leads 8 of the lead frame material 6 are bent at a predetermined angle and stay cut to obtain the semiconductor device of this embodiment.
【００１３】このようにして得られた半導体装置にあっ
ては、基体１の一方の面側の中空部内に受光素子３を設
け、その裏面側に該受光素子３の駆動素子５を設けてい
るので、ベアチップ化が可能なＣＣＤイメージセンサと
なり、したがってこれを用いたＣＣＤシステム全体の小
型化、軽量化、コストダウン化を図り得るものとなる。
また、前述した製造方法においては、基体１の成形後の
ポストキュアを１７５℃、４時間の条件で行ったが、そ
の後に受光素子３のダイボンディングにおけるキュア、
透明シールガラス４のシーリングにおけるキュアを行う
ことから、前述した条件より短時間で前記基体１のポス
トキュアを行うこともできる。In the semiconductor device thus obtained, the light receiving element 3 is provided in the hollow portion on the one surface side of the base body 1, and the driving element 5 of the light receiving element 3 is provided on the back surface side thereof. Therefore, the CCD image sensor can be formed into a bare chip, and therefore, the overall size, weight and cost of the CCD system using the CCD image sensor can be reduced.
In the above-described manufacturing method, post-curing of the base body 1 was performed after molding at 175 ° C. for 4 hours.
Since the transparent sealing glass 4 is cured during sealing, post-curing of the substrate 1 can be performed in a shorter time than the above-mentioned conditions.
【００１４】なお、前記実施例では凹部２を透明シール
ガラス４によって覆い、これによって凹部２を中空部化
するとともに該中空部内の受光素子３を封止するように
したが、例えばこの透明シールガラス４に代えて図１中
二点鎖線で示す透明プラスチックリッド１２を用い、こ
れにより凹部２を覆って中空部を形成するとともに、受
光素子３を封止するようにしてもよく、さらには凹部２
内にアクリル系樹脂やエポキシ系樹脂、シリコーン系樹
脂等の透明樹脂をポッティングによって充填し、受光素
子３を封止するようにしてもよい。また、この場合に透
明樹脂としては、熱硬化型、紫外線照射硬化型、あるい
は紫外線照射および加熱による硬化型のいずれの樹脂を
も用いることが可能である。また、前記実施例では駆動
素子５を一つ設けたが、二つ、あるいはそれ以上の駆動
素子５を基体１内に設けてもよいのはもちろんである。In the above-described embodiment, the recess 2 is covered with the transparent seal glass 4, thereby making the recess 2 hollow and sealing the light receiving element 3 in the hollow. For example, this transparent seal glass 4 may be replaced by a transparent plastic lid 12 shown by a chain double-dashed line in FIG. 1 to cover the concave portion 2 to form a hollow portion and to seal the light receiving element 3.
The light receiving element 3 may be sealed by filling a transparent resin such as an acrylic resin, an epoxy resin, or a silicone resin in the inside by potting. Further, in this case, as the transparent resin, it is possible to use any resin of thermosetting type, ultraviolet irradiation curing type, or curing type by ultraviolet irradiation and heating. Further, although one driving element 5 is provided in the above-mentioned embodiment, it is needless to say that two or more driving elements 5 may be provided in the base 1.
【００１５】図３は本発明の半導体装置の第二実施例を
示す図である。図３に示した半導体装置が図１に示した
半導体装置と異なるところは、駆動素子５に代えてペル
チェ素子２０を設けた点にある。ペルチェ素子２０は、
二つの異なった導体もしくは半導体をつないでこれに直
流電流を流すとそれぞれの接合部においてジュール熱以
外の熱の吸収、または発生が見られるという、いわゆる
ペルチェ効果を利用したものであり、直流電流によって
冷却・加熱・温度制御を自由に行うことのできる半導体
素子である。FIG. 3 is a diagram showing a second embodiment of the semiconductor device of the present invention. The semiconductor device shown in FIG. 3 is different from the semiconductor device shown in FIG. 1 in that a Peltier element 20 is provided instead of the driving element 5. The Peltier device 20 is
This is based on the so-called Peltier effect, in which two different conductors or semiconductors are connected and a direct current is applied to them to absorb or generate heat other than Joule heat at each junction. It is a semiconductor device that can freely control cooling, heating, and temperature.
【００１６】そして、本実施例においてはこのペルチェ
素子２０を、その放熱側の面（放熱面）２０ａが基体１
の外側に向き、吸熱側、すなわち冷却側の面（吸熱面）
２０ｂが前記受光素子３の裏面に向くようにして基体１
内に配置している。なお、この実施例においては、ペル
チェ素子２０はその放熱面２０ａを基体１の外部に臨ま
せるようにして基体１内に配置されており、これによっ
てペルチェ素子２０の動作に伴い発生した熱が、基体１
内に蓄積されないようになっている。In this embodiment, the Peltier element 20 has a heat radiating surface (heat radiating surface) 20a on which the substrate 1 is formed.
Facing toward the outside of the heat absorption side, that is, the cooling side surface (heat absorption surface)
The substrate 1 is so arranged that 20b faces the back surface of the light receiving element 3.
It is placed inside. In this embodiment, the Peltier element 20 is arranged in the base 1 so that its heat radiation surface 20a is exposed to the outside of the base 1, so that the heat generated by the operation of the Peltier element 20 is Base 1
It is designed not to be accumulated inside.
【００１７】このような構成の半導体装置にあっては、
受光素子３がその動作に伴い発熱しても、ペルチェ素子
２０が動作することによってその熱を奪う（吸収する）
ことから、受光素子３周辺に熱が蓄積されることがほと
んどなくなり、これにより受光素子３の特性の低下、具
体的には白キズ等の画質欠陥の発生を防止することがで
きる。また、図３に示した半導体装置において、受光素
子３に代えて他のパワー半導体素子を配設してもよく、
その場合にもペルチェ素子２０が該パワー半導体素子の
動作に伴う熱を吸収することにより、パワー半導体素子
の温度上昇による特性の低下を防止することができる。
なお、このように受光素子３に代えてパワー半導体素子
を用いた場合には、該パワー半導体素子を透明シールガ
ラス４や透明樹脂で封止する必要がないのはもちろんで
ある。In the semiconductor device having such a structure,
Even if the light receiving element 3 generates heat due to its operation, the heat is absorbed (absorbed) by the operation of the Peltier element 20.
As a result, heat is hardly accumulated around the light receiving element 3, which can prevent the deterioration of the characteristics of the light receiving element 3, specifically, the occurrence of image defects such as white scratches. Further, in the semiconductor device shown in FIG. 3, another power semiconductor element may be provided instead of the light receiving element 3.
Even in that case, the Peltier element 20 absorbs heat accompanying the operation of the power semiconductor element, so that it is possible to prevent deterioration of characteristics due to temperature rise of the power semiconductor element.
When a power semiconductor element is used instead of the light receiving element 3 as described above, it is not necessary to seal the power semiconductor element with the transparent seal glass 4 or the transparent resin.
【００１８】図４は本発明の半導体装置の第三実施例を
示す図である。図４に示した半導体装置が図１に示した
半導体装置と異なるところは、モールド樹脂からなる基
体１に代えてガラスエポキシ基板やＢＴレジン基板等の
プリント配線基板からなる基体３０を用いている点であ
る。この基体３０には、その両面にそれぞれ二段に凹ん
で形成された凹部３１が形成されており、その一方の面
側における凹部３１の深い部分には受光素子３が、他方
の面側における凹部３１の深い部分には駆動素子５がそ
れぞれ配置固定されている。また、この基体３０には、
通常の配線基板と同様にその両面間を貫通する貫通孔３
２が複数形成されており、これによって素子間の導通が
なされるようになっている。両面の凹部３１の浅い部分
には通常の配線パターン（図示略）が形成されており、
そのインナーリード部（図示略）と受光素子３又は駆動
素子５とはワイヤーボンディングで結線されている。FIG. 4 is a diagram showing a third embodiment of the semiconductor device of the present invention. The semiconductor device shown in FIG. 4 is different from the semiconductor device shown in FIG. 1 in that a substrate 30 made of a printed wiring board such as a glass epoxy substrate or a BT resin substrate is used instead of the substrate 1 made of mold resin. Is. The base body 30 has recesses 31 formed on both sides thereof so as to be recessed in two steps. The light receiving element 3 is formed in a deep portion of the recess 31 on one surface side and the recess portion on the other surface side. The drive elements 5 are arranged and fixed in the deep portions of 31. Further, the base body 30 includes
Through-hole 3 penetrating between both surfaces as in a normal wiring board
A plurality of 2 are formed so that the elements can be electrically connected to each other. A normal wiring pattern (not shown) is formed on the shallow portions of the recesses 31 on both sides.
The inner lead portion (not shown) and the light receiving element 3 or the driving element 5 are connected by wire bonding.
【００１９】なお、この半導体装置においても受光素子
３側では、図４に示すように透明シールガラス４または
二点鎖線で示す透明プラスチックリッド１２で凹部３１
が覆われることによって受光素子３が封止され、あるい
は凹部３１内にアクリル系、エポキシ系又はシリコーン
系の透明樹脂がポッティングされることによって受光素
子３が直接封止されるようになっている。また、駆動素
子５側では、これを覆うようにして凹部３１の浅い部分
までアクリル系又はエポキシ系の樹脂がポッティングに
より充填されており、これによって駆動素子５も封止さ
れている。なお、この製法では、駆動素子５の結線およ
び樹脂ポッティング封止が先に行われることは言うまで
もない。Also in this semiconductor device, on the light receiving element 3 side, as shown in FIG. 4, the recess 31 is formed by the transparent seal glass 4 or the transparent plastic lid 12 shown by the chain double-dashed line.
The light receiving element 3 is sealed by covering it, or the light receiving element 3 is directly sealed by potting an acrylic, epoxy, or silicone transparent resin in the recess 31. Further, on the drive element 5 side, acrylic resin or epoxy resin is filled by potting up to the shallow portion of the recess 31 so as to cover the drive element 5, and the drive element 5 is also sealed thereby. In this manufacturing method, it goes without saying that the connection of the driving element 5 and the resin potting sealing are performed first.
【００２０】このような半導体装置にあっても、基体３
０の一方の面側に受光素子３を設け、その裏面側に該受
光素子３の駆動素子５を設けているので、図１に示した
半導体装置と同様にベアチップ化が可能なＣＣＤイメー
ジセンサとなり、したがってＣＣＤシステム全体の小型
化、軽量化、コストダウン化を図り得るものとなる。な
お、図４に示したようにガラスエポキシ基板やＢＴレジ
ン基板等の配線基板からなる基体３０を用いた半導体装
置においても、駆動素子５に代えて前記ペルチェ素子２
０を設けてもよく、また、ペルチェ素子２０を設けた場
合にはさらに受光素子３に代えてパワー半導体素子を設
けてもよい。Even in such a semiconductor device, the base 3
0 is provided with the light receiving element 3 on one surface side thereof and the driving element 5 of the light receiving element 3 is provided on the back surface side thereof, which is a CCD image sensor capable of forming a bare chip like the semiconductor device shown in FIG. Therefore, the CCD system as a whole can be reduced in size, weight and cost. Even in the semiconductor device using the base body 30 made of a wiring board such as a glass epoxy board or a BT resin board as shown in FIG. 4, the Peltier element 2 is used instead of the driving element 5.
0 may be provided, and when the Peltier element 20 is provided, a power semiconductor element may be provided instead of the light receiving element 3.
【００２１】[0021]
【発明の効果】以上説明したように本発明の半導体装置
は、基体の表裏両側にそれぞれ半導体素子を設け、しか
も基体の一方の面側には中空部を形成してこの中空部内
に第一の半導体素子を設け、該第一の半導体素子の裏側
に第二の半導体素子を設けたものであるから、半導体装
置全体が小型化、軽量化したものとなり、したがってこ
の半導体装置を組み込んだシステム等を小型化、軽量化
することができる。As described above, in the semiconductor device of the present invention, semiconductor elements are provided on both front and back sides of the base, and a hollow portion is formed on one surface side of the base, and the first portion is provided in the hollow portion. Since the semiconductor element is provided and the second semiconductor element is provided on the back side of the first semiconductor element, the entire semiconductor device is reduced in size and weight. Therefore, a system incorporating this semiconductor device It can be made smaller and lighter.
【００２２】また、第一の半導体素子を受光素子とし、
第二の半導体素子を受光素子のための駆動素子とすれ
ば、該半導体装置は受光素子、すなわちイメージセンサ
とこれを駆動する素子とをマウントしたベアチップ化が
可能なＣＣＤイメージセンサとなり、したがってこれを
用いるＣＣＤシステムを小型化、軽量化することができ
るとともに、従来イメージセンサ部のみがベアチップ化
が難しく、したがってＣＣＤシステム全体の生産性を損
なっていた問題が解消され、これにより小型化、軽量化
が実現し、生産性が向上してそのコストダウンを図るこ
とができる。The first semiconductor element is used as a light receiving element,
If the second semiconductor element is used as a drive element for the light receiving element, the semiconductor device becomes a CCD image sensor capable of forming a bare chip by mounting the light receiving element, that is, the image sensor and the element for driving the image sensor. It is possible to reduce the size and weight of the CCD system to be used, and it is possible to solve the problem that it is difficult to form a bare chip only in the conventional image sensor unit, and thus the productivity of the entire CCD system is impaired. This can be realized, productivity can be improved, and the cost can be reduced.
【００２３】また、第一の半導体素子を受光素子とし、
第二の半導体素子をペルチェ素子とすれば、ＣＣＤシス
テムを小型化、軽量化することができるとともに、ペル
チェ素子の冷却効果によって受光素子がその動作に伴い
発熱し、特性が低下するのを防止することができ、これ
により例えば、１インチ、２／３インチというように大
きくしたがって発熱量が多いためセラミックス型のパッ
ケージを用いなくてはならなかったＣＣＤイメージセン
サにあっても、ペルチェ素子によってその熱蓄積を抑制
することにより、モールド型にしても特性が低下しこれ
によって白キズ等の画質欠陥が生じることを防止するこ
とができる。さらに、第一の半導体素子をパワー素子と
し、第二の半導体素子をペルチェ素子とすれば、ペルチ
ェ素子の熱吸収でパワー半導体素子の温度上昇による特
性劣化を防止することができる。In addition, the first semiconductor element is a light receiving element,
If the second semiconductor element is a Peltier element, the CCD system can be made smaller and lighter, and at the same time, the cooling effect of the Peltier element prevents the light receiving element from generating heat due to its operation and preventing the characteristics from deteriorating. As a result, even if the CCD image sensor has to use a ceramic type package because it is large, for example, 1 inch, 2/3 inch, and thus has a large amount of heat generation, the heat generated by the Peltier element is increased. By suppressing the accumulation, it is possible to prevent the deterioration of the characteristics even in the case of the mold type and the occurrence of the image defect such as the white defect. Further, if the first semiconductor element is a power element and the second semiconductor element is a Peltier element, it is possible to prevent characteristic deterioration due to temperature rise of the power semiconductor element due to heat absorption of the Peltier element.
【図１】本発明の半導体装置の第一実施例の概略構成を
示す断面図である。FIG. 1 is a sectional view showing a schematic configuration of a first embodiment of a semiconductor device of the present invention.
【図２】（ａ）〜（ｄ）は図１に示した半導体装置の製
造工程を工程順に説明するための断面図である。2A to 2D are cross-sectional views for explaining the manufacturing process of the semiconductor device shown in FIG. 1 in the order of processes.
【図３】本発明の半導体装置の第二実施例の概略構成を
示す断面図である。FIG. 3 is a sectional view showing a schematic configuration of a second embodiment of the semiconductor device of the present invention.
【図４】本発明の半導体装置の第三実施例の概略構成を
示す断面図である。FIG. 4 is a sectional view showing a schematic configuration of a third embodiment of the semiconductor device of the present invention.
１ 基体 ２ 凹部（中空部） ３ 受光素子（第一の半導体素子） ３ａ 受光素子面 ５ 駆動素子（第二の半導体素子） ２０ ペルチェ素子 ２０ａ 放熱面 ２０ｂ 冷却面 ３０ 基体 ３１ 凹部（中空部） DESCRIPTION OF SYMBOLS 1 Base 2 Recess (hollow part) 3 Light receiving element (first semiconductor element) 3a Light receiving element surface 5 Driving element (second semiconductor element) 20 Peltier element 20a Heat dissipation surface 20b Cooling surface 30 Base 31 Recess (hollow part)
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 25/18 27/14 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 25/18 27/14
Claims (7)
部が形成され、該中空部内に第一の半導体素子が設けら
れ、該第一の半導体素子の裏側に第二の半導体素子が設
けられてなることを特徴とする半導体装置。1. A hollow portion is formed on one surface side of a substrate having front and back surfaces, a first semiconductor element is provided in the hollow portion, and a second semiconductor element is provided on the back side of the first semiconductor element. A semiconductor device characterized by being provided.
記第一の半導体素子が受光素子面を有してなる受光素子
であり、前記第二の半導体素子が前記受光素子を駆動す
るための駆動素子であり、前記受光素子がその受光素子
面を外側に向けて前記中空部内に配置され、該受光素子
面が透明材料で封止されてなることを特徴とする半導体
装置。2. The semiconductor device according to claim 1, wherein the first semiconductor element is a light receiving element having a light receiving element surface, and the second semiconductor element is a drive for driving the light receiving element. A semiconductor device, which is an element, wherein the light receiving element is arranged in the hollow portion with the light receiving element surface facing outward, and the light receiving element surface is sealed with a transparent material.
記第一の半導体素子が受光素子面を有してなる受光素子
であり、前記第二の半導体素子がペルチェ素子であり、
該ペルチェ素子が前記受光素子の裏側に配設されるとと
もに、その冷却面を受光素子側に向け、かつ放熱面を外
側に向けて配設され、前記受光素子がその受光素子面を
外側に向けて前記中空部内に配置され、該受光素子面が
透明材料で封止されてなることを特徴とする半導体装
置。3. The semiconductor device according to claim 1, wherein the first semiconductor element is a light receiving element having a light receiving element surface, and the second semiconductor element is a Peltier element.
The Peltier element is disposed on the back side of the light receiving element, the cooling surface thereof is directed to the light receiving element side, and the heat radiation surface is directed to the outer side, and the light receiving element is directed to the outer side of the light receiving element. A semiconductor device, wherein the light receiving element surface is sealed with a transparent material.
おいて、前記基体がモールド樹脂によって形成されてな
ることを特徴とする半導体装置。4. The semiconductor device according to claim 1, 2 or 3, wherein the base is formed of a mold resin.
おいて、前記基体がガラスエポキシ基板又はＢＴレジン
基板等のプリント配線基板から形成されてなることを特
徴とする半導体装置。5. The semiconductor device according to claim 1, 2 or 3, wherein the base is formed of a printed wiring board such as a glass epoxy board or a BT resin board.
て、前記受光素子面がシールガラス又は透明プラスチッ
クリッドで中空シールされていることを特徴とする半導
体装置。6. The semiconductor device according to claim 2, wherein the light receiving element surface is hollow-sealed with a sealing glass or a transparent plastic lid.
記駆動素子が樹脂によってモールド封止されていること
を特徴とする半導体装置。7. The semiconductor device according to claim 2, wherein the drive element is molded and sealed with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24009894A JP3239640B2 (en) | 1994-10-04 | 1994-10-04 | Semiconductor device manufacturing method and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24009894A JP3239640B2 (en) | 1994-10-04 | 1994-10-04 | Semiconductor device manufacturing method and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08107167A true JPH08107167A (en) | 1996-04-23 |
| JP3239640B2 JP3239640B2 (en) | 2001-12-17 |
Family
ID=17054469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24009894A Expired - Fee Related JP3239640B2 (en) | 1994-10-04 | 1994-10-04 | Semiconductor device manufacturing method and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3239640B2 (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10163253A (en) * | 1996-12-03 | 1998-06-19 | Matsushita Electric Ind Co Ltd | Camera for alignment, method and apparatus for aligning electronic component |
| FR2827467A1 (en) * | 2001-07-13 | 2003-01-17 | Kingpak Tech Inc | Compact assembly forming component of image sensor, stacks and interconnects image sensor chip, integrated circuit and substrate on PCB |
| FR2827468A1 (en) * | 2001-07-13 | 2003-01-17 | Kingpak Tech Inc | Stacked structure for an image sensor has substrates forming an enclosed space in which sensor is located |
| FR2827425A1 (en) * | 2001-07-13 | 2003-01-17 | Kingpak Tech Inc | Stack arrangement for an image sensor chip for electrically connecting to a circuit board |
| JP2003124500A (en) * | 2001-10-15 | 2003-04-25 | Sharp Corp | Optocoupler |
| KR20040009085A (en) * | 2002-07-22 | 2004-01-31 | 에스티에스반도체통신 주식회사 | Multi chip package and manufacturing method the same |
| KR100428950B1 (en) * | 2001-05-09 | 2004-04-28 | 킹팍 테크놀로지 인코포레이티드 | Stacked structure of an image sensor and method for manufacturing the same |
| KR100428949B1 (en) * | 2001-05-09 | 2004-04-28 | 킹팍 테크놀로지 인코포레이티드 | Stacked package structure of image sensor |
| JP2006269784A (en) * | 2005-03-24 | 2006-10-05 | Konica Minolta Opto Inc | Imaging apparatus |
| US7485848B2 (en) | 2003-10-10 | 2009-02-03 | Panasonic Corporation | Optical device and production method thereof |
| JP4759677B2 (en) * | 2004-06-29 | 2011-08-31 | ラウンド ロック リサーチ リミテッド ライアビリティー カンパニー | Packaged microelectronic imager and method for packaging a microelectronic imager |
-
1994
- 1994-10-04 JP JP24009894A patent/JP3239640B2/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10163253A (en) * | 1996-12-03 | 1998-06-19 | Matsushita Electric Ind Co Ltd | Camera for alignment, method and apparatus for aligning electronic component |
| KR100428950B1 (en) * | 2001-05-09 | 2004-04-28 | 킹팍 테크놀로지 인코포레이티드 | Stacked structure of an image sensor and method for manufacturing the same |
| KR100428949B1 (en) * | 2001-05-09 | 2004-04-28 | 킹팍 테크놀로지 인코포레이티드 | Stacked package structure of image sensor |
| FR2827467A1 (en) * | 2001-07-13 | 2003-01-17 | Kingpak Tech Inc | Compact assembly forming component of image sensor, stacks and interconnects image sensor chip, integrated circuit and substrate on PCB |
| FR2827468A1 (en) * | 2001-07-13 | 2003-01-17 | Kingpak Tech Inc | Stacked structure for an image sensor has substrates forming an enclosed space in which sensor is located |
| FR2827425A1 (en) * | 2001-07-13 | 2003-01-17 | Kingpak Tech Inc | Stack arrangement for an image sensor chip for electrically connecting to a circuit board |
| JP2003124500A (en) * | 2001-10-15 | 2003-04-25 | Sharp Corp | Optocoupler |
| KR20040009085A (en) * | 2002-07-22 | 2004-01-31 | 에스티에스반도체통신 주식회사 | Multi chip package and manufacturing method the same |
| US7485848B2 (en) | 2003-10-10 | 2009-02-03 | Panasonic Corporation | Optical device and production method thereof |
| US7755030B2 (en) | 2003-10-10 | 2010-07-13 | Panasonic Corporation | Optical device including a wiring having a reentrant cavity |
| JP4759677B2 (en) * | 2004-06-29 | 2011-08-31 | ラウンド ロック リサーチ リミテッド ライアビリティー カンパニー | Packaged microelectronic imager and method for packaging a microelectronic imager |
| JP2006269784A (en) * | 2005-03-24 | 2006-10-05 | Konica Minolta Opto Inc | Imaging apparatus |
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| Publication number | Publication date |
|---|---|
| JP3239640B2 (en) | 2001-12-17 |
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