JPH0810303B2 - Liquid crystal display - Google Patents
Liquid crystal displayInfo
- Publication number
- JPH0810303B2 JPH0810303B2 JP25323190A JP25323190A JPH0810303B2 JP H0810303 B2 JPH0810303 B2 JP H0810303B2 JP 25323190 A JP25323190 A JP 25323190A JP 25323190 A JP25323190 A JP 25323190A JP H0810303 B2 JPH0810303 B2 JP H0810303B2
- Authority
- JP
- Japan
- Prior art keywords
- input signal
- liquid crystal
- semiconductor layer
- signal supply
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、薄膜トランジスタをスイッチング素子とし
てもちいたアクティブ・マトリクス型液晶表示装置に関
するものである。Description: TECHNICAL FIELD The present invention relates to an active matrix type liquid crystal display device using a thin film transistor as a switching element.
従来の技術 近年、微細加工技術、液晶材料、及び実装技術の進歩
により、１〜５インチ程度の小型サイズではあるが良好
なテレビ画像を得られる液晶表示装置が商業ベースで生
産されるようになってきている。2. Description of the Related Art In recent years, advances in microfabrication technology, liquid crystal materials, and packaging technology have led to commercial production of liquid crystal display devices that are small in size of about 1 to 5 inches but that can provide good TV images. Is coming.
このような液晶表示装置は、スイッチング素子を備え
た画像表示部に走査信号とデータ信号を供給するため、
外部から駆動用ICを接続する必要があるが、その接続方
法は次の２つが主流である。その１つは液晶表示装置を
構成する２つの透明基板のうち一方の基板上に形成され
た走査信号線の端子群及びデータ信号線の端子群に、例
えば、ポリイミド樹脂薄膜ベースに銅薄膜線を多数形成
した接続フィルムを導電性接着剤等で圧接して外部の駆
動用ICからの信号を供給する、いわゆるフィルムキャリ
ア方式であり、もう１つは、液晶表示装置を構成する一
方の基板上の画像表示部周辺に形成した実装端子に何ら
かの方法で直接駆動用ICを実装するCOG（チップ・オン
・グラス）方式である。Since such a liquid crystal display device supplies a scanning signal and a data signal to the image display unit having a switching element,
It is necessary to connect the driving IC from the outside, but the following two main methods of connection are the mainstream. One of them is a scanning signal line terminal group and a data signal line terminal group formed on one of two transparent substrates constituting a liquid crystal display device, for example, a copper thin film line on a polyimide resin thin film base. A so-called film carrier method is used in which a large number of connection films are pressed against each other with a conductive adhesive or the like to supply a signal from an external driving IC, and the other is on one substrate that constitutes a liquid crystal display device. This is a COG (chip on glass) method in which the driving IC is directly mounted on the mounting terminals formed around the image display part by some method.
現在販売されている液晶テレビのほとんどは前者のフ
ィルムキャリア方式を採用したものであるが、ビデオカ
メラのビューファインダーなどに使われる１インチ程度
の超小型液晶パネルなどでは、省スペースのために後者
のCOG方式が採用されることが増えてきている。Most of the liquid crystal televisions currently on sale use the former film carrier method, but the 1 inch ultra-small liquid crystal panel used for viewfinders of video cameras, etc. uses the latter to save space. The COG method is increasingly adopted.
発明が解決しようとする課題 しかしながら、上記のCOG実装方式を採用した場合、
第４図に示すように、液晶表示装置を構成する基板40上
の画像表示部41の周辺部に、外部信号供給端子42、複数
の駆動用IC43（破線で図示）を実装するための入力信号
供給用実装端子群44と出力信号供給用実装端子群45、駆
動用IC43に外部信号供給端子42からの各種入力信号を伝
達するための第１の入力信号供給配線46、第１の入力信
号供給配線46と入力信号供給用実装端子群44を接続する
第２の入力信号供給配線47、画像表示部41に走査信号を
供給する走査配線群48とデータ信号を供給するデータ配
線群49をそれぞれ配置する必要がある。この場合、配線
46と配線47は、多数の交差点を生ずることになり、これ
ら交差配線間にある層間絶縁層が静電破壊などによって
何らかの欠陥が発生すると、交差配線間の短絡不良や断
線不良を引き起こすことになり、画像表示部が完全無欠
陥の基板であっても不良品として画像表示装置そのもの
を廃棄せざるをえないという問題点を有していた。However, when the above COG mounting method is adopted,
As shown in FIG. 4, an input signal for mounting an external signal supply terminal 42 and a plurality of driving ICs 43 (shown by broken lines) on the periphery of the image display section 41 on the substrate 40 that constitutes the liquid crystal display device. Supply mounting terminal group 44, output signal supplying mounting terminal group 45, first input signal supply wiring 46 for transmitting various input signals from the external signal supply terminal 42 to the driving IC 43, first input signal supply A second input signal supply wiring 47 that connects the wiring 46 and the mounting terminal group 44 for input signal supply, a scanning wiring group 48 that supplies a scanning signal to the image display unit 41, and a data wiring group 49 that supplies a data signal are arranged respectively. There is a need to. In this case, the wiring
46 and the wiring 47 will cause a large number of intersections, and if any defect occurs due to electrostatic breakdown or the like in the interlayer insulating layer between these intersections, short-circuiting or disconnection between the intersections will occur. However, there is a problem in that the image display apparatus itself must be discarded as a defective product even if the image display unit is a completely defect-free substrate.
課題を解決するための手段 上記問題点を解決するために本発明の液晶表示装置
は、互いに交差した入力信号供給配線間に４層からな
る、層間絶縁膜及び半導体層を形成し、各層絶縁構造と
したものである。Means for Solving the Problems In order to solve the above problems, a liquid crystal display device of the present invention forms an interlayer insulating film and a semiconductor layer consisting of four layers between input signal supply wirings intersecting each other, and each layer insulating structure. It is what
作用 本発明は上記した構造によって、交差した第1,第２の
入力信号供給配線間の絶縁耐圧性能を向上させ、静電破
壊に対する配線の信頼性を確保することが可能になる。Action The present invention has the above-described structure, which makes it possible to improve the withstand voltage performance between the intersecting first and second input signal supply wirings and ensure the reliability of the wirings against electrostatic breakdown.
実施例 以下本発明の一実施例の液晶表示装置について、図面
を参照しながら説明する。Embodiment A liquid crystal display device according to an embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の実施例における単位絵素あたりの平
面図、第２図は周辺IC実装部の入力信号側部分の平面
図、第３図は第１図のＡ−Ａ′断面と第２図のＢ−Ｂ′
断面をそれぞれ示した断面図である。FIG. 1 is a plan view of a unit pixel in an embodiment of the present invention, FIG. 2 is a plan view of an input signal side portion of a peripheral IC mounting portion, and FIG. 3 is a sectional view taken along the line AA ′ of FIG. BB 'in Figure 2
It is sectional drawing which showed each cross section.
第１図において、１はゲート電極、２はソース電極、
３は半導体保護膜、４はドレイン電極、５は絵素電極を
形成する第２の透明電極、６は補助容量を形成する第１
の透明電極、７は絵素電極５とドレイン電極４を接続す
るコンタクトホールである。In FIG. 1, 1 is a gate electrode, 2 is a source electrode,
3 is a semiconductor protective film, 4 is a drain electrode, 5 is a second transparent electrode forming a pixel electrode, and 6 is a first transparent electrode forming an auxiliary capacitance.
, And 7 is a contact hole for connecting the pixel electrode 5 and the drain electrode 4.
第２図において、21は第２のIC入力信号供給配線、22
は第１のIC入力信号供給配線、23はIC出力信号用実装端
子、24はIC出力信号用実装端子23を第２のIC入力信号供
給配線21に接続するコンタクトホール、25は第１のIC入
力信号供給配線22と第２のIC入力信号供給配線を接続す
るコンタクトホール、26は配線交差部に島状に形成した
層間絶縁膜である。In FIG. 2, 21 is the second IC input signal supply wiring, 22
Is the first IC input signal supply wiring, 23 is the IC output signal mounting terminal, 24 is the contact hole that connects the IC output signal mounting terminal 23 to the second IC input signal supply wiring 21, and 25 is the first IC A contact hole connecting the input signal supply wiring 22 and the second IC input signal supply wiring, and 26 are interlayer insulating films formed in an island shape at the wiring intersection.
次に第３図を用いてこれらの断面構造を具体的に説明
する。まず、ガラス基板31上に補助容量を持った絵素部
を形成するため第１の透明電極６となる第１のITO透明
電極32と第１のSiO2絶縁膜33、その上に絵素電極、すな
わち第２の透明電極絵となる第２のITO透明電極34を形
成する。さらに第２のSiO2絶縁膜35を被着する。そし
て、絵素部ではゲート電極１と走査配線に、周辺IC実装
部では第２の入力信号供給配線21となる第１の導電性薄
膜Crを選択的に被着形成した後SiNxからなる第１の層間
絶縁膜36、ａ−Si半導体層37、さらに絵素部では半導体
保護膜３に、周辺IC実装部では島状の層間絶縁膜26、す
なわち第２の層間絶縁膜となる第２のSiNx絶縁膜38を形
成する。さらにn+a-Si層39、絵素部ではソース・ドレイ
ン電極2,4とデータ配線に、周辺IC実装部では第１のIC
入力信号供給配線22となる第２の導電性薄膜MoSi2/Alに
よる配線層を形成することにより、この基板は完成す
る。Next, these sectional structures will be specifically described with reference to FIG. First, the first ITO transparent electrode 32 and the first SiO 2 insulating film 33, which will be the first transparent electrode 6 for forming the pixel portion having the auxiliary capacitance on the glass substrate 31, and the pixel electrode thereon. That is, the second ITO transparent electrode 34 which becomes the second transparent electrode picture is formed. Further, a second SiO 2 insulating film 35 is deposited. Then, the gate electrode 1 and the scanning wiring are selectively deposited on the gate electrode 1 and the scanning wiring in the pixel portion, and the first conductive thin film Cr to be the second input signal supply wiring 21 is selectively deposited and formed in the peripheral IC mounting portion. Interlayer insulating film 36, a-Si semiconductor layer 37, the semiconductor protective film 3 in the pixel portion, and the island-shaped interlayer insulating film 26 in the peripheral IC mounting portion, that is, the second SiNx serving as the second interlayer insulating film. The insulating film 38 is formed. Furthermore, the n + a-Si layer 39, the source / drain electrodes 2 and 4 and the data wiring in the pixel portion, and the first IC in the peripheral IC mounting portion
This substrate is completed by forming a wiring layer of the second conductive thin film MoSi 2 / Al which will be the input signal supply wiring 22.
本実施例における液晶表示装置は、液晶駆動用スイッ
チング素子としてゲート絶縁膜にSiNx膜を用いた逆スタ
ガード型ａ−Si薄膜トランジスタを使い、信号電圧の保
持特性向上のため第1,第２のITO透明電極32,34により、
液晶容量と並列に付加された補助容量を有し、チャンネ
ル部ａ−Si上には絵素部ソース・ドレイン電極2,4とａ
−Si半導体層37とのオーミック接触を得るためのn+a-Si
層39を除去する工程において、チャンネル部のａ−Si半
導体層の膜減りを防止するためSiNxからなるパッシベー
ション膜38を有している。The liquid crystal display device according to the present embodiment uses an inverted staggered a-Si thin film transistor using a SiNx film as a gate insulating film as a liquid crystal driving switching element. The first and second ITO transparent films are used to improve signal voltage retention characteristics. By the electrodes 32, 34,
It has an auxiliary capacitance added in parallel with the liquid crystal capacitance, and the source / drain electrodes 2, 4 and a of the pixel portion are formed on the channel portion a-Si.
N + a-Si for obtaining ohmic contact with the -Si semiconductor layer 37
In the step of removing the layer 39, the passivation film 38 made of SiNx is provided in order to prevent film loss of the a-Si semiconductor layer in the channel portion.
このような構造をとることにより、第２図における第
１のIC入力信号供給配線22と第２のIC入力信号供給配線
21の交差部には第３図に示すがごとく、絵素部薄膜トラ
ンジスタの形成と同時にSiNxからなる第１の層間絶縁膜
36、ａ−Siからなる第１の半導体層37、SiNx絶縁膜から
なる第２の層間絶縁膜38、n+a-Siからなる第２の半導体
層39が形成されることになり、４層からなる多層絶縁構
造となり、第1,第２の入力信号供給配線間の絶縁膜厚が
増大し、静電耐圧が向上する。By adopting such a structure, the first IC input signal supply wiring 22 and the second IC input signal supply wiring 22 in FIG.
As shown in FIG. 3, the first interlayer insulating film made of SiNx is formed at the intersection of 21 at the same time as the formation of the thin film transistor of the pixel portion.
36, the first semiconductor layer 37 made of a-Si, the second interlayer insulating film 38 made of SiNx insulating film, and the second semiconductor layer 39 made of n + a-Si are formed, and four layers are formed. The multi-layer insulation structure is formed, and the insulation film thickness between the first and second input signal supply wirings is increased, and the electrostatic breakdown voltage is improved.
発明の効果 以上のように本発明によれば、第２のIC入力信号供給
配線上には第１の層間絶縁膜が被着され、この第１の層
間絶縁膜上には液晶駆動用薄膜トランジスタを形成する
第１の半導体層が被着され、この第１の半導体層上には
島状の第２の層間絶縁膜該被着され、この第２の絶縁膜
上には第１半導体層と液晶駆動用スイッチング素子のソ
ース・ドレイン電極とのオーミック接触をとらしめる第
２の半導体層が被着され、この第２半導体層上には第１
のIC入力信号供給配線が形成されることによって、互い
に交差した第１のIC入力信号供給配線と第２のIC入力信
号供給配線間に４層からなる絶縁膜層と半導体層を積層
することにより、急激な静電気流入等による絶縁破壊に
対する信頼性を向上させることができる。As described above, according to the present invention, the first interlayer insulating film is deposited on the second IC input signal supply wiring, and the liquid crystal driving thin film transistor is formed on the first interlayer insulating film. A first semiconductor layer to be formed is deposited, an island-shaped second interlayer insulating film is deposited on the first semiconductor layer, and a first semiconductor layer and a liquid crystal are deposited on the second insulating film. A second semiconductor layer is deposited to ensure ohmic contact with the source / drain electrodes of the driving switching element, and a first semiconductor layer is deposited on the second semiconductor layer.
By forming the IC input signal supply wiring of, by laminating an insulating film layer and a semiconductor layer consisting of four layers between the first IC input signal supply wiring and the second IC input signal supply wiring intersecting each other, The reliability against dielectric breakdown due to a sudden inflow of static electricity can be improved.
【図面の簡単な説明】 第１図は本発明の実施例における単位絵素あたりの平面
図、第２図は周辺IC実装部の入力信号側部分の平面図、
第３図は第１のＡ−Ａ′断面と第２図のＢ−Ｂ′断面に
おける断面図、第４図は本発明における液晶表示装置を
構成する一方の基板の模式図である。 21……第２のIC入力信号供給配線、22……第１のIC入力
信号供給配線、26,38……第２の層間絶縁膜（SiNx）、3
6……第１の層間絶縁膜（SiNx）、37……ａ−Si半導体
層（第１の半導体層）、39……n+a-Si層（第２の半導体
層）。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a unit pixel in an embodiment of the present invention, FIG. 2 is a plan view of an input signal side portion of a peripheral IC mounting portion,
FIG. 3 is a cross-sectional view taken along the line AA ′ in the first section and the section BB ′ in FIG. 2, and FIG. 4 is a schematic view of one substrate constituting the liquid crystal display device according to the present invention. 21 …… Second IC input signal supply wiring, 22 …… First IC input signal supply wiring, 26,38 …… Second interlayer insulating film (SiNx), 3
6 ... First interlayer insulating film (SiNx), 37 ... a-Si semiconductor layer (first semiconductor layer), 39 ... n + a-Si layer (second semiconductor layer).
Claims (1)
を伝達するための第１のIC入力信号供給配線と前記ICを
基板に実装するための端子群を接続するための第２のIC
入力信号供給配線を備える画像表示装置であって、前記
第２のIC入力信号供給配線上には第１の層間絶縁膜が被
着され、この第１の層間絶縁膜上には前記画像表示部と
なる液晶駆動用薄膜トランジスタを形成する第１の半導
体層が被着され、この第１の半導体層上には島状の第２
の層間絶縁膜が被着され、この島状の第２の層間絶縁膜
上には前記第１の半導体層と前記液晶駆動用薄膜トラン
ジスタのソース・ドレイン電極とのオーミック接触をと
らしめる第２の半導体層が被着され、この第２の半導体
層上には前記第１のIC入力信号供給配線が形成されてな
ることを特徴とする液晶表示装置。1. A first IC input signal supply wiring for transmitting an input signal to an IC for driving an image display section and a second IC for connecting a terminal group for mounting the IC on a substrate. I c
An image display device having an input signal supply wiring, wherein a first interlayer insulating film is deposited on the second IC input signal supply wiring, and the image display unit is provided on the first interlayer insulating film. A first semiconductor layer forming a thin film transistor for driving a liquid crystal to be formed is deposited, and an island-shaped second semiconductor layer is formed on the first semiconductor layer.
A second semiconductor for depositing an ohmic contact between the first semiconductor layer and the source / drain electrode of the liquid crystal driving thin film transistor on the island-shaped second interlayer insulating film. A liquid crystal display device, wherein a layer is deposited, and the first IC input signal supply wiring is formed on the second semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25323190A JPH0810303B2 (en) | 1990-09-21 | 1990-09-21 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25323190A JPH0810303B2 (en) | 1990-09-21 | 1990-09-21 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04130419A JPH04130419A (en) | 1992-05-01 |
| JPH0810303B2 true JPH0810303B2 (en) | 1996-01-31 |
Family
ID=17248396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25323190A Expired - Fee Related JPH0810303B2 (en) | 1990-09-21 | 1990-09-21 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810303B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7065147B2 (en) * | 2020-04-28 | 2022-05-11 | 株式会社ジャパンディスプレイ | Semiconductor device |
-
1990
- 1990-09-21 JP JP25323190A patent/JPH0810303B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04130419A (en) | 1992-05-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |