JPH08102655A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH08102655A JPH08102655A JP6239116A JP23911694A JPH08102655A JP H08102655 A JPH08102655 A JP H08102655A JP 6239116 A JP6239116 A JP 6239116A JP 23911694 A JP23911694 A JP 23911694A JP H08102655 A JPH08102655 A JP H08102655A
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- potential
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- signal
- bus lines
- semiconductor integrated
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体メモリ等のバス
ラインの駆動回路に好適な半導体集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit suitable for a bus line driving circuit such as a semiconductor memory.
【０００２】[0002]
【従来の技術】図４は従来のバスライン駆動回路を示す
半導体集積回路図である。図４で１〜４はバスライン、
５〜１２はクロックトインバータ、１３〜１６は負荷容
量である。2. Description of the Related Art FIG. 4 is a semiconductor integrated circuit diagram showing a conventional bus line driving circuit. In FIG. 4, 1-4 are bus lines,
5 to 12 are clocked inverters, and 13 to 16 are load capacitors.
【０００３】動作を説明する。クロック信号をＬからＨ
にすると、クロックトインバータ５〜８がオンするため
バスライン１〜４に各々クロックトインバータ５〜８の
入力に応じた信号が出力がされる。出力された信号は各
々バスライン１〜４を伝達しクロックトインバータ９〜
１２の入力となる。次にクロック信号をＨからＬにする
と、クロックトインバータ５〜８がオフするためバスラ
イン１〜４には出力信号に応じた電位が保持される。The operation will be described. Clock signal from L to H
Then, since the clocked inverters 5-8 are turned on, signals corresponding to the inputs of the clocked inverters 5-8 are output to the bus lines 1-4. The output signals are transmitted through the bus lines 1 to 4 respectively, and the clocked inverter 9 to
12 inputs. Next, when the clock signal is changed from H to L, the clocked inverters 5 to 8 are turned off, so that the bus lines 1 to 4 hold the potential according to the output signal.
【０００４】[0004]
【発明が解決しようとする課題】上記従来技術では、一
般的には配線長が長いため、あるいは駆動すべき回路等
が付加されるためバスライン１〜４の負荷容量１３〜１
６が大きい。したがって、クロック信号がＬからＨにな
ったときに保持されている前の出力信号と反対の信号が
出力された場合には出力電位は電源電位Ｖｄｄ分の電位
変化をしなければならない。そのため、バスラインの信
号の伝達に時間がかかった。また、負荷容量が大きいの
で、その充放電のために消費電流が大きくなる問題があ
った。In the above prior art, the load capacitances 13 to 1 of the bus lines 1 to 4 are generally due to the long wiring length or the addition of circuits to be driven.
6 is big. Therefore, when a signal opposite to the previous output signal that is being held is output when the clock signal changes from L to H, the output potential must change by the power supply potential Vdd. Therefore, it takes a long time to transmit the signal on the bus line. Further, since the load capacity is large, there is a problem that the current consumption increases due to the charging and discharging.
【０００５】本発明はこの様な問題を解決するもので、
その目的とするところは信号の伝達の動作スピードを向
上させ、かつ、消費電流値の低減を図ることのできるバ
スラインの駆動回路を有する半導体集積回路を得ること
である。The present invention solves such problems.
An object of the invention is to obtain a semiconductor integrated circuit having a bus line driving circuit capable of improving the operation speed of signal transmission and reducing the consumption current value.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体集積回路
は、複数の信号ラインと各々前記信号ラインを駆動する
複数の駆動回路において、前記信号ラインの信号の変化
に先立って印加されるクロック信号により前記信号ライ
ンと前記駆動回路とを切り離す手段と、前記信号ライン
間を短絡する手段と、前記信号ラインに電位を供給する
手段とを設け、前記クロック信号により前記信号ライン
を中間電位に設定する回路を備えたことを特徴とする。According to another aspect of the present invention, there is provided a semiconductor integrated circuit, comprising a plurality of signal lines and a plurality of drive circuits each driving the signal line, wherein a clock signal applied prior to a change in the signal of the signal line. Means for disconnecting the signal line from the drive circuit, means for short-circuiting the signal lines, and means for supplying a potential to the signal line, and the signal line is set to an intermediate potential by the clock signal. It is characterized by having a circuit.
【０００７】また、本発明の半導体集積回路は、前記信
号ラインに電位を供給する手段が、前記信号ラインと電
源電位間との間に接続されたことを特徴とする。Further, the semiconductor integrated circuit of the present invention is characterized in that means for supplying a potential to the signal line is connected between the signal line and a power supply potential.
【０００８】また、本発明の半導体集積回路は、前記信
号ラインに電位を供給する手段が、前記信号ラインと接
地電位間との間に接続されたことを特徴とする。Further, the semiconductor integrated circuit of the present invention is characterized in that means for supplying a potential to the signal line is connected between the signal line and a ground potential.
【０００９】また、本発明の半導体集積回路は、前記信
号ラインに電位を供給する手段が、前記信号ラインの電
位に応じて電位を供給することを特徴とする。Further, in the semiconductor integrated circuit of the present invention, the means for supplying a potential to the signal line supplies a potential according to the potential of the signal line.
【００１０】[0010]
【作用】上記手段によれば、バスラインの電位を電位の
変化前に予め中間電位に設定しておくため、電位の変化
量が小さくなり高速動作と、電流値が低減できる。According to the above means, the potential of the bus line is previously set to the intermediate potential before the potential is changed, so that the amount of change in the potential is reduced and the high speed operation and the current value can be reduced.
【００１１】また、中間電位の設定にはバスラインに保
持されている電荷を利用するため、中間電位の設定に要
する電流は小さく低消費電力化が可能である。Further, since the electric charge held in the bus line is used for setting the intermediate potential, the current required for setting the intermediate potential is small and the power consumption can be reduced.
【００１２】[0012]
【実施例】図１は本発明の実施例を示す半導体集積回路
図である。図１で１〜４はバスライン、５〜１２はクロ
ックトインバータ、１３〜１６は負荷容量、１７はイン
バータ、１８〜２０はＰｃｈトランジスタ、２１〜２３
はＮｃｈトランジスタ、２４、２７は電位供給回路であ
り各々Ｐｃｈトランジスタ２５、２６、Ｎｃｈトランジ
スタ２８、２９より成る。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a semiconductor integrated circuit diagram showing an embodiment of the present invention. In FIG. 1, 1-4 are bus lines, 5-12 are clocked inverters, 13-16 are load capacitors, 17 are inverters, 18-20 are Pch transistors, 21-23.
Is an Nch transistor, and 24 and 27 are potential supply circuits, which are composed of Pch transistors 25 and 26 and Nch transistors 28 and 29, respectively.
【００１３】動作を説明する。バスライン１〜４に各々
クロックトインバータ５〜８の入力に応じた信号が出力
がされている状態で、クロック信号をＨからＬにすると
クロックトインバータ５〜１２はオフ、トランジスタ１
８〜２３、２５、２９は全てオンになる。The operation will be described. When the clock signal is changed from H to L while the signals corresponding to the inputs of the clocked inverters 5 to 8 are output to the bus lines 1 to 4, the clocked inverters 5 to 12 are turned off and the transistor 1
8 to 23, 25 and 29 are all turned on.
【００１４】説明を容易にするために負荷容量１３〜１
６の値が各々等しく、電位供給回路２４、２７が無い場
合を仮定する。まずトランジスタ１８〜２３がオンであ
るからバスライン１〜４は各々短絡され同電位となる。
この場合バスライン１〜４の電位レベルが全てＨの場合
は電位は電源電位Ｖｄｄのままであるが、バスライン１
〜４の電位レベルの内３本がＨの場合は短絡すると３／
４Ｖｄｄ、２本がＨの場合は１／２Ｖｄｄ、１本がＨの
場合は１／４Ｖｄｄ、全てがＬの場合は接地電位、０と
なる。For ease of explanation, load capacities 13 to 1
It is assumed that the values of 6 are equal and the potential supply circuits 24 and 27 are not provided. First, since the transistors 18 to 23 are turned on, the bus lines 1 to 4 are short-circuited to the same potential.
In this case, when all the potential levels of the bus lines 1 to 4 are H, the potential remains the power supply potential Vdd, but the bus line 1
3 out of 4 potential levels are 3 /
4Vdd, 1/2 Vdd when two lines are H, 1 / 4Vdd when one line is H, and ground potential 0 when all lines are L.
【００１５】次に電位供給回路２４、２７がある場合を
説明する。電位供給回路２４はトランジスタ２６のしき
い値電位をＶｔｈｐとするとバスラインの電位がＶｄｄ
−Ｖｔｈｐ以下であるとオンする。したがって、Ｖｔｈ
ｐを例えば１／２Ｖｄｄ＞Ｖｄｄ−Ｖｔｈｐ＞１／４Ｖ
ｄｄに成るように設定すると、バスライン１〜４の内１
本がＨの場合と、全てがＬの場合、バスラインの電位は
Ｖｄｄ−Ｖｔｈｐまで引き上げられる。同様に電位供給
回路２９はトランジスタ２８のしきい値電位をＶｔｈｎ
とするとバスラインの電位がＶｔｈｎ以上であるとオン
する。したがって、Ｖｔｈｎを例えば３／４Ｖｄｄ＞Ｖ
ｔｈｎ＞１／２Ｖｄｄに成るように設定すると、バスラ
イン１〜４の内３本がＨの場合と、全てがＨの場合、バ
スラインの電位はＶｔｈｎまで引き下げられる。バスラ
イン１〜４の内２本がＨの場合は電位供給回路２４、２
７は両方オフであるから１／２Ｖｄｄのままである。Next, the case where the potential supply circuits 24 and 27 are provided will be described. In the potential supply circuit 24, when the threshold potential of the transistor 26 is Vthp, the potential of the bus line is Vdd.
It is turned on when the voltage is −Vthp or less. Therefore, Vth
p is, for example, 1 / 2Vdd>Vdd-Vthp> 1 / 4V
If set to dd, 1 of bus lines 1 to 4
When the number of books is H and when all of them are L, the potential of the bus line is raised to Vdd-Vthp. Similarly, the potential supply circuit 29 changes the threshold potential of the transistor 28 to Vthn.
Then, the bus line is turned on when the potential of the bus line is Vthn or higher. Therefore, Vthn is set to, for example, 3/4 Vdd> V
If thn> 1 / 2Vdd is set, the potential of the bus lines is lowered to Vthn when three of the bus lines 1 to 4 are H and when all are H. When two of the bus lines 1 to 4 are H, the potential supply circuits 24 and 2
Since 7 is both off, it remains at 1/2 Vdd.
【００１６】次にクロック信号をＬからＨにするとクロ
ックトインバータ５〜１２はオン、トランジスタ１８〜
２３、２５、２９は全てオフになりバスライン間の短絡
も解除される。バスライン１〜４にはクロックトインバ
ータ５〜８の新たな入力に応じた信号が出力されるが、
その電位の変化量は出力信号がＨの場合はＶｄｄ−Ｖｔ
ｈｎ、１／２Ｖｄｄ、Ｖｔｈｐの何れかであり、出力が
Ｌの場合はＶｄｄ−Ｖｔｈｐ、１／２Ｖｄｄ、Ｖｔｈｎ
のいずれかとなる。Next, when the clock signal is changed from L to H, the clocked inverters 5-12 are turned on, and the transistors 18-.
23, 25 and 29 are all turned off, and the short circuit between the bus lines is released. Signals corresponding to new inputs of the clocked inverters 5 to 8 are output to the bus lines 1 to 4,
The change amount of the potential is Vdd-Vt when the output signal is H
hn, 1/2 Vdd, or Vthp, and when the output is L, Vdd-Vthp, 1/2 Vdd, Vthn
Will be either.
【００１７】したがって、図２に示すように出力電位は
従来例のようにＶｄｄ分の変化をする必要がなくその分
（Δｔ分）バスラインの信号の伝達の高速化が可能とな
る。また、電位変化量が小さくなるためその分負荷容量
を充放電するための消費電流値を低減できる。Therefore, as shown in FIG. 2, the output potential does not need to be changed by Vdd as in the conventional example, and the signal transmission of the bus line can be speeded up by that much (Δt). Further, since the potential change amount is small, the current consumption value for charging / discharging the load capacity can be reduced accordingly.
【００１８】また、電位の設定には、バスラインを短絡
することによってバスラインに保持されている総電荷を
分割した形で利用するため、電位の設定に要する電流は
小さく低消費電力化が可能である。Further, since the total electric charge held in the bus line is divided and used by setting the electric potential by short-circuiting the bus line, the electric current required for setting the electric potential is small and low power consumption is possible. Is.
【００１９】また、電位供給回路２４、２７は同時には
オンしないためここに流れる貫通電流はない。Further, since the potential supply circuits 24 and 27 are not turned on at the same time, there is no through current flowing there.
【００２０】尚、本実施例では簡単のため４本のバスラ
インで説明したがこれは４本に限らず複数であれば何本
であっても良い。In this embodiment, four bus lines have been described for the sake of simplicity, but the number of bus lines is not limited to four, and any number of bus lines may be used.
【００２１】また、複数の配線とそれに伴う負荷容量が
あればバスラインという名称にとらわれることなく本実
施例が適応できる。Further, if there are a plurality of wirings and load capacitances associated therewith, this embodiment can be applied regardless of the name of a bus line.
【００２２】また、Ｖｔｈｐの設定は例えば１／４Ｖｄ
ｄ＞Ｖｄｄ−Ｖｔｈｐ＞０、Ｖｔｈｎの設定は例えばＶ
ｄｄ＞Ｖｔｈｎ＞３／４Ｖｄｄであっても良く、同様の
効果がある。The setting of Vthp is, for example, 1/4 Vd.
The setting of d>Vdd-Vthp> 0 and Vthn is, for example, V
It may be dd>Vthn> 3 / 4Vdd, and has the same effect.
【００２３】また、電位供給回路２４、２７は同時には
オンしない設定であるが、例えばトランジスタ２６、２
８がなく電位供給回路２４、２７を同時にオンさせて、
バスラインをある中間電位に設定してもそこに流れる貫
通電流が増えるが高速動作に対しては効果がある。Although the potential supply circuits 24 and 27 are set so as not to be turned on at the same time, for example, the transistors 26 and 2 are used.
There is no 8 and the potential supply circuits 24 and 27 are simultaneously turned on,
Even if the bus line is set to a certain intermediate potential, the through current flowing therethrough increases, but it is effective for high-speed operation.
【００２４】また、電位供給回路２４、２７は必ずしも
両方必要ではなく、例えば電位供給回路２４だけの場合
は出力信号がＨからＬに切り替わる場合の高速動作に対
して効果がある。Further, both the potential supply circuits 24 and 27 are not always necessary. For example, the potential supply circuit 24 alone is effective for high-speed operation when the output signal switches from H to L.
【００２５】また、Ｖｔｈｐ、Ｖｔｈｎを作るのに特別
なしきい値電位を持つトランジスタ２６、２８を使用し
たが、図３に示すようにノーマルなＰｃｈトランジスタ
３０〜３２あるいはＮｃｈトランジスタ３３〜３５を各
々ダイオード接続させて、それらのしきい値電位の和と
して作っても良い。Although transistors 26 and 28 having special threshold potentials are used to generate Vthp and Vthn, normal Pch transistors 30 to 32 or Nch transistors 33 to 35 are respectively diode-connected as shown in FIG. They may be connected and made as the sum of their threshold potentials.
【００２６】[0026]
【発明の効果】以上述べた様に本発明によれば、バスラ
インの電位を電位の変化前に予め中間電位に設定してお
くため、電位の変化量が小さくなり信号の伝達の高速動
作が可能となる。また、電流値が低減できる。As described above, according to the present invention, the potential of the bus line is previously set to the intermediate potential before the potential is changed, so that the amount of change in the potential becomes small and the high-speed operation of signal transmission becomes possible. It will be possible. In addition, the current value can be reduced.
【００２７】また、中間電位の設定にはバスラインに保
持されている電荷を利用するため、中間電位の設定に要
する電流は小さく低消費電力化に対して有効となる。Further, since the electric charge held in the bus line is used for the setting of the intermediate potential, the current required for setting the intermediate potential is small and it is effective in reducing the power consumption.
【図１】本発明の実施例における半導体集積回路図。FIG. 1 is a semiconductor integrated circuit diagram according to an embodiment of the present invention.
【図２】本発明の実施例における電位変化図。FIG. 2 is a potential change diagram in the example of the present invention.
【図３】本発明の実施例における第２の電位供給回路
図。FIG. 3 is a second potential supply circuit diagram in the embodiment of the present invention.
【図４】従来の実施例における半導体集積回路図。FIG. 4 is a semiconductor integrated circuit diagram in a conventional example.
１〜４ バスライン ５〜１２ クロックトインバータ １３〜１６ 負荷容量 １７ インバータ １８〜２０、２５、２６ Ｐｃｈトランジスタ ２１〜２３、２８、２９ Ｎｃｈトランジスタ ２４、２７ 電位供給回路 1-4 Bus lines 5-12 Clocked inverters 13-16 Load capacity 17 Inverters 18-20, 25, 26 Pch transistors 21-23, 28, 29 Nch transistors 24, 27 Potential supply circuit
Claims (4)
駆動する複数の駆動回路において、前記信号ラインの信
号の変化に先立って印加されるクロック信号により前記
信号ラインと前記駆動回路とを切り離す手段と、前記信
号ライン間を短絡する手段と、前記信号ラインに電位を
供給する手段とを設け、前記クロック信号により前記信
号ラインを中間電位に設定する回路を備えたことを特徴
とする半導体集積回路。1. In a plurality of signal lines and a plurality of drive circuits for driving the signal lines, a means for disconnecting the signal lines from the drive circuit by a clock signal applied prior to a change in the signal of the signal lines. A circuit for setting the signal line to an intermediate potential by means of the clock signal, and a means for short-circuiting the signal lines and a means for supplying a potential to the signal line. .
前記信号ラインと電源電位間との間に接続されたことを
特徴とする請求項１記載の半導体集積回路。2. A means for supplying a potential to the signal line,
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected between the signal line and a power supply potential.
前記信号ラインと接地電位間との間に接続されたことを
特徴とする請求項１記載の半導体集積回路。3. A means for supplying a potential to the signal line,
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected between the signal line and a ground potential.
が、前記信号ラインの電位に応じて電位を供給すること
を特徴とする請求項１記載の半導体集積回路。4. The semiconductor integrated circuit according to claim 1, wherein the means for supplying a potential to the signal line supplies a potential according to the potential of the signal line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23911694A JP3275570B2 (en) | 1994-10-03 | 1994-10-03 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23911694A JP3275570B2 (en) | 1994-10-03 | 1994-10-03 | Semiconductor integrated circuit |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001266363A Division JP3541822B2 (en) | 2001-09-03 | 2001-09-03 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08102655A true JPH08102655A (en) | 1996-04-16 |
| JP3275570B2 JP3275570B2 (en) | 2002-04-15 |
Family
ID=17040039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23911694A Expired - Fee Related JP3275570B2 (en) | 1994-10-03 | 1994-10-03 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3275570B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6215340B1 (en) | 1998-02-18 | 2001-04-10 | Nec Corporation | Signal transition accelerating driver with simple circuit configuration and driver system using the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ITMI20080097A1 (en) | 2008-01-23 | 2009-07-24 | Reagens Spa | COMPOSITION FOR THE STABILIZATION OF HALOGEN CONTAINING POLYMERS |
| EP2151475B1 (en) | 2008-08-01 | 2011-05-25 | Reagens S.p.A. | Composition comprising sodium formate for stabilizing halogen-containing polymers |
| EP2404960A1 (en) | 2010-07-08 | 2012-01-11 | Reagens S.p.A. | Stabilizing composition for halogen-containing polymers |
| EP2662403B1 (en) | 2012-05-11 | 2015-02-18 | Reagens S.p.A. | Stabilizing resin formulation of halogen-containing polymers |
| ES2928341T3 (en) | 2016-05-12 | 2022-11-17 | Reagens Spa | Compositions and products for stabilizing halogen-containing polymers |
| WO2020053157A1 (en) | 2018-09-10 | 2020-03-19 | Reagens S.P.A. | A stabilized chlorinated polyvinylchloride and an article made therefrom |
-
1994
- 1994-10-03 JP JP23911694A patent/JP3275570B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6215340B1 (en) | 1998-02-18 | 2001-04-10 | Nec Corporation | Signal transition accelerating driver with simple circuit configuration and driver system using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3275570B2 (en) | 2002-04-15 |
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