JPH0799801B2 - Amplifier circuit - Google Patents
Amplifier circuitInfo
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- JPH0799801B2 JPH0799801B2 JP60089246A JP8924685A JPH0799801B2 JP H0799801 B2 JPH0799801 B2 JP H0799801B2 JP 60089246 A JP60089246 A JP 60089246A JP 8924685 A JP8924685 A JP 8924685A JP H0799801 B2 JPH0799801 B2 JP H0799801B2
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- current
- transistor
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Description
【発明の詳細な説明】 産業上の利用分野 本発明は低電源電圧用の増幅回路に関するものである。Description: FIELD OF THE INVENTION The present invention relates to an amplifier circuit for low power supply voltage.
従来の技術 従来の増幅回路の構成を第４図に示す。60は入力端子、
62は出力端子、61は電源端子、63は接地端子、51,52,5
5,56,57,58はトランジスタ、53,54はダイオード、59は
定電流源である。この増幅回路はトランジスタ51,52の
ダーリントン接続段と、トランジスタ55,56のSEPPで構
成している。2. Description of the Related Art The configuration of a conventional amplifier circuit is shown in FIG. 60 is an input terminal,
62 is an output terminal, 61 is a power supply terminal, 63 is a ground terminal, 51, 52, 5
5,56,57,58 are transistors, 53,54 are diodes, and 59 is a constant current source. This amplifier circuit is composed of Darlington connection stages of transistors 51 and 52 and SEPP of transistors 55 and 56.
発明が解決しようとする問題点 このような従来の構成では、電源端子61からトランジス
タ57のエミッタ−コレクタ、トランジスタ55のベース−
エミッタ、トランジスタ56のエミッタ−ベース、トラン
ジスタ52のコレクタ−エミッタを経て接続端子63へ流れ
る電流の経路を考える場合、電源端子61の電圧としてベ
ース−エミッタ順方向電圧（以下VBEと示す。）の２倍
と、コレクタ−エミッタ飽和電圧（以下VCEsatと示
す。）の２倍の合計の電圧、すなわち2VBE＋2VCEsatの
電圧が少くとも必要であり、増幅回路の最低動作電圧が
高いという問題点があった。本発明は増幅回路の最低動
作電圧を下げる事を目的とし、更にアイドリング電流少
なくすることのできるＡ級の動作の増幅回路を提供する
ものである。Problems to be Solved by the Invention In such a conventional configuration, from the power supply terminal 61 to the emitter-collector of the transistor 57 and the base of the transistor 55-
When considering the path of the current flowing to the connection terminal 63 via the emitter, the emitter-base of the transistor 56, and the collector-emitter of the transistor 52, the base-emitter forward voltage (hereinafter referred to as V BE ) is used as the voltage of the power supply terminal 61. The problem is that the minimum operating voltage of the amplifier circuit is high because it requires twice the total voltage, which is twice the collector-emitter saturation voltage (hereinafter referred to as V CEsat ), that is, 2V BE + 2V CEsat. was there. The present invention aims to reduce the minimum operating voltage of the amplifier circuit, and further provides an amplifier circuit of class A operation capable of reducing the idling current.
問題点を解決するための手段 前記問題点を解決するために、本発明は、同相且つ大き
さの等しい２つの出力を発生する同相二出力増幅部に入
力を加え、上記同相二出力増幅部の第１の電流出力端子
を電流源と第１の電流増幅部の入力端子に接続し、更に
上記同相二出力増幅部の第２の電流出力端子を第２の電
流増幅部の入力端子に接続し、上記第１の電流増幅部の
出力端子と、上記第１の電流増幅部の出力端子を接続
し、その接続点より出力を得る構成とした。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention adds an input to a common-mode two-output amplifying unit that generates two outputs that are in-phase and have the same size, and outputs the common-mode two-output amplifying unit. The first current output terminal is connected to the current source and the input terminal of the first current amplification section, and the second current output terminal of the in-phase dual output amplification section is further connected to the input terminal of the second current amplification section. The output terminal of the first current amplification section is connected to the output terminal of the first current amplification section, and an output is obtained from the connection point.
特に上記同相出力増幅部として第１のトランジスタのコ
レクタ及びベースと、第２のトランジスタのベースと、
第３のトランジスタのベースとを接続し、その接続点を
入力端子とし、更に第２及び第３のトランジスタのエミ
ッタを同電位としたカレントミラー構成とし、また、第
１の電流増幅部として、第４のトランジスタのコレクタ
とベースを接続し更に第５のトランジスタのベースに接
続し、その接続ラインを入力端子とし、更に第４のトラ
ンジスタのエミッタに抵抗を入れ第５のトランジスタの
コレクタを出力端子とする構成とし、更に第２の電流増
幅部として、第１の電流増幅部と同じ構成とし、上記第
1,第２の電流増幅部の出力端子すなわち、トランジスタ
のコレクタ同志を接続し、出力をとり出す構成とする事
で、極めて低電源電圧まで動作する増幅回路を提供す
る。In particular, the collector and base of the first transistor, the base of the second transistor, and
A current mirror configuration in which the base of the third transistor is connected, the connection point serves as an input terminal, and the emitters of the second and third transistors have the same potential, and the first current amplification unit includes The collector and the base of the fourth transistor are connected to each other, and the base of the fifth transistor is further connected, the connection line is used as an input terminal, and the emitter of the fourth transistor is connected with a resistor to connect the collector of the fifth transistor to the output terminal. In addition, the second current amplification section has the same configuration as the first current amplification section.
By providing a configuration in which the output terminals of the first and second current amplification units, that is, the collectors of the transistors are connected and the output is taken out, an amplification circuit that operates up to an extremely low power supply voltage is provided.
作用 入力信号電流を、同相二出力増幅部で、２つの同相で大
きさの等しい信号に増幅し、前記同相二出力増幅部で得
られる第１の電流出力は、第１の電流出力端子に接続さ
れた電流源により逆相の信号となり、第１の電流増幅部
に入力され増幅される。一方、同相二出力増幅部の第２
の電流出力は、第２の電流増幅部で増幅される。第１の
電流増幅部の出力電流は、第２の電流増幅部の出力電流
と互いに逆相であり、信号成分は加え合わされて出力と
なる。Action Input signal current is amplified by two in-phase two-output amplifiers into two in-phase and equal-sized signals, and the first current output obtained by the in-phase two-output amplifiers is connected to the first current output terminal. The converted current source produces a signal of opposite phase, which is input to the first current amplification section and amplified. On the other hand, the second in-phase dual output amplifier
The current output of is amplified by the second current amplification unit. The output current of the first current amplification unit has a phase opposite to that of the output current of the second current amplification unit, and the signal components are added together to form an output.
無信号のバイアスは、電流源が第１の電流増幅部を同相
二出力増幅部の第２の出力が第２の電流増幅部をそれぞ
れ供給する。なお同相二出力増幅部はその入力電流によ
りバイアスされる。In the signalless bias, the current source supplies the first current amplification unit and the second output of the in-phase two-output amplification unit supplies the second current amplification unit. The in-phase dual output amplifier is biased by its input current.
本発明の増幅回路において、特に、同相二出力増幅部を
第１のトランジスタと第２のトランジスタと第３のトラ
ンジスタとで又、第１の電流増幅部を第４のトランジス
タと第５のトランジスタと抵抗とで構成し、更に第２の
電流増幅部を第１の電流増幅部と同じ構成とした時には
電流と接地間の素子数が少くなり、極めて低い電源電圧
まで動作する。In the amplifier circuit of the present invention, in particular, the in-phase dual-output amplifier section includes the first transistor, the second transistor, and the third transistor, and the first current amplifier section includes the fourth transistor and the fifth transistor. When the second current amplifying unit is made of a resistor and the second current amplifying unit has the same configuration as the first current amplifying unit, the number of elements between the current and ground is small, and the device operates even at an extremely low power supply voltage.
また、最大出力電流は電流源の電流と、第１の電流増幅
部と第２の電流増幅部の増幅度できまり、電流源の電流
を、第１及び第２の電流増幅部の増幅度倍した電流とな
る。本発明では、第１及び第２の電流増幅部の増幅度を
入力電流により正の頃きを持った指数関数的に変化する
構成とするため、アイドリング電流より大きな最大出力
電流を得る事ができる。Further, the maximum output current is determined by the current of the current source and the amplification factor of the first current amplification unit and the second current amplification unit, and the current of the current source is multiplied by the amplification factors of the first and second current amplification units. It becomes the current. In the present invention, since the amplification factors of the first and second current amplification units are changed exponentially with a positive period according to the input current, the maximum output current larger than the idling current can be obtained. .
実 施 例 第１図に本発明の実施例のブロック図を示す。１は同相
二出力増幅部、11は入力端子、12は第１の電流出力端
子、13は第２の電流出力端子、２は定電流源、21は定電
流源の出力端子、３は第１の電流増幅部、31は入力端
子、32は出力端子、４は第２の電流増幅部、41は入力端
子、42は出力端子、10は電流入力端子、43は電流出力端
子である。第１の電流増幅部3,第２の電流増幅部４とし
て、入力電流により増幅部が指数関数的に変化する特性
を持つ回路を用いてもよい。すなわち、それぞれの増幅
度を とすると と表わされるような特性をもつ回路である。なおK1,K2
は比例定数である。Practical Example FIG. 1 shows a block diagram of an embodiment of the present invention. 1 is an in-phase dual-output amplifier, 11 is an input terminal, 12 is a first current output terminal, 13 is a second current output terminal, 2 is a constant current source, 21 is a constant current source output terminal, and 3 is a first Current amplifier, 31 is an input terminal, 32 is an output terminal, 4 is a second current amplifier, 41 is an input terminal, 42 is an output terminal, 10 is a current input terminal, and 43 is a current output terminal. As the first current amplification unit 3 and the second current amplification unit 4, circuits having a characteristic that the amplification unit exponentially changes depending on the input current may be used. That is, And It is a circuit with the characteristics as K 1 , K 2
Is a constant of proportionality.
第２図に本発明の具体的な回路例を示し動作を説明す
る。The operation will be described with reference to FIG. 2 showing a concrete circuit example of the present invention.
第２図において１は同相二出力増幅部で、11は入力端
子、12は第１の電流出力端子、13は第２の電流出力端
子、101,102,103はトランジスタである。トランジスタ1
02,103の各コレクタからの出力電流をI01,I02とする。
２は定電流源で、201は電流値がICなる定電流源、21は
出力端子である。３は電流増幅部で、301,302はトラン
ジスタ、303は値がR1なる抵抗、31は入力端子で、その
入力電流はI1、32は電流出力端子でその電流値はId1で
ある。４は第２の電流増幅部で、401,402はトランジス
タ、403は値がR2なる抵抗、41は入力端子で、その入力
電流はI2、42は電流出力端子でその電流値はId2であ
る。10は入力端子、43は出力端子44は電流端子、45は接
地端子である。In FIG. 2, 1 is an in-phase dual-output amplifier, 11 is an input terminal, 12 is a first current output terminal, 13 is a second current output terminal, and 101, 102 and 103 are transistors. Transistor 1
The output currents from the collectors 02 and 103 are I 01 and I 02 .
2 is a constant current source, 201 is a constant current source whose current value is I C , and 21 is an output terminal. Reference numeral 3 is a current amplification unit, 301 and 302 are transistors, 303 is a resistor whose value is R 1 , 31 is an input terminal, its input current is I 1 , 32 is a current output terminal, and its current value is I d1 . Reference numeral 4 is a second current amplification unit, 401 and 402 are transistors, 403 is a resistor having a value of R 2 , 41 is an input terminal, the input current is I 2 , 42 is a current output terminal, and the current value is I d2 . . 10 is an input terminal, 43 is an output terminal 44 is a current terminal, and 45 is a ground terminal.
この実施例で電流と接地間の電流経路を考えると、電源
44よりトランジスタ103のエミッタ−−コレクタとトラ
ンジスタ402のベース−エミッタを通り接地に至ってお
り、必要な電源電圧は、VBE＋VCEsatである。従って本
構成によると、極めて低い電源電圧まで動作可能であ
る。Considering the current path between the current and ground in this embodiment, the power supply
From 44, it passes through the emitter-collector of the transistor 103 and the base-emitter of the transistor 402 to the ground, and the necessary power supply voltage is V BE + V CEsat . Therefore, according to this configuration, it is possible to operate up to an extremely low power supply voltage.
本構成によるトランジスタ302,トランジスタ402のアイ
ドリング電流は、電流源201の電流値ICと、第１の電流
増幅部３の増幅度 と、第２の電流増幅部４の増幅度 により決まる。第１の電流増幅部３の出力電流Id1は入
力電流I1と、抵抗R1を用いて、 で表わされる。ここにVTはビルトイン電圧でｑを電子の
荷電荷、ｋをボルツマン係数、Ｔを絶対温度として、VT
＝kT/qで表わされる。第２の電流増幅部４の出力電流I
d2も同様に、入力電流I2と抵抗R2を用いて、 となり、（１）式と（２）式より、第１の電流増幅部3,
第２の電流増幅部４の増幅度 は（３）式のように入力電流I1,I2の指数関数で表わさ
れる。The idling currents of the transistors 302 and 402 according to this configuration are the current value I C of the current source 201 and the amplification degree of the first current amplification unit 3. And the amplification factor of the second current amplification unit 4. Determined by The output current I d1 of the first current amplification unit 3 is calculated by using the input current I 1 and the resistor R 1 . It is represented by. Here V T is the electron load charge q in built-in voltage, the Boltzmann coefficient k, a T as an absolute temperature, V T
= K T / q Output current I of the second current amplification unit 4
Similarly for d2 , using input current I 2 and resistor R 2 , From equations (1) and (2), the first current amplification unit 3,
Amplification degree of the second current amplification unit 4 Is expressed by an exponential function of the input currents I 1 and I 2 as shown in equation (3).
一方、同相二出力増幅部の出力電流I01,I02は等しく、
又、I02は、そのままI2となる。電流増幅部３への入力
電流I1は、I2を用いて（４）式で表わされる。 On the other hand, the output currents I 01 and I 02 of the in-phase two-output amplifier are equal,
Also, I 02 becomes I 2 as it is. The input current I 1 to the current amplification unit 3 is expressed by the equation (4) using I 2 .
I1＝IC−I2 ……（４） トランジスタ302と、トランジスタ402のアイドリング電
流はId1＝Id2となるように決める。アイドリング電流を
Idとし、（１）式と（２）式でId1＝Id2＝Idとおき
（３），（４）式を用いて、アイドリング電流を IC,I2で表わすと（５）式となる。I 1 = I C −I 2 (4) The idling currents of the transistor 302 and the transistor 402 are determined so that I d1 = I d2 . Idling current
Let I d be, I d1 = I d2 = I d in equations (1) and (2), and by using equations (3) and (4), the idling current is When expressed by I C and I 2 , the formula (5) is obtained.
特にR1＝R2なる条件がある時には、I1＝I2となり、 でバランスし、アイドリング電流、Idは となる。 Especially when there is a condition of R 1 = R 2 , I 1 = I 2 , Balance at, idling current, I d Becomes
ただし である。However Is.
このように、R1＝R2なる条件を持たせる事により、アイ
ドリング電流の電流値を、極めて容易に決める事ができ
る。Thus, by providing the condition of R 1 = R 2 , the current value of the idling current can be determined very easily.
信号電流は、入力端子10より入力されトランジスタ102,
トランジスタ103のコレクタより出力される。トランジ
スタ102からの電流出力は、電流源201により逆相になっ
て第１の電流増幅部３に入力され、一方、トランジスタ
103からのコレクタよりの信号電流は同相のまま第２の
電流増幅部４に入力される。第１及び第２の電流増幅部
は入力信号を増幅し、出力電流を出力端子より出力す
る。なお第１の電流増幅部３と第２の電流増幅部４の出
力信号電流は互いに逆相であり、加え合う。本構成はＡ
級の構成をとりながら、第１及び第２の電流増幅部にそ
の入力電流により、増幅度が正の傾きをもった指数関数
的に変化する特性を持たせる事により無信号時のアイド
リング電流を越える最大出力電流を得る事ができる。第
２図において特にR1＝R2の時について考えると、アイド
リング電流は であり、一方最大出力電流Imaxはトランジスタ302,402
ともに、 で示されるため通常のＡ級の場合と比較し 倍の最大出力電流が得られる。このことはＡ級動作をす
るにもかかわらず小さなアイドリング電流で、大きな最
大出力電流を得られる事を示す。The signal current is input from the input terminal 10 and the transistor 102,
It is output from the collector of the transistor 103. The current output from the transistor 102 is reversed in phase by the current source 201 and input to the first current amplifying unit 3, while the transistor
The signal current from the collector from 103 is input to the second current amplification unit 4 in the same phase. The first and second current amplification units amplify the input signal and output the output current from the output terminal. The output signal currents of the first current amplification unit 3 and the second current amplification unit 4 have opposite phases to each other and are added. This configuration is A
By adopting a class structure, the first and second current amplifiers have a characteristic that the amplification degree changes exponentially with a positive slope according to the input currents thereof, so that the idling current at no signal can be reduced. The maximum output current that exceeds can be obtained. Considering especially when R 1 = R 2 in FIG. 2 , the idling current is While the maximum output current I max is
Together Since it is shown by Double maximum output current is obtained. This indicates that a large maximum output current can be obtained with a small idling current despite the class A operation.
次に、同相二出力増幅部を別の構成とし、差動アンプの
能動負荷に接続した場合の実施例を第３図に示す。Next, FIG. 3 shows an embodiment in which the in-phase two-output amplifying section has another structure and is connected to the active load of the differential amplifier.
第３図において、１は同相二出力増幅部で、11は入力端
子、12は第１の電流出力端子、13は第２の電流出力端
子、104,105はトランジスタで、106,107は値がともにRA
なる抵抗である。２は定電流源で、201は電流値がICな
る定電流源、21は出力端子である。３は第１の電流増幅
部で、301,302はトランジスタ、303は値がR1なる抵抗、
31は入力端子で32は電流出力端子である。４は第２の電
流増幅部で、401,402はトランジスタ、403は値がR2なる
抵抗、41は入力端子で、42は電流出力端子である。701,
702,703,704はトランジスタで、705は電流源で、71は非
反転入力端子で、72は反転入力端子で73は差動出力端子
である。43は出力端子、44は電源端子、45は接地端子で
ある。第３図において、トランジスタ701,702,703,704,
及び電流源705により、差動増幅段を構成する。In FIG. 3, 1 is an in-phase dual output amplifier, 11 is an input terminal, 12 is a first current output terminal, 13 is a second current output terminal, 104 and 105 are transistors, and 106 and 107 are both R A
It is resistance. 2 is a constant current source, 201 is a constant current source whose current value is I C , and 21 is an output terminal. 3 is a first current amplification unit, 301 and 302 are transistors, 303 is a resistor whose value is R 1 ,
31 is an input terminal and 32 is a current output terminal. Reference numeral 4 is a second current amplification unit, 401 and 402 are transistors, 403 is a resistor having a value of R 2 , 41 is an input terminal, and 42 is a current output terminal. 701,
Reference numerals 702, 703 and 704 are transistors, 705 is a current source, 71 is a non-inverting input terminal, 72 is an inverting input terminal and 73 is a differential output terminal. 43 is an output terminal, 44 is a power supply terminal, and 45 is a ground terminal. In FIG. 3, transistors 701, 702, 703, 704,
And the current source 705 form a differential amplifier stage.
同相二出力増幅部１は、トランジスタ104,105のベース
が共通であり、抵抗106,107の値が等しいため、トラン
ジスタ104,105のエミッタ電圧が等しく、そのトランジ
スタ104,105のコレクタから得られる出力電流すなわち
第１の電流出力と第２の電流出力は同相で大きさが等し
い。同相二出力増幅部の入力は、差動増幅段の差動出力
端子73に接続されている。Since the bases of the transistors 104 and 105 are common and the resistors 106 and 107 have the same value, the in-phase dual-output amplifier 1 has the same emitter voltage of the transistors 104 and 105, and the output current obtained from the collectors of the transistors 104 and 105, that is, the first current output. The second current outputs are in phase and of equal magnitude. The inputs of the in-phase dual-output amplification section are connected to the differential output terminal 73 of the differential amplification stage.
同相二出力増幅部１と定電流源２と第１の電流増幅部３
と第２の電流増幅部４とから成る増幅回路の動作は第２
図の場合と同様である。In-phase dual output amplifier 1, constant current source 2 and first current amplifier 3
The operation of the amplification circuit including the second current amplification unit 4 is
It is similar to the case of the figure.
第３図は、71を非反転入力端子、72を反転入力端子、43
を出力端子とする差動増幅回路であり、このように、本
発明の増幅回路を容易に産動増幅回路に応用できる。In FIG. 3, 71 is a non-inverting input terminal, 72 is an inverting input terminal, 43
Is an output terminal, and thus the amplifier circuit of the present invention can be easily applied to a production amplifier circuit.
発明の効果 本発明により、極めて低い電源電圧における増幅器構成
が可能となり、また最大出力電流を得るためのアイドリ
ング電流を、Ａ級動作にもかかわらず小さく抑える事が
できる。またこの結果、消費電流を少なく抑え、低電源
電圧まで動く事を要求される電池駆動タイプのアンプ構
成を容易にする。EFFECTS OF THE INVENTION According to the present invention, it is possible to realize an amplifier configuration with an extremely low power supply voltage, and it is possible to suppress the idling current for obtaining the maximum output current to be small despite the class A operation. Further, as a result, the current consumption is suppressed to a low level, and the battery-driven type amplifier configuration required to operate to a low power supply voltage is facilitated.
第１図は本発明の一実施例による増幅回路のブロック
図、第２図は本発明の他の実施例の結線図、第３図は上
記実施例をより具体的に示した結線図、第４図は従来例
の結線図である。 １……同相二出力増幅部、２……定電流源、３……第１
の電流増幅部、４……第２の電流増幅部。FIG. 1 is a block diagram of an amplifier circuit according to an embodiment of the present invention, FIG. 2 is a connection diagram of another embodiment of the present invention, and FIG. 3 is a connection diagram showing the above embodiment more specifically. FIG. 4 is a connection diagram of a conventional example. 1 ... In-phase dual output amplifier, 2 ... Constant current source, 3 ... First
Current amplification section 4 ... second current amplification section.
Claims (6)
しい電流を出力する同相二出力増幅部と、上記同相二出
力増幅部の第１の電流出力端子に接続された定電流源
と、上記第１の電流出力端子と上記定電流源とに共通に
接続され、かつ上記定電流源の電流と、上記同相二出力
増幅部の第１の電流出力端子からの電流の差が入力さ
れ、電流増幅を行なう第１の電流増幅部と、上記同相二
出力増幅部の第２の電流出力端子に接続され、かつ上記
同相二出力増幅部の第２の出力電流が入力され、電流増
幅を行なう第２の電流増幅部とを備え、上記第１の電流
増幅部の出力端子と上記第２の電流増幅部の出力端子と
を接続し、上記接続点より出力を得ることを特徴とする
増幅回路。1. An in-phase two-output amplifying section that inputs a current and outputs two in-phase and equal-sized currents, and a constant current source connected to a first current output terminal of the in-phase two-output amplifying section. , The first current output terminal and the constant current source are commonly connected, and the difference between the current of the constant current source and the current from the first current output terminal of the in-phase dual-output amplifier is input. , A first current amplifying section that performs current amplification and a second current output terminal of the in-phase two-output amplifying section, and the second output current of the in-phase two-output amplifying section is input to amplify the current. A second current amplifying section for performing the amplification, connecting the output terminal of the first current amplifying section and the output terminal of the second current amplifying section, and obtaining an output from the connection point. circuit.
スタのコレクタとベース、第２のトランジスタのベー
ス、第３のトランジスタのベースを接続し、その接続ラ
インを入力とし、第２、第３のトランジスタのエミッタ
を同電位にし、第２及び第３のトランジスタのコレクタ
をそれぞれ第１の電流出力端子、第２の電流出力端子と
するカレントミラー構成を用いた特許請求の範囲第
（１）項記載の増幅回路。2. An in-phase dual-output amplifying unit that connects the collector and base of the first transistor, the base of the second transistor, and the base of the third transistor, and uses the connection line as an input to connect the second and the third transistors. Claim 3 (1), wherein the current mirror structure is used in which the emitters of the transistors are set to the same potential, and the collectors of the second and third transistors are the first current output terminal and the second current output terminal, respectively. The described amplifier circuit.
スタのベース、第３のトランジスタのベースを接続し、
その接続ラインを入力とし、第２、第３のトランジスタ
を同電位にし、第２及び第３のトランジスタのコレクタ
をそれぞれ第１の電流出力端子、第２の電流出力端子と
する構成とした特許請求の範囲第（１）項記載の増幅回
路。3. A base of a second transistor and a base of a third transistor are connected as an in-phase dual output amplifier,
A configuration in which the connection line is used as an input, the second and third transistors have the same potential, and the collectors of the second and third transistors are the first current output terminal and the second current output terminal, respectively. The amplifier circuit according to item (1).
応じて増幅度が正の傾きをもつ指数関数的に変化する構
成とした特許請求の範囲第（１）項記載の増幅回路。4. The amplification according to claim 1, wherein the first and second current amplification units are structured such that the amplification degree changes exponentially with a positive slope according to the input current. circuit.
続した第４のトランジスタと、第４のトランジスタのコ
レクタとベースにそのベースを接続した第５のトランジ
スタとを有し、第４のトランジスタのエミッタに抵抗を
接続したことを特徴とするカレントミラー構成とした特
許請求の範囲第（４）項記載の増幅回路。5. A fourth transistor having a collector and a base connected to the first current amplification section, and a fifth transistor having its base connected to the collector and the base of the fourth transistor. The amplifier circuit according to claim (4), which has a current mirror structure in which a resistor is connected to the emitter of the transistor.
続した第６のトランジスタと、第６のトランジスタのコ
レクタとベースにそのベースを接続した第７のトランジ
スタとを有し、第６のトランジスタのエミッタに抵抗を
接続したことを特徴とするカレントミラー構成とした特
許請求の範囲第（４）項記載の増幅回路。6. A sixth transistor having a second current amplifying section having a collector and a base connected, and a seventh transistor having a collector and a base of the sixth transistor connected to the base. The amplifier circuit according to claim (4), which has a current mirror structure in which a resistor is connected to the emitter of the transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60089246A JPH0799801B2 (en) | 1985-04-25 | 1985-04-25 | Amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60089246A JPH0799801B2 (en) | 1985-04-25 | 1985-04-25 | Amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61247111A JPS61247111A (en) | 1986-11-04 |
| JPH0799801B2 true JPH0799801B2 (en) | 1995-10-25 |
Family
ID=13965393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60089246A Expired - Fee Related JPH0799801B2 (en) | 1985-04-25 | 1985-04-25 | Amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0799801B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01223807A (en) * | 1988-03-02 | 1989-09-06 | Matsushita Electric Ind Co Ltd | Output circuit |
| DE4136605A1 (en) * | 1991-11-07 | 1993-05-13 | Philips Patentverwaltung | AMPLIFIER |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5731213A (en) * | 1980-08-01 | 1982-02-19 | Nec Corp | Electric power amplifier |
| IT1235857B (en) * | 1983-08-05 | 1992-11-16 | Sgs Microelettronica Spa | OUTPUT STAGE FOR POWER AMPLIFIERS. |
| JPH0752814B2 (en) * | 1984-10-30 | 1995-06-05 | 三洋電機株式会社 | Push-pull amplifier circuit |
-
1985
- 1985-04-25 JP JP60089246A patent/JPH0799801B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61247111A (en) | 1986-11-04 |
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| LAPS | Cancellation because of no payment of annual fees |