JPH0795081A - Integrator - Google Patents
IntegratorInfo
- Publication number
- JPH0795081A JPH0795081A JP27083293A JP27083293A JPH0795081A JP H0795081 A JPH0795081 A JP H0795081A JP 27083293 A JP27083293 A JP 27083293A JP 27083293 A JP27083293 A JP 27083293A JP H0795081 A JPH0795081 A JP H0795081A
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- Prior art keywords
- control signal
- reference potential
- active level
- circuit
- integrated output
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は積分器の関し、特にダイ
ナミックレンジを拡大した積分器に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrator, and more particularly to an integrator having a wide dynamic range.
【０００２】[0002]
【従来の技術】まず初めに、従来の最も基本的な積分器
の一例を示す回路図及びその入力電圧，出力電圧の波形
図を図９（ａ），（ｂ）に示す。2. Description of the Related Art First, FIGS. 9 (a) and 9 (b) show a circuit diagram showing an example of a most basic conventional integrator and waveform diagrams of its input voltage and output voltage.
【０００３】この積分器は、第１の入力端（＋，非反転
入力端）を接地電位点と接続し出力端から積分出力Ｖｏ
ｕｔ（出力電圧）を出力する演算増幅器ＯＰ１と、この
演算増幅器ＯＰ１の第２の入力端（−，反転入力端）と
出力端との間に接続された容量素子Ｃ１と、一端に入力
電圧Ｖｉｎを受け他端を演算増幅器ＯＰ１の入力端
（−）と接続する抵抗Ｒ１とを有する構成となってい
る。In this integrator, the first input terminal (+, non-inverting input terminal) is connected to the ground potential point and the integrated output Vo is output from the output terminal.
ut (output voltage), an operational amplifier OP1, a capacitive element C1 connected between the second input terminal (-, inverting input terminal) and the output terminal of the operational amplifier OP1, and an input voltage Vin at one end. And a resistor R1 having the other end connected to the input terminal (-) of the operational amplifier OP1.
【０００４】次に、この積分器の積分動作原理について
説明する。Next, the principle of integral operation of this integrator will be described.
【０００５】演算増幅器ＯＰ１の入力端（＋）と入力端
（−）との間はイマジナリーショートになっているもの
と仮定する。It is assumed that there is an imaginary short between the input terminal (+) and the input terminal (-) of the operational amplifier OP1.
【０００６】入力電圧Ｖｉｎと出力電圧Ｖｏｕｔとの関
係は、以下のように求めることができる。抵抗Ｒ１に流
れる電流ｉR は、 ｉR ＝Ｖｉｎ／Ｒ１，（Ｒ１は抵抗Ｒ１の抵抗値） 容量素子Ｃ１に蓄えられる電荷ｑは、 ｑ＝Ｃ１・Ｖｏｕｔ，（Ｃ１は容量素子Ｃ１の容量値） 容量素子Ｃ１に流れる電流ｉｃは、電荷ｑを時間で微分
したものとなるから ｉｃ＝ｄｑ／ｄｔ＝Ｃ１・ｄＶｏｕｔ／ｄｔ となる。The relationship between the input voltage Vin and the output voltage Vout can be obtained as follows. The current i R flowing through the resistor R1 is: i R = Vin / R1, (R1 is the resistance value of the resistor R1) The charge q stored in the capacitance element C1 is q = C1 · Vout, (C1 is the capacitance value of the capacitance element C1. ) The electric current ic flowing through the capacitive element C1 is the electric charge q differentiated with respect to time, and therefore ic = dq / dt = C1 · dVout / dt.
【０００７】演算増幅器ＯＰ１の入力端（−）における
入力インピーダンスは∞であり抵抗Ｒ１に流れた電流ｉ
R は全て容量素子Ｃ１に流入するためｉR ＝ｉｃとな
る。よって Ｃ１・ｄＶｏｕｔ／ｄｔ＝Ｖｉｎ／Ｒ１ となり、両辺を積分して整理すると、The input impedance of the operational amplifier OP1 at the input terminal (-) is ∞, and the current i flowing through the resistor R1 is i.
Since all R flows into the capacitive element C1, i R = ic. Therefore, C1 · dVout / dt = Vin / R1.
【０００８】 [0008]
【０００９】となり、入力電圧Ｖｉｎに対して積分演算
を施した出力電圧Ｖｏｕｔが得られる。Thus, the output voltage Vout obtained by performing the integral operation on the input voltage Vin is obtained.
【００１０】この積分器のステップ応答を示したものが
図９（ｂ）である。積分出力Ｖｏｕｔはステップ入力と
共に時間ｔに比例して増大し電源電圧Ｖｄｄに達すると
飽和し一定となる。FIG. 9B shows the step response of this integrator. The integrated output Vout increases with the step input in proportion to the time t, and when it reaches the power supply voltage Vdd, it is saturated and becomes constant.
【００１１】この積分器では、積分出力Ｖｏｕｔが電源
電圧Ｖｄｄに達すると飽和してしまうので、ダイナミッ
クレンジが狭い。そこで、ダイナミックレンジを拡大し
た積分器が現れた。ダイナミックレンジを拡大した積分
器の第１の例の回路図及びその入力電圧，出力電圧の波
形図を図１０（ａ），（ｂ）に示す。In this integrator, the integrated output Vout saturates when it reaches the power supply voltage Vdd, so that the dynamic range is narrow. Then, an integrator with an expanded dynamic range appeared. A circuit diagram of a first example of an integrator with an expanded dynamic range and waveform diagrams of its input voltage and output voltage are shown in FIGS. 10 (a) and 10 (b).
【００１２】この積分器は、図９に示された積分器の容
量素子Ｃ１（帰還容量）を直列接続された２つの容量素
子Ｃ１，Ｃ２に換き換え、片方の容量素子Ｃ２と並列に
スイッチ回路２ｄを設け、このスイッチ回路２ｄを、ス
イッチ制御回路３ｂにより、積分出力Ｖｏｕｔが飽和レ
ベル直前（ほぼ電源電圧Ｖｄｄ）となったとき導通状態
とし、帰還容量の値を変える（大きくなる）ようにした
ものである。This integrator replaces the capacitive element C1 (feedback capacitance) of the integrator shown in FIG. 9 with two capacitive elements C1 and C2 connected in series, and switches in parallel with one capacitive element C2. A circuit 2d is provided, and this switch circuit 2d is made conductive by the switch control circuit 3b when the integrated output Vout becomes immediately before the saturation level (approximately the power supply voltage Vdd), and the value of the feedback capacitance is changed (increased). It was done.
【００１３】例えば、容量素子Ｃ１，Ｃ２の値が等しい
ものとすると、スイッチ回路２ｄを導通状態とした直後
の積分出力ＶｏｕｔはほぼＶｄｄ／２となる。そして帰
還容量の値が２倍となるので、その後の積分出力Ｖｏｕ
ｔの増加の割合はそれまでの１／２となる。従って、積
分出力Ｖｏｕｔが次に電源電圧Ｖｄｄに到達する時間は
最初に電源電圧Ｖｄｄに到達した時間と等しくなるの
で、ダイナミックレンジが２倍に拡大されたことにな
る。For example, assuming that the capacitance elements C1 and C2 have the same value, the integrated output Vout immediately after the switch circuit 2d is made conductive is approximately Vdd / 2. Since the value of the feedback capacitance is doubled, the integrated output Vou
The rate of increase of t is ½ of that. Therefore, the time when the integrated output Vout reaches the power supply voltage Vdd next time is equal to the time when the integrated output Vout first reaches the power supply voltage Vdd, which means that the dynamic range is doubled.
【００１４】しかしながら、この積分器では、部品のば
らつきや温度特性のための管理にコストがかかり電子カ
メラ等には不向きである、という理由により、図１１に
示すような積分器（第２の例）が特開昭６３−２９２７
１７号公報に開示されている。However, this integrator is unsuitable for an electronic camera or the like because it is costly to manage due to variations in parts and temperature characteristics, so that the integrator shown in FIG. 11 (second example) is used. ) Is JP-A-63-2927
No. 17 publication.
【００１５】この積分器は、入力電圧Ｖｉｎに対する時
間積分を行う積分回路部１ｂへの入力信号をスイッチ回
路２ｅ（ゲート手段）を介して伝達し、このスイッチ回
路２ｅのオン，オフを入力制御部６により制御して入力
信号のチョッピングを行いその伝達，非伝達の比率を制
御することにより、積分回路部１ｂの積分結果が所定の
範囲内にとなるようにしている。This integrator transmits an input signal to an integrating circuit section 1b for performing time integration with respect to an input voltage Vin via a switch circuit 2e (gate means), and turns on / off the switch circuit 2e. 6, the input signal is chopped to control the ratio of transmission and non-transmission of the input signal, so that the integration result of the integration circuit unit 1b falls within a predetermined range.
【００１６】[0016]
【発明が解決しようとする課題】上述した従来のダイナ
ミックレンジを拡大した積分器は、第１の例では、帰還
容量として２つの容量素子Ｃ１，Ｃ２を直列接続しその
うちの１つを短絡することによって容量値及び積分出力
Ｖｏｕｔを制御してダイナミックレンジを拡大する構成
となっているので、２倍のダイナミックレンジを得よう
とすると帰還容量の総容量値を４倍とする必要があるた
めハードウェア量が増大するという欠点と、後段回路に
おいて帰還容量の容量値の切換え前後での時定数の変化
を補正するため、やはりハードウェア量が増大するとい
う欠点と、一般的に線形性が悪いと言われる高いレベル
において拡大処理が行なわれるため積分特性が悪いとい
う欠点と、２つの容量素子Ｃ１，Ｃ２相互の接続節点に
はスイッチ回路２ｅの開閉動作によって電荷がトラップ
される可能性が高く、トラップされた場合には積分電圧
Ｖｏｕｔにオフセット電圧として現れ積分特性が劣化す
るという欠点とがあり、また、第２の例では、入力信号
Ｖｉｎをチョッピングしてパルス列としているため、積
分出力Ｖｏｕｔが折線状になるという欠点と、積分出力
Ｖｏｕｔが積分回路部１のダイナミックレンジを逸脱し
ないように、かつサンプリング定理に基ずき入力電圧Ｖ
ｉｎをチョッピングするためハードウェア量が増大する
という欠点とがあった。In the first example, the above-mentioned conventional integrator with an expanded dynamic range has two capacitance elements C1 and C2 connected in series as feedback capacitances and one of them is short-circuited. Since the capacitance value and the integrated output Vout are controlled to expand the dynamic range, the total capacitance value of the feedback capacitors needs to be quadrupled in order to obtain a dynamic range of two times. It is said that the amount of hardware increases and that the amount of hardware also increases in order to correct the change in the time constant before and after the switching of the capacitance value of the feedback capacitor in the latter stage circuit, and that the linearity is generally poor. That is, since the enlargement processing is performed at a high level, the integration characteristic is poor, and the switch circuit 2 is provided at the connection node between the two capacitive elements C1 and C2. There is a high possibility that the charge will be trapped by the opening and closing operation of, and if trapped, it will appear as an offset voltage in the integrated voltage Vout and the integration characteristics will deteriorate, and in the second example, there will be a drawback. Are chopped to form a pulse train, the integrated output Vout has a polygonal shape, and the integrated output Vout does not deviate from the dynamic range of the integration circuit unit 1 and the input voltage Vout is based on the sampling theorem.
Since there is a chopping of in, there is a drawback that the amount of hardware increases.
【００１７】本発明の目的は、ハードウェア量が増大す
るのを抑えると共に任意のレベルでの拡大処理が可能で
あり、かつオフセット電圧，折線状等による積分特性の
劣化のない積分器を提供することにある。An object of the present invention is to provide an integrator capable of suppressing an increase in the amount of hardware, performing expansion processing at an arbitrary level, and having no deterioration of integration characteristics due to an offset voltage, a polygonal line and the like. Especially.
【００１８】[0018]
【課題を解決するための手段】本発明の積分器は、第１
の演算増幅器とこの第１の演算増幅器の入力端及び出力
端間に接続された容量素子と一端に入力信号を受け他端
を前記第１の演算増幅器の入力端と接続する抵抗とを備
え前記入力信号と対応したレベルの積分出力を出力する
積分回路部と、前記容量素子と並列接続し第１の制御信
号のアクティブレベルに応答して導通する第１のスイッ
チ回路と、第１及び第２の基準電位の範囲内にあった前
記積分出力が前記第２の基準電位を越えると前記第１の
制御信号をアクティブレベルとし前記第１のスイッチ回
路により前記積分出力を前記第１の基準電位として前記
第１の制御信号をインアクティブレベルとする第１のス
イッチ制御回路と、一端に前記第２の基準電位を受け他
端を前記第１の演算増幅器の出力端と接続し第２の制御
信号のアクティブレベルに応答して導通する第２のスイ
ッチ回路と、前記第１及び第２の基準電位の範囲内にあ
った前記積分出力が前記第１の基準電位を越えると前記
第２の制御信号をアクティブレベルとし前記第２のスイ
ッチ回路により前記積分出力を前記第２の基準電位とし
た後前記第２の制御信号をインアクティブレベルとする
第２のスイッチ制御回路と、前記第１及び第２の制御信
号のアクティブレベルとなった回数の差を記憶し出力す
る記憶手段とを有している。The integrator of the present invention has a first
An operational amplifier, a capacitive element connected between the input terminal and the output terminal of the first operational amplifier, and a resistor having one end for receiving an input signal and the other end connected to the input terminal of the first operational amplifier. An integrating circuit section that outputs an integrated output of a level corresponding to the input signal; a first switch circuit that is connected in parallel with the capacitive element and that conducts in response to the active level of the first control signal; first and second When the integrated output within the range of the reference potential exceeds the second reference potential, the first control signal is set to the active level and the first switch circuit sets the integrated output to the first reference potential. A first switch control circuit for setting the first control signal to an inactive level and a second control signal for connecting the second reference potential at one end to the output end of the first operational amplifier Active A second switch circuit that conducts in response to a bell, and the second control signal is activated when the integrated output that is within the range of the first and second reference potentials exceeds the first reference potential. A second switch control circuit which sets the integrated output to the second reference potential by the second switch circuit and then sets the second control signal to the inactive level; and the first and second controls. And a storage unit that stores and outputs the difference in the number of times the signal becomes the active level.
【００１９】また、第１のスイッチ制御回路が、第１及
び第２の基準電位の範囲内にあった積分出力が前記第２
の基準電位を越えると第１の制御信号をアクティブレベ
ルとし第１のスイッチ回路により前記積分出力を前記第
１の基準電位として前記第１の制御信号をインアクティ
ブレベルとすると共に前記第１の基準電位及びこの第１
の基準電位に対し前記第２の基準電位とは逆の極性をも
つ第３の基準電位の範囲内にあった前記積分出力が前記
第３の基準電位を越えると前記第１の制御信号をアクテ
ィブレベルとし前記第１のスイッチ回路により前記積分
出力を前記第１の基準電位として前記第１の制御信号を
インアクティブレベルとする回路であり、一端に前記第
３の基準電位を受け他端を前記積分出力の節点と接続し
第３の制御信号のアクティブレベルに応答して導通する
第３のスイッチ回路と、前記第１及び第３の基準電位の
範囲内にあった前記積分出力が前記第１の基準電位を越
えると前記第３の制御信号をアクティブレベルとし前記
第３のスイッチ回路により前記積分出力を前記第３の基
準電位とした後前記第３の制御信号をインアクティブレ
ベルとする第３のスイッチ制御回路とを設け、記憶手段
が前記積分出力の第２の基準電位越えによる第１の制御
信号のアクティブレベル及び第２の制御信号のアクティ
ブレベルとなった回路の差を記憶し出力する第１の記憶
手段と、前記積分出力の第３の基準電位越えによる第１
の制御信号のアクティブレベル及び第３の制御信号のア
クティブレベルとなった回数の差を記憶し出力する第２
の記憶手段とを含んで構成される。In addition, the first switch control circuit outputs the integrated output within the range of the first and second reference potentials as the second output.
If the first reference signal is exceeded, the first control signal is set to the active level, the first switch circuit sets the integrated output to the first reference potential, and the first control signal is set to the inactive level. Electric potential and this first
The first control signal is activated when the integrated output, which was within the range of the third reference potential having a polarity opposite to that of the second reference potential, exceeds the third reference potential. Is a circuit for setting the level of the first control signal to an inactive level by using the integrated output as the first reference potential by the first switch circuit, and receiving the third reference potential at one end and the other end at the other end. A third switch circuit connected to a node of the integrated output and rendered conductive in response to an active level of a third control signal, and the integrated output within the range of the first and third reference potentials is the first If the third control signal is exceeded, the third control signal is set to the active level, the third switch circuit sets the integrated output to the third reference potential, and then the third control signal is set to the inactive level. of Switch control circuit is provided, and the storage means stores and outputs the difference between the circuits in which the active level of the first control signal and the active level of the second control signal due to exceeding the second reference potential of the integrated output. 1 storage means, and a first by means of exceeding the third reference potential of the integrated output
A second difference for storing and outputting the difference between the number of times the active level of the third control signal and the active level of the third control signal
And storage means.
【００２０】[0020]
【実施例】次に本発明の実施例について図面を参照して
説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００２１】図１は本発明の第１の実施例を示す回路図
である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
【００２２】この実施例は、第１の入力端（＋）を接地
電位点と接続する第１の演算増幅器ＯＰ１とこの演算増
幅器ＯＰ１の第２の入力端（−）及び出力端間に接続さ
れた容量素子Ｃ１と一端に入力電圧Ｖｉｎを受け他端を
演算増幅器ＯＰ１の第２の入力端（−）と接続する抵抗
Ｒ１とを備え演算増幅器ＯＰ１の出力端から積分出力Ｖ
ｏｕｔを出力する積分回路部１と、容量素子Ｃ１と並列
接続し第１の制御信号ＳＣ１のアクティブレベルに応答
して導通する第１のスイッチ回路２ａと、第１の入力端
（＋）に積分出力Ｖｏｕｔを受け第２の入力端（−）に
基準電位Ｖｒｅｆを受け出力端から制御信号ＳＣ１を出
力する第２の演算増幅器ＯＰ２を備え接地電位（第１の
基準電位）及び基準電位Ｖｒｅｆ（第２の基準電位）の
範囲内にあった積分出力Ｖｏｕｔが基準電位Ｖｒｅｆを
越えると制御信号ＳＣ１をアクティブレベルとしスイッ
チ回路２ａにより容量素子Ｃ１の電荷を放電し積分出力
Ｖｏｕｔを接地電位として制御信号ＳＣ１をインアクテ
ィブレベルとする第１のスイッチ制御回路３と、一端に
基準電位Ｖｒｅｆを受け他端を演算増幅器ＯＰ１の出力
端と接続し第２の制御信号ＳＣ２のアクティブレベルに
応答して導通する第２のスイッチ回路２ｂと、制御信号
ＳＣ１のアクティブレベルに応答してセット（記憶内容
“１”）され制御信号ＳＣ２のアクティブレベルに応答
してリセット（記憶内容“０”）されて制御信号ＳＣ
１，ＳＣ２のアクティブレベルとなった回数の差（但
し、１，０のみ）を記憶し出力（ＤＮ）する記憶手段の
ラッチ回路ＬＣ１を含みかつ第１の入力端（＋）を接地
電位点と接続し第２の入力端（−）に積分出力Ｖｏｕｔ
を受ける第３の演算増幅器ＯＰ３とこの演算増幅器ＯＰ
３の出力及びラッチ回路ＬＣ１の出力のＡＮＤ処理を行
い制御信号ＳＣ２として出力する論理ゲートＧ１を備え
接地電位及び基準電位Ｖｒｅｆの範囲内にあった積分出
力Ｖｏｕｔが接地電位を越えると制御信号ＳＣ２をアク
ティブレベルとしスイッチ回路２ｂにより積分出力Ｖｏ
ｕｔを基準電位Ｖｒｅｆとして制御信号ＳＣ２をインア
クティブレベルとする第２のスイッチ制御回路４とを有
する構成となっている。In this embodiment, a first operational amplifier OP1 connecting the first input terminal (+) to the ground potential point and a second input terminal (-) and an output terminal of the operational amplifier OP1 are connected. A capacitive element C1 and a resistor R1 which receives the input voltage Vin at one end and connects the other end to the second input end (-) of the operational amplifier OP1.
an integrating circuit section 1 that outputs out, a first switch circuit 2a that is connected in parallel with the capacitive element C1 and is conductive in response to the active level of the first control signal SC1, and an integrating circuit at the first input terminal (+). A second operational amplifier OP2 that receives the output Vout and receives the reference potential Vref at the second input terminal (−) and outputs the control signal SC1 from the output terminal is provided, and the ground potential (first reference potential) and the reference potential Vref (first reference potential). When the integrated output Vout within the range of (reference potential of 2) exceeds the reference potential Vref, the control signal SC1 is set to an active level and the switch circuit 2a discharges the electric charge of the capacitive element C1 to set the integrated output Vout to the ground potential. Is connected to the output terminal of the operational amplifier OP1 and the other end is connected to the output terminal of the operational amplifier OP1. The second switch circuit 2b which is rendered conductive in response to the active level of the control signal SC2 and is set (stored content "1") in response to the active level of the control signal SC1 and reset in response to the active level of the control signal SC2. (Stored content “0”) Control signal SC
1, which includes a latch circuit LC1 of storage means for storing and outputting (DN) the number of times the active levels of SC1 and SC2 (however, only 1,0) and the first input terminal (+) as a ground potential point. Connected to the second input terminal (-) and the integrated output Vout
And a third operational amplifier OP3 for receiving the operational amplifier OP3
When the integrated output Vout within the range of the ground potential and the reference potential Vref exceeds the ground potential, it is provided with a logic gate G1 which performs an AND process of the output of 3 and the output of the latch circuit LC1 and outputs the control signal SC2. The integrated output Vo is set by the switch circuit 2b to the active level.
The second switch control circuit 4 sets the control signal SC2 to the inactive level with ut as the reference potential Vref.
【００２３】次にこの実施例の動作について説明する。
図２はこの実施例の動作を説明するための入力電圧Ｖｉ
ｎ及び出力電圧（積分出力）Ｖｏｕｔの波形図である。Next, the operation of this embodiment will be described.
FIG. 2 shows an input voltage Vi for explaining the operation of this embodiment.
It is a wave form diagram of n and output voltage (integrated output) Vout.
【００２４】初期状態において、スイッチ回路２ａ，２
ｂは非導通状態、ラッチ回路ＬＣ１はリセット状態
（“０”）となっている。In the initial state, the switch circuits 2a, 2
b is in a non-conductive state, and the latch circuit LC1 is in a reset state (“0”).
【００２５】入力電圧Ｖｉｎとして、＋１のステップ状
の電圧を入力すると積分出力Ｖｏｕｔは時間ｔと共に直
線的に増大する。積分出力Ｖｏｕｔが基準電位Ｖｒｅｆ
を越えると演算増幅器ＯＰ２の出力、すなわち制御信号
ＳＣ１がアクティブレベル（高レベル）となりスイッチ
回路２ａを導通状態とすると共にラッチ回路ＬＣ１をセ
ット（“１”）する。スイッチ回路２ａが導通状態にな
ると容量素子Ｃ１の電荷がこのスイッチ回路２ａを通し
て放電されるので、積分出力Ｖｏｕｔは接地電位（０
Ｖ）となる。この時点で制御信号ＳＣ１はインアクティ
ブレベルとなる。従ってスイッチ回路２ａは非導通状態
となり積分出力Ｖｏｕｔは接地電位から再び上昇する。When a +1 step voltage is input as the input voltage Vin, the integrated output Vout increases linearly with time t. The integrated output Vout is the reference potential Vref
When the voltage exceeds the threshold, the output of the operational amplifier OP2, that is, the control signal SC1 becomes the active level (high level) to make the switch circuit 2a conductive and set the latch circuit LC1 ("1"). When the switch circuit 2a becomes conductive, the electric charge of the capacitive element C1 is discharged through the switch circuit 2a, so that the integrated output Vout becomes the ground potential (0
V). At this point, the control signal SC1 becomes inactive level. Therefore, the switch circuit 2a becomes non-conductive, and the integrated output Vout rises again from the ground potential.
【００２６】積分出力Ｖｏｕｔと制御信号ＳＣ１，ＳＣ
２のアクティブレベルの回数の差の信号（以下、スイッ
チオン回数差信号という）ＤＮとを受けた後段の回路
は、スイッチオン回数差信号ＤＮが“０”のときは積分
出力Ｖｏｕｔをそのまま、“１”のときは積分出力Ｖｏ
ｕｔに基準電位Ｖｒｅｆを加算してダイナミックレンジ
が拡大された積分出力を得ることができる。Integrated output Vout and control signals SC1 and SC
When the switch-on number difference signal DN is “0”, the circuit at the subsequent stage receiving the signal of the difference in the number of active levels of 2 (hereinafter referred to as the switch-on number difference signal) DN keeps the integrated output Vout as it is. When it is 1 ”, the integrated output Vo
By adding the reference potential Vref to ut, it is possible to obtain an integrated output with an expanded dynamic range.
【００２７】入力電圧Ｖｉｎの＋１の電圧が継続する
と、積分出力Ｖｏｕｔは再び基準電位Ｖｒｅｆを越えて
制御信号ＳＣ１がアクティブレベルとなるが、このとき
ラッチ回路ＬＣ１はセット状態となっているので、ラッ
チ回路ＬＣ１による制御信号ＳＣ１，ＳＣ２のアクティ
ブレベルの回数の差を正確に記憶できなくなる。従って
この実施例ではダイナミックレンジが拡大された積分出
力を２×Ｖｒｅｆ未満に限定する必要がある。しかし、
基準電位Ｖｒｅｆをほぼ電源電圧Ｖｄｄとした場合、こ
の積分器のダイナミックレンジはほぼ２倍に拡大された
ことになる。When the +1 voltage of the input voltage Vin continues, the integrated output Vout again exceeds the reference potential Vref and the control signal SC1 becomes the active level. At this time, the latch circuit LC1 is in the set state, so that the latch circuit LC1 is latched. It becomes impossible to accurately store the difference in the number of times of the active levels of the control signals SC1 and SC2 by the circuit LC1. Therefore, in this embodiment, it is necessary to limit the integrated output with the expanded dynamic range to less than 2 × Vref. But,
When the reference potential Vref is approximately the power supply voltage Vdd, the dynamic range of this integrator is approximately doubled.
【００２８】入力電圧Ｖｉｎの＋１の電圧を制御信号Ｓ
Ｃ１が再びアクティブレベルとなる前に−１の電圧にす
ると（図２）、積分出力Ｖｏｕｔは時間ｔと共に直線的
に減少する。そして接地電位（０Ｖ）を越えると演算増
幅器ＯＰ３の出力がアクティブレベルとなり、これとラ
ッチ回路ＬＣ１のセットレベル（“１”）とを受けた論
理ゲートＧ１の出力、すなわち制御信号ＳＣ２はアクテ
ィブレベルとなってスイッチ回路２ｂを導通状態とする
と共にラッチ回路ＬＣ１をリセットする。スイッチ回路
２ｂの導通により積分出力Ｖｏｕｔは基準電位Ｖｒｅｆ
となりこの時点で制御信号ＳＣ２がインアクティブレベ
ルとなる。The voltage +1 of the input voltage Vin is the control signal S
If the voltage is set to -1 before C1 becomes active level again (FIG. 2), the integrated output Vout decreases linearly with time t. When the voltage exceeds the ground potential (0V), the output of the operational amplifier OP3 becomes an active level, and the output of the logic gate G1 which receives this and the set level (“1”) of the latch circuit LC1, that is, the control signal SC2 becomes an active level. Then, the switch circuit 2b is turned on and the latch circuit LC1 is reset. Due to the conduction of the switch circuit 2b, the integrated output Vout becomes the reference potential Vref.
At this point, the control signal SC2 becomes inactive level.
【００２９】入力電圧Ｖｉｎの−１の電圧が継続すると
積分出力Ｖｏｕｔは時間と共に減する。この場合も、入
力電圧Ｖｉｎの＋１の電圧のときと同様に、制御信号Ｓ
Ｃ２が２回以上連続してアクティブレベルとなるのを避
ける必要がある。When the voltage -1 of the input voltage Vin continues, the integrated output Vout decreases with time. In this case as well, as in the case where the input voltage Vin is +1, the control signal S
It is necessary to avoid that C2 becomes active level twice or more continuously.
【００３０】図３は本発明の第２の実施例を示す回路
図、図４はこの実施例の入力電圧及び出力電圧の波形図
である。FIG. 3 is a circuit diagram showing a second embodiment of the present invention, and FIG. 4 is a waveform diagram of input voltage and output voltage of this embodiment.
【００３１】この実施例が第１の実施例と相違する点
は、第１の実施例におけるラッチ回路ＬＣ１の代りに、
第１の制御信号ＳＣ１のアクティブレベルに応答してカ
ウントアップし第２の制御信号ＳＣ２のアクティブレベ
ルに応答してカウントダウンするカウンタ回路４１を設
け、このカウンタ回路４１の出力（ＤＮ）のＯＲ処理結
果を論理ゲートＧ１の一方の入力端に伝達する論理ゲー
トＧ２を設けた点にある。The difference between this embodiment and the first embodiment is that instead of the latch circuit LC1 in the first embodiment,
A counter circuit 41 that counts up in response to the active level of the first control signal SC1 and counts down in response to the active level of the second control signal SC2 is provided, and the OR processing result of the output (DN) of this counter circuit 41 is provided. Is provided at one input end of the logic gate G1.
【００３２】この実施例では、カウンタ回路４１の出
力、すなわちスイッチオン回数差信号ＤＮのビット数を
Ｎとすると、その値が“０”から（２N −１）までの範
囲なら、制御信号ＳＣ１，ＳＣ２を連続してアクティブ
レベルとすることができる。従って、基準電位Ｖｒｅｆ
を電源電圧Ｖｄｄとほぼ等しく設定すると、電源電圧Ｖ
ｄｄのほぼ２N 倍のダイナミックレンジを得ることがで
きる。なお、論理ゲートＧ２は、スイッチオン回数差信
号ＤＮが１〜（２N −１）の範囲内で制御信号ＳＣ２を
アクティブレベルとするためのものである。In this embodiment, assuming that the output of the counter circuit 41, that is, the number of bits of the switch-on number difference signal DN is N, if the value is in the range of "0" to (2 N -1), the control signal SC1 , SC2 can be continuously set to the active level. Therefore, the reference potential Vref
Is set to be approximately equal to the power supply voltage Vdd, the power supply voltage Vdd
A dynamic range approximately 2 N times dd can be obtained. The logic gate G2 is for setting the control signal SC2 to the active level within the range of the switch-on number difference signal DN of 1 to (2 N -1).
【００３３】これら実施例においては、容量素子は１つ
で済み従来の第１の例のような時定数の変化に対する補
正や第２の例のような入力信号のチョッピング制御のた
めの回路が不要となるのでハードウェア量が増大するの
を抑えることができ、また、第１及び第２の基準電位を
任意に設定できるので線形性の高い範囲で拡大処理がで
き、かつオフセット電圧の発生がなく折線状とならない
ので、積分特性の劣化を防止することができる。In these embodiments, only one capacitive element is required, and a circuit for correction for changes in the time constant as in the conventional first example and a circuit for chopping control of the input signal as in the second example is unnecessary. Therefore, it is possible to suppress an increase in the amount of hardware, and since the first and second reference potentials can be arbitrarily set, it is possible to perform expansion processing in a highly linear range and to prevent the occurrence of offset voltage. Since it does not have a broken line shape, it is possible to prevent deterioration of the integral characteristic.
【００３４】図５は本発明の第３の実施例を示す回路
図、図６はこの実施例の入力電圧及び出力電圧の波形図
である。FIG. 5 is a circuit diagram showing a third embodiment of the present invention, and FIG. 6 is a waveform diagram of input voltage and output voltage of this embodiment.
【００３５】この実施例が図１に示された第１の実施例
と相違する点は、第１のスイッチ制御回路３ａを、第１
の入力端に積分出力を受け第２の入力端に第２の基準電
位Ｖｒｅｆを受ける演算増幅器ＯＰ２のほかに、第１の
入力端に第２の基準電位Ｖｒｅｆとは逆極性の第３の基
準電位−Ｖｒｅｆを受け第２の入力端に積分出力Ｖｏｕ
ｔを受ける演算増幅器ＯＰ４と、これら演算増幅器ＯＰ
２，ＯＰ４の出力信号のＯＲ処理を行う論理ゲートＧ３
とを含み、第１及び第２の基準電位の範囲内にあった積
分出力Ｖｏｕｔが第２の基準電位Ｖｒｅｆを越えると第
１の制御信号ＳＣ１ａをアクティブレベルとし第１のス
イッチ回路２ａにより積分出力Ｖｏｕｔを第１の基準電
位Ｖｒｅｆとして第１の制御信号ＳＣ１ａをインアクテ
ィブレベルとすると共に、第１及び第３の基準電位の範
囲内にあった積分出力Ｖｏｕｔが第３の基準電位−Ｖｒ
ｅｆを越えると第１の制御信号ＳＣ１ａをアクティブレ
ベルとし第１のスイッチ回路２ａにより積分出力Ｖｏｕ
ｔを第１の基準電位として第１の制御信号ＳＣ１ａをイ
ンアクティブレベルとする回路とし、一端に第３の基準
電位−Ｖｒｅｆを受け他端を演算増幅器ＯＰ１の出力端
と接続し第３の制御信号ＳＣ３のアクティブレベルに応
答して導通する第３のスイッチ回路２ｃと、第２のスイ
ッチ制御回路４の演算増幅器ＯＰ３の出力信号をレベル
反転するインバータＩＶ１と第１のスイッチ制御回路３
ａの演算増幅器ＯＰ４の出力信号のアクティブレベルで
セットされ第３の制御信号ＳＣ３でリセットされるラッ
チ回路ＬＣ２とこのラッチ回路ＬＣ２の出力信号及びイ
ンバータＩＶ１の出力信号のＡＮＤ処理を行い第３の制
御信号ＳＣ３を出力する論理ゲートＧ４とを備え、第１
及び第３の基準電位の範囲内にあった積分出力Ｖｏｕｔ
が第１の基準電位を越えると第３の制御信号ＳＣ３をア
クティブレベルとし第３のスイッチ回路２ｃにより積分
出力Ｖｏｕｔを第３の基準電位−Ｖｒｅｆとした後第３
の制御信号ＳＣ３をインアクティブレベルとする第３の
スイッチ制御回路５とを設け、ラッチ回路ＬＣ１を、積
分出力Ｖｏｕｔの第２の基準電位Ｖｒｅｆ越えによる第
１の制御信号ＳＣ１ａのアクティブレベル、すなわち演
算増幅器ＯＰ２の出力信号のアクティブレベル及び第２
の制御信号ＳＣ２のアクティブレベルとなった回数の差
を記憶し出力（ＤＮ１）する第１の記憶手段とし、ラッ
チ回路ＬＣ２を、積分出力Ｖｏｕｔの第３の基準電位越
えによる第１の制御信号ＳＣ１ａのアクティブレベル、
すなわち演算増幅器ＯＰ４の出力信号のアクティブレベ
ル及び第３の制御信号ＳＣ３のアクティブレベルとなっ
た回数の差を記憶し出力する第２の記憶手段とした点に
ある。This embodiment differs from the first embodiment shown in FIG. 1 in that the first switch control circuit 3a is
In addition to the operational amplifier OP2 which receives the integrated output at its input terminal and the second reference potential Vref at its second input terminal, a third reference having a polarity opposite to that of the second reference potential Vref at its first input terminal. The integrated output Vou is received at the second input terminal by receiving the potential -Vref.
operational amplifier OP4 that receives t and these operational amplifiers OP4
2, a logic gate G3 for ORing the output signals of OP4
And the integrated output Vout within the range of the first and second reference potentials exceeds the second reference potential Vref, the first control signal SC1a is set to an active level and the first switch circuit 2a outputs the integrated output. Vout is set to the first reference potential Vref, the first control signal SC1a is set to the inactive level, and the integrated output Vout within the range of the first and third reference potentials is the third reference potential −Vr.
When ef is exceeded, the first control signal SC1a is set to an active level and the integrated output Vou is output by the first switch circuit 2a.
A circuit that sets t as a first reference potential and sets the first control signal SC1a to an inactive level, receives the third reference potential −Vref at one end, and connects the other end to the output end of the operational amplifier OP1 to perform the third control. The third switch circuit 2c which is rendered conductive in response to the active level of the signal SC3, the inverter IV1 which inverts the level of the output signal of the operational amplifier OP3 of the second switch control circuit 4, and the first switch control circuit 3
The third control is performed by ANDing the latch circuit LC2 set at the active level of the output signal of the operational amplifier OP4 of a and reset by the third control signal SC3, the output signal of the latch circuit LC2, and the output signal of the inverter IV1. A logic gate G4 for outputting a signal SC3,
And the integrated output Vout that was within the range of the third reference potential
Exceeds the first reference potential, the third control signal SC3 is set to the active level and the third switch circuit 2c sets the integrated output Vout to the third reference potential −Vref and then the third
And the third switch control circuit 5 for setting the control signal SC3 of the control signal SC3 to the inactive level, and the latch circuit LC1 is driven to the active level of the first control signal SC1a when the second reference potential Vref of the integrated output Vout is exceeded, that is, the calculation. The active level of the output signal of the amplifier OP2 and the second
Of the control signal SC2 as the first storage means for storing and outputting (DN1) the number of times that the control signal SC2 has become the active level, and the latch circuit LC2 is used as the first control signal SC1a by exceeding the third reference potential of the integrated output Vout. Active level of
That is, the second storage means stores and outputs the difference between the active level of the output signal of the operational amplifier OP4 and the number of times the active level of the third control signal SC3 has become active.
【００３６】第１の実施例では、第１の基準電位（接地
電位）に対し積分出力Ｖｏｕｔが負となる入力信号Ｖｉ
ｎに対してはそのダイナミックレンジを拡大することは
できないが、この第３の実施例では、正負ともダイナミ
ックレンジを拡大することができる。この積分出力Ｖｏ
ｕｔの正の側のダイナミックレンジの拡大には第１の実
施例と同じ、第１のスイッチ制御回路３ａの演算増幅器
ＯＰ２と第２のスイッチ回路２ａ，２ｂとが関与し、負
の側のダイナミックレンジの拡大には、第１のスイッチ
制御回路３ａの演算増幅器ＯＰ４と第３のスイッチ制御
回路５と第１，第３のスイッチ２ａ，２ｃとが関与す
る。負の側のダイナミックレンジの拡大動作は、正の側
の場合（第１の実施例）に比べ、極性が逆になっている
だけであるので、これ以上の説明は省略する。In the first embodiment, the input signal Vi whose integrated output Vout is negative with respect to the first reference potential (ground potential).
Although the dynamic range cannot be expanded for n, the dynamic range can be expanded for both positive and negative in the third embodiment. This integrated output Vo
The expansion of the dynamic range on the positive side of ut involves the operational amplifier OP2 of the first switch control circuit 3a and the second switch circuits 2a and 2b, which is the same as in the first embodiment. The operational amplifier OP4 of the first switch control circuit 3a, the third switch control circuit 5, and the first and third switches 2a and 2c are involved in expanding the range. The operation of expanding the dynamic range on the negative side is only opposite in polarity as compared with the case of the positive side (first embodiment), and therefore further description is omitted.
【００３７】図７は本発明の第４の実施例の回路図、図
８はこの実施例の入力電圧及び出力電圧の波形図であ
る。FIG. 7 is a circuit diagram of the fourth embodiment of the present invention, and FIG. 8 is a waveform diagram of input voltage and output voltage of this embodiment.
【００３８】この実施例は、第３の実施例におけるラッ
チ回路ＬＣ１，ＬＣ２の代りに、積分出力Ｖｏｕｔの第
２の基準電位Ｖｒｅｆ越えによる第１の制御信号ＳＣ１
ａのアクティブレベル、すなわち演算増幅器ＯＰ２の出
力信号のアクティブレベルに応答してカウントアップし
第２の制御信号ＳＣ２のアクティブレベルに応答してカ
ウントダウンするカウンタ回路４１、及び積分出力Ｖｏ
ｕｔの第３の基準電位−Ｖｒｅｆ越えによる第１の制御
信号ＳＣ１ａのアクティブレベル、すなわち演算増幅器
ＯＰ４の出力信号のアクティブレベルに応答してカウン
トアップし第３の制御信号ＳＣ３のアクティブレベルに
応答してカウントダウンするカウンタ回路５１を設けた
ものである。In this embodiment, instead of the latch circuits LC1 and LC2 in the third embodiment, a first control signal SC1 is generated by exceeding the second reference potential Vref of the integrated output Vout.
The counter circuit 41 that counts up in response to the active level of a, that is, the active level of the output signal of the operational amplifier OP2, and counts down in response to the active level of the second control signal SC2, and the integrated output Vo.
In response to the active level of the first control signal SC1a due to exceeding the third reference potential −Vref of ut, that is, the active level of the output signal of the operational amplifier OP4, the count-up is performed and the count level is increased in response to the active level of the third control signal SC3. A counter circuit 51 for counting down is provided.
【００３９】この実施例の動作は、第３の実施例のラッ
チ回路ＬＣ１，ＬＣ２をカウンタ回路４１，５１に代え
ただけであり、カウンタ回路４１の動作は第２の実施例
と同一であり、カウンタ回路５１の動作もカウントアッ
プで、カウントダウンする入力信号が異なるだけで他の
動作はカウンタ回路４１と同じであるので、これ以上の
説明は省略する。The operation of this embodiment is the same as that of the second embodiment except that the latch circuits LC1 and LC2 of the third embodiment are replaced by the counter circuits 41 and 51. The operation of the counter circuit 51 also counts up, and since the other operation is the same as the counter circuit 41 except that the input signal to be counted down is different, further description will be omitted.
【００４０】[0040]
【発明の効果】以上説明したように本発明は、積分回路
部の帰還容量を１つの容量素子とし、この容量素子と並
列に第１のスイッチ回路を設けて積分出力が第１及び第
２（第３）の基準電位の範囲内から第２（第３）の基準
電位を越えたときにこの第１のスイッチ回路をオンとし
て積分出力を第１の基準電位した後この第１のスイッチ
回路をオフとし、一端に第２（第３）の基準電位を受け
他端を積分出力端と接続する第２のスイッチ回路を設け
て積分出力が第１及び第２（第３）の基準電位の範囲内
から第１の基準電位を越えたときにこの第２（第３）の
スイッチ回路をオンとして積分出力を第２（第３）の基
準電位とした後この第２（第３）のスイッチ回路をオフ
とし、かつ第１及び第２（第３）のスイッチ回路をオン
とした回数の差を記憶し出力する記憶手段を設けた構成
とすることにより、積分回路部の帰還容量が１つの容量
素子で済み時定数変化の補正回路や入力チョッピング用
の制御回路が不要となるのでハードウェア量が増大する
のを抑えることができ、線形性の高い範囲内でダイナミ
ックレンジ拡大処理を可能としオフセット電圧の発生を
抑え、かつ折線状とならないので、積分特性の劣化を防
止することができる効果がある。As described above, according to the present invention, the feedback capacitance of the integrating circuit section is one capacitance element, and the first switching circuit is provided in parallel with this capacitance element so that the integrated output has the first and second ( When the second (third) reference potential is exceeded from within the (third) reference potential range, the first switch circuit is turned on to set the integrated output to the first reference potential, and then the first switch circuit is turned on. A second switch circuit that is turned off and receives the second (third) reference potential at one end and connects the other end to the integration output end is provided, and the integration output is in the range of the first and second (third) reference potentials. This second (third) switch circuit is turned on when the first reference potential is exceeded from the inside, and the integrated output is set to the second (third) reference potential. Is turned off, and the first and second (third) switch circuits are turned on. By providing the storage means for storing and outputting the memory, the feedback capacitance of the integrating circuit unit is only required to be one capacitance element, and the correction circuit for the time constant change and the control circuit for input chopping are unnecessary, so that the amount of hardware is reduced. Since it is possible to suppress the increase, it is possible to expand the dynamic range within a range of high linearity, suppress the generation of offset voltage, and prevent the voltage from becoming a broken line. Therefore, it is possible to prevent the deterioration of the integral characteristic. .
【図１】本発明の第１の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
【図２】図１に示された実施例の動作を説明するための
入力電圧及び出力電圧の波形図である。2 is a waveform diagram of an input voltage and an output voltage for explaining the operation of the embodiment shown in FIG.
【図３】本発明の第２の実施例を示す回路図である。FIG. 3 is a circuit diagram showing a second embodiment of the present invention.
【図４】図３に示された実施例の動作を説明するための
入力電圧及び出力電圧の波形図である。FIG. 4 is a waveform diagram of an input voltage and an output voltage for explaining the operation of the embodiment shown in FIG.
【図５】本発明の第３の実施例を示す回路図である。FIG. 5 is a circuit diagram showing a third embodiment of the present invention.
【図６】図５に示された実施例の動作を説明するための
入力電圧及び出力電圧の波形図である。6 is a waveform diagram of an input voltage and an output voltage for explaining the operation of the embodiment shown in FIG.
【図７】本発明の第４の実施例を示す回路図である。FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention.
【図８】図７に示された実施例の動作を説明するための
入力電圧及び出力電圧の波形図である。8 is a waveform diagram of an input voltage and an output voltage for explaining the operation of the embodiment shown in FIG.
【図９】従来の積分器の最も基本的な一例を示す回路図
及びその入力電圧，出力電圧の波形図である。FIG. 9 is a circuit diagram showing a most basic example of a conventional integrator and waveform diagrams of its input voltage and output voltage.
【図１０】ダイナミックレンジを拡大した従来の積分器
の第１の例を示す回路図及びその入力電圧，出力電圧の
波形図である。FIG. 10 is a circuit diagram showing a first example of a conventional integrator with an expanded dynamic range and waveform diagrams of its input voltage and output voltage.
【図１１】ダイナミックレンジを拡大した従来の積分器
の第２の例を示すブロック図である。FIG. 11 is a block diagram showing a second example of a conventional integrator with an expanded dynamic range.
１，１ａ，１ｂ 積分回路部 ２ａ〜２ｅ スイッチ回路 ３，３ａ，３ｂ，４，４ａ，５，５ａ スイッチ制御
回路 ６ 入力制御部 ４１，５１ カウンタ回路 Ｃ１，Ｃ２ 容量素子 Ｇ１〜Ｇ５ 論理ゲート ＩＶ１ インバータ ＬＣ１，ＬＣ２ ラッチ回路 ＯＰ１〜ＯＰ４ 演算増幅器 Ｒ１ 抵抗1, 1a, 1b Integration circuit section 2a-2e Switch circuit 3, 3a, 3b, 4, 4a, 5, 5a Switch control circuit 6 Input control section 41, 51 Counter circuit C1, C2 Capacitive element G1-G5 Logic gate IV1 Inverter LC1, LC2 Latch circuit OP1 to OP4 Operational amplifier R1 Resistance
Claims (8)
器の入力端及び出力端間に接続された容量素子と一端に
入力信号を受け他端を前記第１の演算増幅器の入力端と
接続する抵抗とを備え前記入力信号と対応したレベルの
積分出力を出力する積分回路部と、前記容量素子と並列
接続し第１の制御信号のアクティブレベルに応答して導
通する第１のスイッチ回路と、第１及び第２の基準電位
の範囲内にあった前記積分出力が前記第２の基準電位を
越えると前記第１の制御信号をアクティブレベルとし前
記第１のスイッチ回路により前記積分出力を前記第１の
基準電位として前記第１の制御信号をインアクティブレ
ベルとする第１のスイッチ制御回路と、一端に前記第２
の基準電位を受け他端を前記第１の演算増幅器の出力端
と接続し第２の制御信号のアクティブレベルに応答して
導通する第２のスイッチ回路と、前記第１及び第２の基
準電位の範囲内にあった前記積分出力が前記第１の基準
電位を越えると前記第２の制御信号をアクティブレベル
とし前記第２のスイッチ回路により前記積分出力を前記
第２の基準電位とした後前記第２の制御信号をインアク
ティブレベルとする第２のスイッチ制御回路と、前記第
１及び第２の制御信号のアクティブレベルとなった回数
の差を記憶し出力する記憶手段とを有することを特徴と
する積分器。1. A first operational amplifier and a capacitive element connected between an input terminal and an output terminal of the first operational amplifier, one end of which receives an input signal, and the other end of which is an input terminal of the first operational amplifier. An integrating circuit section that includes a resistor to be connected and outputs an integrated output of a level corresponding to the input signal; and a first switch circuit that is connected in parallel with the capacitive element and is conductive in response to an active level of a first control signal. And when the integrated output within the range of the first and second reference potentials exceeds the second reference potential, the first control signal is set to an active level and the first switch circuit outputs the integrated output. A first switch control circuit that sets the first control signal to an inactive level as the first reference potential, and the second switch control circuit at one end.
A second switch circuit which receives the reference potential of the second operational amplifier and which has the other end connected to the output terminal of the first operational amplifier and which conducts in response to the active level of the second control signal; and the first and second reference potentials. When the integrated output within the range of exceeds the first reference potential, the second control signal is set to an active level and the second switch circuit sets the integrated output to the second reference potential, and A second switch control circuit for setting the second control signal to an inactive level, and a storage means for storing and outputting a difference in the number of times the first and second control signals have become the active level. And the integrator.
ブレベルに応答してセットされ第２の制御信号のアクテ
ィブレベルに応答してリセットされるラッチ回路で構成
された請求項１記載の積分器。2. The integration according to claim 1, wherein the storage means comprises a latch circuit which is set in response to the active level of the first control signal and is reset in response to the active level of the second control signal. vessel.
ブレベルに応答してカウントアップし第２の制御信号の
アクティブレベルに応答してカウントダウンするカウン
タで構成された請求項１記載の積分器。3. The integrator according to claim 1, wherein the storage means comprises a counter that counts up in response to the active level of the first control signal and counts down in response to the active level of the second control signal. .
端に積分出力を受け第２の入力端に第２の基準電位を受
け出力端から第１の制御信号を出力する第２の演算増幅
器で構成され、第２のスイッチ制御回路が、第１の入力
端に第１の基準電位を受け第２の入力端に前記積分出力
を受け出力端から第２の制御信号と対応する信号を出力
する第３の演算増幅器を含んで構成された請求項１記載
の積分器。4. A second switch control circuit, wherein a first input terminal receives an integrated output, a second input terminal receives a second reference potential, and an output terminal outputs a first control signal. A signal corresponding to the second control signal from the output end of the second switch control circuit, the second switch control circuit receiving the first reference potential at the first input end and the integrated output at the second input end; The integrator according to claim 1, wherein the integrator includes a third operational amplifier that outputs
２の基準電位の範囲内にあった積分出力が前記第２の基
準電位を越えると第１の制御信号をアクティブレベルと
し第１のスイッチ回路により前記積分出力を前記第１の
基準電位として前記第１の制御信号をインアクティブレ
ベルとすると共に前記第１の基準電位及びこの第１の基
準電位に対し前記第２の基準電位とは逆の極性をもつ第
３の基準電位の範囲内にあった前記積分出力が前記第３
の基準電位を越えると前記第１の制御信号をアクティブ
レベルとし前記第１のスイッチ回路により前記積分出力
を前記第１の基準電位として前記第１の制御信号をイン
アクティブレベルとする回路であり、一端に前記第３の
基準電位を受け他端を前記積分出力の節点と接続し第３
の制御信号のアクティブレベルに応答して導通する第３
のスイッチ回路と、前記第１及び第３の基準電位の範囲
内にあった前記積分出力が前記第１の基準電位を越える
と前記第３の制御信号をアクティブレベルとし前記第３
のスイッチ回路により前記積分出力を前記第３の基準電
位とした後前記第３の制御信号をインアクティブレベル
とする第３のスイッチ制御回路とを設け、記憶手段が前
記積分出力の第２の基準電位越えによる第１の制御信号
のアクティブレベル及び第２の制御信号のアクティブレ
ベルとなった回路の差を記憶し出力する第１の記憶手段
と、前記積分出力の第３の基準電位越えによる第１の制
御信号のアクティブレベル及び第３の制御信号のアクテ
ィブレベルとなった回数の差を記憶し出力する第２の記
憶手段とを含んで構成された請求項１記載の積分器。5. The first switch control circuit sets the first control signal to an active level when the integrated output within the range of the first and second reference potentials exceeds the second reference potential. Switch circuit to use the integrated output as the first reference potential to set the first control signal to an inactive level, and the first reference potential and the second reference potential with respect to the first reference potential. Is within the range of the third reference potential having the opposite polarity, the integrated output is the third
A circuit in which the first control signal is set to an active level and the integrated output is set to the first reference potential by the first switch circuit to set the first control signal to an inactive level when the reference potential is exceeded. The third reference potential is received at one end and the other end is connected to the node of the integrated output.
Which conducts in response to the active level of the control signal of the third
Switch circuit, and when the integrated output within the range of the first and third reference potentials exceeds the first reference potential, the third control signal is set to an active level.
And a third switch control circuit for setting the third control signal to an inactive level after the integrated output is set to the third reference potential by the switch circuit of FIG. First storage means for storing and outputting the difference between the circuits having the active level of the first control signal and the active level of the second control signal due to the potential exceeding, and the third storage means for exceeding the third reference potential of the integrated output. 2. The integrator according to claim 1, further comprising a second storage unit that stores and outputs a difference between the number of times the active level of the first control signal and the active level of the third control signal become the active level.
準電位越えによる第１の制御信号のアクティブレベルに
応答してセットされ第２の制御信号のアクティブレベル
に応答してリセットされる第１のラッチ回路で構成さ
れ、第２の記憶手段が、前記積分出力の第３の基準電位
越えによる第１の制御信号のアクティブレベルに応答し
てセットされ第３の制御信号のアクティブレベルに応答
してリセットされる第２のラッチ回路で構成された請求
項５記載の積分器。6. The first storage means is set in response to the active level of the first control signal due to exceeding the second reference potential of the integrated output, and reset in response to the active level of the second control signal. The second storage means is set in response to the active level of the first control signal caused by exceeding the third reference potential of the integrated output, and the second storage means is set to the active level of the third control signal. 6. The integrator according to claim 5, comprising a second latch circuit which is reset in response to the.
準電位越えによる第１の制御信号のアクティブレベルに
応答してカウントアップし第２の制御信号のアクティブ
レベルに応答してカウントダウンする第１のカウンタで
構成され、第２の記憶手段が、前記積分出力の第３の基
準電位越えによるアクティブレベルに応答してカウント
アップし第３の制御信号のアクティブレベルに応答して
カウントダウンする第２のカウンタで構成された請求項
５記載の積分器。7. The first storage means counts up in response to the active level of the first control signal due to exceeding the second reference potential of the integrated output, and counts down in response to the active level of the second control signal. The second storage means counts up in response to the active level of the integrated output due to exceeding the third reference potential, and counts down in response to the active level of the third control signal. The integrator according to claim 5, which is constituted by a second counter.
端に積分出力を受け第２の入力端に第２の基準電位を受
け出力端から前記積分出力が前記第２の基準電位を越え
るとアクティブレベルとなる制御信号を出力する第２の
演算増幅器と、第１の入力端に第３の基準電位を受け第
２の入力端に前記積分出力を受け出力端から前記積分出
力が前記第３の基準電位を越えるとアクティブレベルと
なる制御信号を出力する第３の演算増幅器と、前記第２
及び第３の演算増幅器の出力信号の論理和を第１の制御
信号として出力する論理ゲートとを含んで構成され、第
２のスイッチ制御回路が、第１の入力端に第１の基準電
位を受け第２の入力端に前記積分出力を受け出力端から
第２の制御信号と対応する信号を出力する第４の演算増
幅器を含んで構成され、第３のスイッチ制御回路が、入
力端に前記第４の演算増幅器の出力信号を受けてレベル
反転し出力端から第３の制御信号を対応する信号を出力
するインバータを含んで構成された請求項５記載の積分
器。8. A first switch control circuit receives an integrated output at a first input terminal, receives a second reference potential at a second input terminal, and receives the second reference potential from an output terminal, and the integrated output receives the second reference potential. A second operational amplifier that outputs a control signal that becomes an active level when it exceeds, and a third reference potential at a first input end that receives the integrated output at a second input end A third operational amplifier that outputs a control signal that becomes an active level when the voltage exceeds a third reference potential;
And a logic gate that outputs the logical sum of the output signals of the third operational amplifiers as the first control signal, and the second switch control circuit supplies the first reference potential to the first input terminal. A receiving second input terminal is configured to include a fourth operational amplifier which receives the integrated output from the output terminal and outputs a signal corresponding to the second control signal, and a third switch control circuit is provided at the input terminal. 6. The integrator according to claim 5, comprising an inverter which receives the output signal of the fourth operational amplifier, inverts the level of the output signal, and outputs a signal corresponding to the third control signal from the output end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27083293A JP2550889B2 (en) | 1993-07-27 | 1993-10-28 | Integrator |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5-184288 | 1993-07-27 | ||
| JP18428893 | 1993-07-27 | ||
| JP27083293A JP2550889B2 (en) | 1993-07-27 | 1993-10-28 | Integrator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0795081A true JPH0795081A (en) | 1995-04-07 |
| JP2550889B2 JP2550889B2 (en) | 1996-11-06 |
Family
ID=26502415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27083293A Expired - Fee Related JP2550889B2 (en) | 1993-07-27 | 1993-10-28 | Integrator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2550889B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4842377B2 (en) * | 2006-06-30 | 2011-12-21 | サムスン エレクトロニクス カンパニー リミテッド | Apparatus and method for converting an analog signal into a digital signal |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7525472B2 (en) | 2006-12-27 | 2009-04-28 | Semiconductor Energy Laboratory Co., Ltd. | Integration type and converter and device including same |
-
1993
- 1993-10-28 JP JP27083293A patent/JP2550889B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4842377B2 (en) * | 2006-06-30 | 2011-12-21 | サムスン エレクトロニクス カンパニー リミテッド | Apparatus and method for converting an analog signal into a digital signal |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2550889B2 (en) | 1996-11-06 |
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