JPH0786233A - Method and device for manufacturing semiconductor device - Google Patents
Method and device for manufacturing semiconductor deviceInfo
- Publication number
- JPH0786233A JPH0786233A JP25223293A JP25223293A JPH0786233A JP H0786233 A JPH0786233 A JP H0786233A JP 25223293 A JP25223293 A JP 25223293A JP 25223293 A JP25223293 A JP 25223293A JP H0786233 A JPH0786233 A JP H0786233A
- Authority
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- Japan
- Prior art keywords
- etching
- temperature
- platinum film
- semiconductor device
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
- ing And Chemical Polishing (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法お
よびその製造装置に関し、特に白金シリサイドを用いる
半導体装置の性能向上に有力な効果を発揮する製造方法
およびその製造装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a manufacturing apparatus therefor, and more particularly to a manufacturing method and a manufacturing apparatus therefor for exerting a powerful effect in improving the performance of a semiconductor device using platinum silicide.
【０００２】[0002]
【従来の技術】一般に半導体装置の配線材料としてはＡ
ｌやＡｌ合金が用いられるが、これを半導体そのもの
（シリコン、ポリシリコン等）と直接接触させる構造を
とると、製造工程中の温度の上昇でＡｌがＳｉ中に侵入
し、Ｐｎ接合を破壊する現象（アロイスパイク）が起き
やすい。これを防ぐにはＡｌとＳｉの間に白金シリサイ
ド（Ｐｔ−Ｓｉ）層を形成するのが有効で、広く用いら
れている。Ｐｔ−Ｓｉ層を形成するには全面にＰｔ膜を
被着し、熱処理によりシリサイド化し、さらにシリサイ
ド化していない部分のＰｔをエッチング除去するのが一
般的である。但し、Ｐｔ膜は化学的に非常に安定なた
め、エッチングには高温の王水（塩酸と硝酸の混合液）
を使う以外に有力な方法がない。通常ＨＣｌ：ＨＮ
Ｏ３：Ｈ２Ｏ２＝１：３：４程度の混合液を９０〜９４
℃に保ち１〜２分間浸漬することにより除去できる。ま
た、エッチングについて、特開昭６１−６１４２１号に
は、所望の断面形状に応じてエッチング速度の異方度の
時間変化パターンを求め、被エッチング層の断面形状を
所望の形状に近いずけることが、特開昭６３−２７４１
４７号には、ドライエッチングに関し、冷却用エッチン
グガスをエッチングのステップに合わせ制御し、エッチ
ング残りを除去することが提案されている。2. Description of the Related Art Generally, A is used as a wiring material for semiconductor devices.
Although Al and Al alloys are used, if a structure is adopted in which this is brought into direct contact with the semiconductor itself (silicon, polysilicon, etc.), Al penetrates into Si due to the temperature rise during the manufacturing process and destroys the Pn junction. Phenomena (alloy spikes) are likely to occur. To prevent this, it is effective to form a platinum silicide (Pt-Si) layer between Al and Si, and it is widely used. In order to form a Pt-Si layer, it is general that a Pt film is deposited on the entire surface, silicidation is performed by heat treatment, and Pt in the unsilicided portion is removed by etching. However, since the Pt film is chemically very stable, high-temperature aqua regia (mixed solution of hydrochloric acid and nitric acid) is used for etching.
There is no effective method other than using. Usually HCl: HN
O 3: H 2 O 2 = 1: 3: 90~94 a mixture of about 4
It can be removed by keeping the temperature at ℃ and immersing for 1-2 minutes. Regarding etching, in JP-A-61-61421, a time change pattern of anisotropy of etching rate is obtained according to a desired cross-sectional shape, and the cross-sectional shape of the layer to be etched is approximated to the desired shape. However, JP-A-63-2741
With respect to dry etching, No. 47 proposes to control the etching gas for cooling in accordance with the etching step to remove the etching residue.
【０００３】[0003]
【発明が解決しようとする課題】しかし近年半導体装置
の微細化、高速化が進むにつれて次の様な不都合が生じ
るようになった。 （１）Ｐｔ膜のエッチングが過剰になると、本来除去さ
れてはいけないＰｔ−Ｓｉ層が未反応のＰｔとの境界部
分付近でエッチングされてしまい、ＡｌとＳｉが直接接
触する部分が極部的に生じ、アロイスパイクによりＰｎ
接合を破壊する。 （２）上記の不都合を防ぐべく、エッチングを短時間で
抑えようとすると、間隔の微細なところで未反応のＰｔ
が除去されきらずに短絡又はリークが生じる。However, in recent years, the following inconveniences have arisen as semiconductor devices have become finer and faster. (1) If the Pt film is excessively etched, the Pt-Si layer, which should not be removed originally, is etched in the vicinity of the boundary with unreacted Pt, and the portion where Al and Si are in direct contact is an extreme part. And Pn due to alloy spike
Break the joint. (2) If etching is to be suppressed in a short time in order to prevent the above-mentioned inconvenience, unreacted Pt will be formed at a fine interval.
Is not completely removed, causing a short circuit or leakage.
【０００４】これらの不都合は一般の金属膜のエッチン
グにも共通して起こる問題ではあるが、白金膜のエッチ
ングの場合、高温の液を必要とすること、温度変化に対
するエッチングレート変化が非常に大きいこと、わずか
であっても白金表面に汚れがあるとエッチングの開始が
遅れてエッチング残りが起きやすいこと、などの特殊性
があり実用上大きな問題があった。特に常温の被エッチ
ング物を高温の薬液槽に浸漬する時に液温が低下し、従
ってエッチングレートが連続的に変動してしまう影響が
大きい。また、上記の特開昭６１−６１４２１号、特開
昭６３−２７４１４７号は、白金膜のウエットエッチン
グに関するものではなく、そして白金膜のエッチングの
場合における、高温の液を必要とすること、温度変化に
対するエッチングレート変化が非常に大きいこと、わず
かであっても白金表面に汚れがあるとエッチングの開始
が遅れてエッチング残りが起きやすいことなどの特殊性
についての問題解決するものではない。Although these disadvantages are common problems in general metal film etching, in the case of platinum film etching, a high temperature liquid is required, and the etching rate changes greatly with temperature changes. However, there is a serious problem in practical use due to its peculiarities such as the start of etching being delayed and the etching residue is likely to occur if the platinum surface is slightly contaminated. In particular, when an object to be etched at room temperature is immersed in a high temperature chemical bath, the temperature of the solution is lowered, and therefore, the etching rate has a large influence on continuous fluctuation. Further, the above-mentioned JP-A-61-61421 and JP-A-63-274147 do not relate to wet etching of a platinum film, and in the case of etching a platinum film, a high temperature liquid is required, This does not solve the problem of peculiarities such as a very large change in the etching rate with respect to the change, and even a slight amount of contamination on the platinum surface delays the start of etching and easily causes an etching residue.
【０００５】[0005]
【課題を解決するための手段】本発明は、半導体基板上
に白金膜を被着する工程と、熱処理により白金膜を選択
的にシリサイド化する工程と、未反応の白金膜を硝酸と
塩酸を含む混液でエッチングする際、エッチング液温の
エッチング時間積分値が一定となるようにエッチング時
間を制御する半導体装置の製造方法てあり、また、薬液
槽に温度センサー、ヒーター制御機構を備え、かつ半導
体基板の搬送機構の動作により作動するタイマーおよび
温度センサーに接続されている積分器を備え、エッチン
グ液温のエッチング時間に対する積分値が一定値となる
ようにエッチング時間を制御することを特徴とする半導
体装置の製造装置である。According to the present invention, a step of depositing a platinum film on a semiconductor substrate, a step of selectively siliciding the platinum film by heat treatment, and a step of unreacted platinum film with nitric acid and hydrochloric acid are carried out. There is a method for manufacturing a semiconductor device in which the etching time is controlled so that the etching time integrated value of the etching liquid temperature becomes constant when etching with a mixed liquid containing the same, and the chemical bath is equipped with a temperature sensor and a heater control mechanism, and A semiconductor including an integrator connected to a timer and a temperature sensor that operate according to the operation of the substrate transport mechanism, and controlling the etching time so that the integrated value of the etching solution temperature with respect to the etching time becomes a constant value. It is a device manufacturing device.
【０００６】[0006]
【作用】本発明においては、高温のウェットエッチング
に際して、被エッチング物を投入すること等による液温
変化、即ちエッチレート変化を補正すべくエッチング時
間を制御するので、エッチング物の量や装置の特性に左
右されない一定のエッチングができるものである。In the present invention, during the high temperature wet etching, the etching time is controlled so as to correct the change in the liquid temperature, that is, the change in the etching rate due to the introduction of the object to be etched. It is possible to perform constant etching that is not affected by
【０００７】[0007]
【実施例】本発明の実施例について図面を参照して説明
する。図１は本発明の一実施例の半導体装置の断面図、
図２は本発明を実現するために用いるエッチング装置の
ブロック図である。 ［実施例１］図１において半導体基板１上にシリコン酸
化膜２が被着され、その開口部２１を覆うように厚さ２
００ｎｍの電極引出用ポリシリコン３が配されている
（図１（ａ））。次に該基板表面全面に白金膜４をマグ
ネトロンスパッタ法により３０ｎｍの厚さに被着する
（図１（ｂ））。次に基板全体を５５０℃Ｎ２雰囲気中
で熱処理し、ポリシリコン上の白金とポリシリコンを反
応させて白金シリサイド化する（図１（ｃ））。然る後
に図２に示すエッチング装置を用いてＨＣｌ：ＨＮ
Ｏ３：Ｈ２Ｏ＝１：３：４の薬液により未反応の白金膜
を除去し、自己整合的にポリシリコン上にのみ白金シリ
サイド層を残す（図１（ｄ））。さらに通常の方法でＡ
ｌ配線を形成すれば半導体装置が完成する。Embodiments of the present invention will be described with reference to the drawings. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention,
FIG. 2 is a block diagram of an etching apparatus used to realize the present invention. [Embodiment 1] In FIG. 1, a silicon oxide film 2 is deposited on a semiconductor substrate 1 and has a thickness of 2 so as to cover an opening 21 thereof.
Electrode leading polysilicon 3 having a thickness of 00 nm is arranged (FIG. 1A). Next, a platinum film 4 is deposited to a thickness of 30 nm on the entire surface of the substrate by a magnetron sputtering method (FIG. 1 (b)). Next, the entire substrate is heat-treated in a N 2 atmosphere at 550 ° C. to react platinum on the polysilicon with the polysilicon to form platinum silicide (FIG. 1C). Then, using the etching apparatus shown in FIG. 2, HCl: HN
The unreacted platinum film is removed with a chemical solution of O 3 : H 2 O = 1: 3: 4, and the platinum silicide layer is left only on the polysilicon in a self-aligned manner (FIG. 1D). In addition, A
The semiconductor device is completed by forming the l wiring.
【０００８】ここで図２のエッチング装置によるエッチ
ングを詳しく説明する。エッチング装置は、薬液槽６に
温度センサー７１、ヒーター制御機構９を備え、かつ半
導体基板１０の搬送機構１３の動作により作動するタイ
マー１４および温度センサー７２に接続されている積分
器１５を備え、エッチング液温のエッチング時間に対す
る積分値が一定値となるようにエッチング時間を制御す
る半導体装置の製造装置である。詳しくは、、ヒーター
８と温度センサー７１、７２を有する薬液槽６内に王水
が入れられており、ヒーター制御機構９により９２℃に
保たれている。半導体基板１０がキャリヤ１１に入れら
れ、ハンガー１２を経由して搬送機構１３により保持さ
れている。まず搬送機構が動作し半導体基板１０が王水
中に入れられる。この時タイマー１４がスタートする。
被エッチング物の投入により液温は急激に低下しエッチ
ングレートが低下する。この液温変化を温度センサー７
２に接続されている積分器１５に送られる。Etching by the etching apparatus shown in FIG. 2 will be described in detail. The etching apparatus is provided with a temperature sensor 71, a heater control mechanism 9 in the chemical bath 6, a timer 14 operated by the operation of the transfer mechanism 13 for the semiconductor substrate 10, and an integrator 15 connected to the temperature sensor 72. The semiconductor device manufacturing apparatus controls the etching time such that the integrated value of the liquid temperature with respect to the etching time becomes a constant value. More specifically, aqua regia is placed in the chemical liquid tank 6 having the heater 8 and the temperature sensors 71 and 72, and is maintained at 92 ° C. by the heater control mechanism 9. The semiconductor substrate 10 is put in the carrier 11 and held by the transfer mechanism 13 via the hanger 12. First, the transport mechanism operates to put the semiconductor substrate 10 into aqua regia. At this time, the timer 14 starts.
When the material to be etched is added, the liquid temperature sharply drops and the etching rate drops. This temperature change of the liquid sensor 7
2 is sent to the integrator 15 connected to 2.
【０００９】この時液温変化を図３に示す。液温はＴ１
からＴ２に低下するがヒーター制御機構９が働らくので
徐々に元のＴ１に戻ってゆく。エッチング液温の変化に
応じてエッチングレートも変化するので、温度の低下量
や回復の推移によってエッチングされる量は実質的に大
きく変化する。本発明においては、エッチング液温Ｔの
時間積分値［数１］が一定値となるｔ２に達した時、搬
送機構１３を動作させてエッチングを終了させる（Ｔ０
は定数）。このようにすることで、温度の低下量や、回
復時定数が変化しても一定のエッチング結果を得ること
ができる。即ち半導体基板の枚数、薬液槽の容量、ヒー
ター制御機構の時定数が変化しても一定のエッチング結
果を得ることができる。The change in liquid temperature at this time is shown in FIG. Liquid temperature is T 1
Although decreases in T 2 Yuku back gradually original T 1 so Raku heater control mechanism 9 is working from. Since the etching rate also changes according to the change in the etching solution temperature, the amount of etching changes substantially due to the decrease in temperature and the transition of recovery. In the present invention, when the time integrated value [Equation 1] of the etching solution temperature T reaches t 2 at which it is a constant value, the transport mechanism 13 is operated to end the etching (T 0
Is a constant). By doing so, a constant etching result can be obtained even if the amount of temperature decrease or the recovery time constant changes. That is, a constant etching result can be obtained even if the number of semiconductor substrates, the capacity of the chemical bath, and the time constant of the heater control mechanism change.
【数１】 [Equation 1]
【００１０】［実施例２］図４に、本発明の第２の実施
例に用いるエッチング層内のブロック図を示す。半導体
装置の断面フロー、搬送制御の方式は上記の実施例１と
同じであるが、温度制御機構（ヒーター制御機構）が異
る。本方式によると、フィルタ１７、ポンプ１６を備え
たフィルタリング循環により薬液中のゴミを低減でき、
より高品質のエッチングができる。本方式をとると一般
に液温の回復時間は長くなるが、本発明では温度の時間
積分値を一定にするっようにエッチングするので、一定
のエッチング結果を得ることができる。[Embodiment 2] FIG. 4 shows a block diagram of an etching layer used in the second embodiment of the present invention. The cross-sectional flow of the semiconductor device and the transport control method are the same as those in the first embodiment, but the temperature control mechanism (heater control mechanism) is different. According to this method, dust in the chemical liquid can be reduced by the filtering circulation provided with the filter 17 and the pump 16.
Higher quality etching is possible. When this method is adopted, the recovery time of the liquid temperature is generally long, but in the present invention, since etching is performed so that the time integral value of temperature is constant, a constant etching result can be obtained.
【００１１】[0011]
【発明の効果】以上説明したように、本発明によれば、
高温のウェットエッチングに際して、被エッチング物を
投入すること等による液温変化、即ちエッチレート変化
を補正すべくエッチング時間を制御するので、エッチン
グ物の量や装置の特性に左右されない一定のエッチング
ができる。これにより、白金膜のエッチングにおける高
温の液を必要とすること、温度変化に対するエッチング
レート変化が非常に大きいこと、わずかであっても白金
表面に汚れがあるとエッチングの開始が遅れてエッチン
グ残りが起きやすいこと、などの特殊性に対応でき、以
って特性の安定な半導体装置を得ることができる。As described above, according to the present invention,
During high-temperature wet etching, the etching time is controlled to compensate for changes in the liquid temperature, such as changes in the etch rate, caused by the introduction of the object to be etched, etc., so that constant etching can be performed without being affected by the amount of the object to be etched and the characteristics of the apparatus. . As a result, a high temperature liquid is required for etching the platinum film, the change in the etching rate with respect to the temperature change is very large, and even if the platinum surface is slightly contaminated, the start of etching is delayed and the etching residue remains. It is possible to deal with peculiarities such as easiness of occurrence and to obtain a semiconductor device with stable characteristics.
【図１】本発明の一実施例の半導体装置断面図。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施例を実現するために用いるエッ
チング装置のブロック図。FIG. 2 is a block diagram of an etching apparatus used to realize an embodiment of the present invention.
【図３】液温の変化を示す図。FIG. 3 is a diagram showing changes in liquid temperature.
【図４】本発明の第２の実施例に用いるエッチング装置
のブロック図。FIG. 4 is a block diagram of an etching apparatus used in the second embodiment of the present invention.
１．半導体基板 ２．シリコン酸化膜（ＳＯ２） ２１．シリコン酸化膜開孔部 ３．ポリシリコン ４．白金 ４１．白金シリサイド ６．薬液槽 ７１、７２．温度センサ ８．ヒーター ９．ヒーター制御機構 １０．半導体基板 １１．キャリヤ １２．ハンガー １３．搬送機構 １４．タイマー １５．積分器 １６．ポンプ １７．フィルタ1. Semiconductor substrate 2. Silicon oxide film (SO 2 ) 21. Silicon oxide film opening 3. Polysilicon 4. Platinum 41. Platinum silicide 6. Chemical solution tank 71, 72. Temperature sensor 8. Heater 9. Heater control mechanism 10. Semiconductor substrate 11. Carrier 12. Hanger 13. Transport mechanism 14. Timer 15. Integrator 16. Pump 17. filter
Claims (3)
と、熱処理により白金膜を選択的にシリサイド化する工
程と、未反応の白金膜を硝酸と塩酸を含む混液でエッチ
ングする工程とを含む半導体装置の製造方法において、
エッチング液温のエッチング時間に対する積分値が一定
値となるようにエッチング時間を制御することを特徴と
する半導体装置の製造方法。1. A step of depositing a platinum film on a semiconductor substrate, a step of selectively siliciding the platinum film by heat treatment, and a step of etching an unreacted platinum film with a mixed solution containing nitric acid and hydrochloric acid. In a method of manufacturing a semiconductor device including:
A method of manufacturing a semiconductor device, wherein the etching time is controlled so that the integrated value of the etching liquid temperature with respect to the etching time becomes a constant value.
構を備え、かつ半導体基板の搬送機構の動作により作動
するタイマーおよび温度センサーに接続されている積分
器を備え、エッチング液温のエッチング時間に対する積
分値が一定値となるようにエッチング時間を制御するこ
とを特徴とする半導体装置の製造装置。2. The chemical solution tank is provided with a temperature sensor and a heater control mechanism, and a timer operated by the operation of the semiconductor substrate transfer mechanism and an integrator connected to the temperature sensor are provided, and the integration of the etching solution temperature with respect to the etching time is performed. An apparatus for manufacturing a semiconductor device, wherein the etching time is controlled so that the value becomes a constant value.
タ、ポンプを備えたフィルタリング循環を設けているこ
とを特徴とする請求項２に記載の半導体装置の製造装
置。3. The apparatus for manufacturing a semiconductor device according to claim 2, wherein the heater control mechanism of the chemical liquid tank is provided with a filtering circulation provided with a filter and a pump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25223293A JPH0786233A (en) | 1993-09-14 | 1993-09-14 | Method and device for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25223293A JPH0786233A (en) | 1993-09-14 | 1993-09-14 | Method and device for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0786233A true JPH0786233A (en) | 1995-03-31 |
Family
ID=17234360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25223293A Pending JPH0786233A (en) | 1993-09-14 | 1993-09-14 | Method and device for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0786233A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007194632A (en) * | 2006-01-18 | 2007-08-02 | Stmicroelectronics (Crolles 2) Sas | Method of selectively removing nonsilicided metal |
| JP2010157684A (en) * | 2008-12-03 | 2010-07-15 | Panasonic Corp | Method of manufacturing semiconductor device |
| WO2019087702A1 (en) * | 2017-10-31 | 2019-05-09 | 株式会社Ｓｃｒｅｅｎホールディングス | Substrate treatment device and substrate treatment method |
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| JPS5797627A (en) * | 1980-12-10 | 1982-06-17 | Sigma Gijutsu Kogyo Kk | Formation of electric wiring |
| JPH0249011A (en) * | 1988-08-11 | 1990-02-19 | Somar Corp | Resist for processing with high energy beam |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5797627A (en) * | 1980-12-10 | 1982-06-17 | Sigma Gijutsu Kogyo Kk | Formation of electric wiring |
| JPH0249011A (en) * | 1988-08-11 | 1990-02-19 | Somar Corp | Resist for processing with high energy beam |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007194632A (en) * | 2006-01-18 | 2007-08-02 | Stmicroelectronics (Crolles 2) Sas | Method of selectively removing nonsilicided metal |
| JP2010157684A (en) * | 2008-12-03 | 2010-07-15 | Panasonic Corp | Method of manufacturing semiconductor device |
| WO2019087702A1 (en) * | 2017-10-31 | 2019-05-09 | 株式会社Ｓｃｒｅｅｎホールディングス | Substrate treatment device and substrate treatment method |
| JP2019083267A (en) * | 2017-10-31 | 2019-05-30 | 株式会社Ｓｃｒｅｅｎホールディングス | Substrate processing apparatus and substrate processing method |
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