JPH0778935A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH0778935A JPH0778935A JP22358593A JP22358593A JPH0778935A JP H0778935 A JPH0778935 A JP H0778935A JP 22358593 A JP22358593 A JP 22358593A JP 22358593 A JP22358593 A JP 22358593A JP H0778935 A JPH0778935 A JP H0778935A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- substrate
- integrated circuit
- hybrid integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は混成集積回路装置に関す
る。This invention relates to hybrid integrated circuit devices.
【０００２】[0002]
【従来の技術】従来、混成集積回路装置は図６に示すよ
うに構成されている。セラミック基板等を積層して構成
される印刷配線積層基板（以下、単に基板という）５０
は３層構造となっている。１層目には外部との接続のた
めの複数の端子５１がロウ材５２により接着されてい
る。２層目は、半導体素子５３を載置するため収容部５
４が設けられており、そこに半導体素子５３が接着剤５
５により接着されている。基板５０と半導体素子５３と
はワイヤ５６により電気的に接続されている。３層目の
表面には半導体素子５３を封止するための、金属等で形
成されたキャップ５７が設けられている。該キャップ５
７は、治具を用いて位置決めされ、低融点ガラス等のシ
ール材５８が基板５０との接合部全周に塗布されてお
り、所定の位置に載置されている。そして、３層目の表
面のキャップ５７の外周部分には回路配線層５９が載置
され、その上に表面実装部品６０が半田６１を介して実
装されている。なお、ワイヤ５６と表面実装部品６０及
び端子５１とは、基板５０内部に形成されたビアホール
６２及び内部配線６３によって接続されている。2. Description of the Related Art Conventionally, a hybrid integrated circuit device is constructed as shown in FIG. Printed wiring laminated substrate (hereinafter simply referred to as substrate) 50 configured by laminating ceramic substrates and the like
Has a three-layer structure. On the first layer, a plurality of terminals 51 for connection to the outside are adhered by a brazing material 52. The second layer is the accommodating portion 5 for mounting the semiconductor element 53.
4 is provided, and the semiconductor element 53 has the adhesive 5 on it.
Bonded by 5. The substrate 50 and the semiconductor element 53 are electrically connected by the wire 56. On the surface of the third layer, a cap 57 made of metal or the like is provided for sealing the semiconductor element 53. The cap 5
7 is positioned by using a jig, a sealing material 58 such as low melting point glass is applied to the entire circumference of the joint with the substrate 50, and is placed at a predetermined position. The circuit wiring layer 59 is placed on the outer peripheral portion of the cap 57 on the surface of the third layer, and the surface mount component 60 is mounted thereon by solder 61. The wire 56, the surface mount component 60, and the terminal 51 are connected by a via hole 62 and an internal wiring 63 formed inside the substrate 50.
【０００３】[0003]
【発明が解決しようとする課題】ところが、キャップ５
７が基板５０表面上に載置されるため、該キャップ５７
と同一平面上に載置される回路配線層５９及び表面実装
部品６０は基板５０表面上のキャップシール部分の外側
のみにしか設けることができない。そして、その実装領
域を確保するために、基板５０の面積が大きくなり、実
装効率を上げることができないという問題が生じてい
る。However, the cap 5
7 is placed on the surface of the substrate 50, the cap 57
The circuit wiring layer 59 and the surface mount component 60 placed on the same plane as the above can be provided only outside the cap seal portion on the surface of the substrate 50. Then, in order to secure the mounting area, the area of the substrate 50 becomes large, which causes a problem that the mounting efficiency cannot be improved.
【０００４】そこで、（特開平５−４１５７０号）には
実装効率を上げるため、キャップの裏面に電子部品を設
けることが開示されている。しかし、この電子部品は封
止された内部に設けられているため、パッケージされた
後の信頼性試験により発見された不具合部品のリペアが
不可能であり、製品として出荷することができなくな
り、歩留りを上げることができない。Therefore, Japanese Patent Application Laid-Open No. 5-41570 discloses that electronic parts are provided on the back surface of the cap in order to improve the mounting efficiency. However, since this electronic component is installed inside the sealed interior, it is impossible to repair defective components found by the reliability test after packaging, and it becomes impossible to ship as a product, and the yield I can't raise.
【０００５】本発明は上記問題点を解決するためになさ
れたものであって、その目的は実装効率を上げ、かつ、
生産効率を上げることができ、また、信頼性を高めるこ
とができる混成集積回路装置を提供することにある。The present invention has been made to solve the above problems, and its purpose is to improve mounting efficiency and
It is an object of the present invention to provide a hybrid integrated circuit device capable of increasing production efficiency and reliability.
【０００６】[0006]
【課題を解決するための手段】本発明は上記問題点を解
決するため、請求項１記載の発明は、印刷配線積層基板
に凹設した収容部に半導体素子を搭載し、その収容部開
口をキャップにて閉塞して半導体素子を封止した混成集
積回路装置において、キャップ表面に回路配線層を形成
したことをその要旨とする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention according to claim 1 mounts a semiconductor element in an accommodating portion recessed in a printed wiring laminated board and opens the accommodating portion opening. In a hybrid integrated circuit device in which a semiconductor element is sealed by closing with a cap, the gist is that a circuit wiring layer is formed on the surface of the cap.
【０００７】請求項２記載の発明は、請求項１の混成集
積回路装置において、キャップ表面に形成された回路配
線層上に表面実装部品を設けたことをその要旨とする。
請求項３記載の発明は、請求項２の混成集積回路装置に
おいて、印刷配線積層基板はその表面に回路配線層が形
成され、キャップはその表面が印刷配線積層基板の表面
と面一となるように印刷配線積層基板に取着され、キャ
ップの回路配線層と印刷配線積層基板の表面に形成した
回路配線層とを表面実装部品を介して電気的に接続した
ことをその要旨とする。A second aspect of the present invention is characterized in that, in the hybrid integrated circuit device according to the first aspect, the surface mount component is provided on the circuit wiring layer formed on the cap surface.
According to a third aspect of the present invention, in the hybrid integrated circuit device according to the second aspect, the printed wiring laminated board has a circuit wiring layer formed on a surface thereof, and the cap has a surface flush with a surface of the printed wiring laminated board. The gist is that the circuit wiring layer of the cap and the circuit wiring layer formed on the surface of the printed wiring laminated board are attached to the printed wiring laminated board and electrically connected to each other through the surface mount component.
【０００８】請求項４記載の発明は、請求項１又は請求
項２又は請求項３の混成集積回路装置において、キャッ
プは印刷配線積層基板の熱膨張係数が同程度の材質であ
ることをその要旨とする。According to a fourth aspect of the present invention, in the hybrid integrated circuit device according to the first aspect, the second aspect, or the third aspect, the cap is made of a material having a similar coefficient of thermal expansion to the printed wiring board. And
【０００９】[0009]
【作用】請求項１及び請求項２記載の発明によれば、キ
ャップ表面に回路配線層及び表面実装部品を設けるの
で、基板表面の実装領域を狭くすることができ、基板を
小型化することができる。また、キャップ表面上の表面
実装部品についてはリペアが可能となる。According to the first and second aspects of the present invention, since the circuit wiring layer and the surface mounting component are provided on the cap surface, the mounting area on the substrate surface can be narrowed and the substrate can be miniaturized. it can. Further, the surface mount component on the cap surface can be repaired.
【００１０】請求項３記載の発明によれば、印刷配線積
層基板の中央部にキャップ収容部を設け、このキャップ
収容部にキャップを印刷配線積層基板表面と面一となる
ように取着することにより、キャップ表面と印刷配線積
層基板表面とにより形成される平面に回路配線層を単一
工程で形成することができ、該回路配線層上に表面実装
部品を設けることができる。According to the third aspect of the present invention, a cap accommodating portion is provided at the center of the printed wiring laminated board, and the cap is attached to the cap accommodating portion so as to be flush with the surface of the printed wiring laminated board. Thus, the circuit wiring layer can be formed in a single step on the plane formed by the cap surface and the printed wiring laminated substrate surface, and the surface mount component can be provided on the circuit wiring layer.
【００１１】請求項４記載の発明によれば、キャップと
基板との熱膨張係数を同程度とすることにより、基板と
キャップ、キャップ及び基板と表面実装部品の接合部分
にクラックが入ることが避けられる。According to the fourth aspect of the present invention, by making the thermal expansion coefficients of the cap and the substrate about the same, it is possible to prevent cracks from being generated at the joint portion between the substrate and the cap, the cap, and the substrate and the surface mount component. To be
【００１２】[0012]
【実施例】以下、本発明の混成集積回路装置を具体化し
た一実施例を図１に従って説明する。印刷配線積層基板
（以下、単に基板という）１０は、セラミック基板を積
層して形成され、各層には内部配線１１と各層を電気的
に接続するビアホール１２が設けられている。基板１０
中央には階段状の収容部１３が形成され、収容部１３に
は内部配線１１と接続する配線１４が設けられている。
基板１０表面には回路配線層１５が形成されている。前
記収容部１３には半導体素子１６が半田１７を介して固
着されている。該半導体素子１６はワイヤ１８にて収容
部１３の配線１４と電気的に接続されている。基板１０
裏面にはロウ材１９を介して端子２０が取着され、内部
配線１１及びビアホール１２を介して基板１０表面に形
成された回路配線層１５や半導体素子１６と電気的に接
続されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the hybrid integrated circuit device of the present invention will be described below with reference to FIG. A printed wiring laminated board (hereinafter, simply referred to as a substrate) 10 is formed by laminating ceramic substrates, and each layer is provided with an internal wiring 11 and a via hole 12 that electrically connects each layer. Board 10
A staircase-shaped accommodating portion 13 is formed in the center, and the accommodating portion 13 is provided with a wiring 14 connected to the internal wiring 11.
A circuit wiring layer 15 is formed on the surface of the substrate 10. A semiconductor element 16 is fixed to the housing portion 13 via a solder 17. The semiconductor element 16 is electrically connected to the wiring 14 of the housing portion 13 by a wire 18. Board 10
A terminal 20 is attached to the back surface via a brazing material 19, and is electrically connected to a circuit wiring layer 15 and a semiconductor element 16 formed on the front surface of the substrate 10 via an internal wiring 11 and a via hole 12.
【００１３】セラミックで形成されたキャップ３０は、
シール材３１を介して、収容部１３開口を閉塞するよう
に固着され、半導体素子１６を封止している。該キャッ
プ３０は基板１０への落とし込み構造となっていて、キ
ャップ３０の表面と基板１０の表面とが面一となってい
る。なお、キャップ３０が基板１０と面一となるよう
に、予め基板１０、シール材３１、キャップ３０の厚み
が設計されている。キャップ３０表面には回路配線層３
２が形成され、その上に表面実装部品３３ａ，３３ｂが
半田３４によって実装されている。基板１０上の回路配
線層１５とキャップ３０表面の回路配線層３２とは両者
を跨いで実装されている表面実装部品３３ａを介して電
気的に接続されている。The cap 30 made of ceramic is
The semiconductor element 16 is sealed by being fixed so as to close the opening of the housing portion 13 via the sealing material 31. The cap 30 has a structure of being dropped onto the substrate 10, and the surface of the cap 30 and the surface of the substrate 10 are flush with each other. The thicknesses of the substrate 10, the sealing material 31, and the cap 30 are designed in advance so that the cap 30 is flush with the substrate 10. The circuit wiring layer 3 is formed on the surface of the cap 30.
2 is formed, and surface mount components 33a and 33b are mounted thereon by solder 34. The circuit wiring layer 15 on the substrate 10 and the circuit wiring layer 32 on the surface of the cap 30 are electrically connected to each other via the surface-mounted component 33a mounted across the both.
【００１４】キャップ３０表面に表面実装部品３３ａ，
３３ｂを設けるようにしたことで、基板１０表面に表面
実装部品３３ａを実装する領域を狭くすることができ
る。その結果、基板１０を小型化することができ、実装
効率を上げることができる。On the surface of the cap 30, surface mount parts 33a,
By providing 33b, the area for mounting the surface mount component 33a on the surface of the substrate 10 can be narrowed. As a result, the substrate 10 can be downsized and the mounting efficiency can be improved.
【００１５】キャップ３０が基板１０表面と面一となる
ように固着されているので、基板１０とキャップ３０と
により形成される平面があたかも一枚の基板であるかの
ように扱うことができる。従って、基板１０表面とキャ
ップ３０表面の回路配線層１５，３２を単一工程により
形成することができる。さらに回路配線層１５，３２は
表面実装部品３３ａにより電気的に接続されているの
で、基板１０とキャップ３０とにより形成される平面を
有効的に利用することができる。Since the cap 30 is fixed so as to be flush with the surface of the substrate 10, the flat surface formed by the substrate 10 and the cap 30 can be treated as if it were a single substrate. Therefore, the circuit wiring layers 15 and 32 on the surface of the substrate 10 and the surface of the cap 30 can be formed in a single process. Further, since the circuit wiring layers 15 and 32 are electrically connected by the surface mount component 33a, the plane formed by the substrate 10 and the cap 30 can be effectively used.
【００１６】さらに、基板１０表面及びキャップ３０表
面に実装された表面実装部品３３ａ，３３ｂは、混成集
積回路装置作製後も修理、交換が可能であるので、信頼
性試験の結果、不具合が生じたときにはリペアをして、
製品として出荷することができ、歩留りが向上する。し
かも、キャップ３０を落とし込み構造としたことで、治
具を用いなくてもキャップ３０の搭載位置精度を高める
ことができ、その結果生産効率も良くなる。Further, since the surface mount components 33a and 33b mounted on the surface of the substrate 10 and the surface of the cap 30 can be repaired and replaced even after the hybrid integrated circuit device is manufactured, a failure occurs as a result of the reliability test. Sometimes repair
It can be shipped as a product and the yield is improved. Moreover, since the cap 30 has a structure in which it is dropped, the mounting position accuracy of the cap 30 can be improved without using a jig, and as a result, the production efficiency is improved.
【００１７】また、基板１０表面とキャップ３０表面の
両方の回路配線層１５，３２に跨いで実装される表面実
装部品３３ａは、部品下にキャップ３０と基板１０との
間に生じる隙間が存在する。従って、半田３４を付けた
ときのリフロー後のフラックス洗浄工程において、洗浄
液が入り込み易く、表面実装部品３３ａに付着した半田
３４等の洗浄性が向上する。Further, in the surface mount component 33a mounted over the circuit wiring layers 15 and 32 on both the surface of the substrate 10 and the surface of the cap 30, there is a gap formed between the cap 30 and the substrate 10 under the component. . Therefore, in the flux cleaning process after the reflow when the solder 34 is attached, the cleaning liquid easily enters and the cleaning property of the solder 34 and the like attached to the surface mount component 33a is improved.
【００１８】さらにまた、基板１０とキャップ３０は同
じセラミックにより形成されているので、熱膨張係数は
当然同じである。従って、ヒートサイクルに対して、基
板１０とキャップ３０、キャップ３０及び基板１０と表
面実装部品３３ａの接合部分のそれぞれシール材３１及
び半田３４にクラックが入ることが避けられる。すなわ
ち、気密性、電気的接続が損なわれることがないので、
信頼性を高めることができる。Furthermore, since the substrate 10 and the cap 30 are made of the same ceramic, the coefficients of thermal expansion are naturally the same. Therefore, it is possible to prevent cracks from being generated in the seal material 31 and the solder 34 at the joint portion between the substrate 10 and the cap 30, the cap 30, and the substrate 10 and the surface mount component 33a due to the heat cycle. That is, airtightness and electrical connection are not impaired,
The reliability can be increased.
【００１９】なお、本発明は前記実施例に限定されるも
のでなく、本発明の趣旨を逸脱しない範囲において、例
えば次のように変更してもよい。 （１）上記実施例では、基板１０表面とキャップ３０表
面を面一とするために、予め基板１０、シール材３１、
キャップ３０の厚みを設計しておくとしたが、図２に示
すようなキャップ３０を形成してもよい。すなわち、キ
ャップ３０の下面に突部３５を、基板１０との接合部に
設ける。この突部３５を含んだキャップ３０の厚みが基
板１０の階段高さと同じになるように設計する。なお、
突部３５は基板１０側に設けてもよく、キャップ３０及
び基板１０双方に設けてあってもよい。また、突部３５
は接合部全周に設けてあってもよく、四隅に独立で設け
てあっても同様な効果が得られる。また、突部３５の材
質はキャップ３０と同一である必要はなく、キャップ３
０を取着して上から圧力をかけたとき、及び高温下にお
いて変形しないものであれば、別材質であってもよい。
この突部３５を設けることによって、基板１０表面とキ
ャップ３０表面とを面一とする工程が容易になる。The present invention is not limited to the above embodiment, and may be modified as follows, for example, without departing from the gist of the present invention. (1) In the above embodiment, in order to make the surface of the substrate 10 flush with the surface of the cap 30, the substrate 10, the sealing material 31,
Although the thickness of the cap 30 is designed in advance, the cap 30 as shown in FIG. 2 may be formed. That is, the protrusion 35 is provided on the lower surface of the cap 30 at the joint with the substrate 10. The thickness of the cap 30 including the protrusion 35 is designed to be the same as the step height of the substrate 10. In addition,
The protrusion 35 may be provided on the substrate 10 side, or may be provided on both the cap 30 and the substrate 10. Also, the protrusion 35
May be provided on the entire circumference of the joining portion, or the same effect can be obtained even if they are provided at four corners independently. Further, the material of the protrusion 35 need not be the same as that of the cap 30, and the cap 3
Another material may be used as long as it does not deform when 0 is attached and pressure is applied from above and at a high temperature.
Providing this protrusion 35 facilitates the step of making the surface of the substrate 10 flush with the surface of the cap 30.
【００２０】（２）上記実施例では、半導体素子１６の
接着、表面実装部品３３ａ，３３ｂの接合に半田１７，
３４を用いていたが、接合部材として導電性接着剤であ
ってもよく、たとえば、Ａｇエポキシ，Ａｇシリコンが
ある。導電性接着剤は、半田に比べてヒートサイクルに
対して崩壊する等の恐れが少なく、接合部材の信頼性が
高くなる。また、半導体素子１６の接着には、導電性で
ある必要はないので、非導電性の接着剤等を用いてもよ
い。(2) In the above embodiment, the semiconductor element 16 is bonded, the surface mount components 33a and 33b are joined by the solder 17,
Although 34 is used, a conductive adhesive may be used as the joining member, and examples thereof include Ag epoxy and Ag silicon. Compared with solder, the conductive adhesive is less likely to be collapsed by a heat cycle, etc., and the reliability of the joining member is increased. Further, since the semiconductor element 16 does not have to be electrically conductive for adhesion, a non-conductive adhesive or the like may be used.
【００２１】（３）上記実施例では、キャップ３０表面
に実装される表面実装部品として表面実装部品３３ａ，
３３ｂが設けられていたが、表面実装部品３３ｂを設け
ない図３に示すような構成であってもよい。(3) In the above embodiment, the surface mount components 33a, which are mounted on the surface of the cap 30, are used.
Although 33b is provided, the surface mounting component 33b may not be provided as shown in FIG.
【００２２】（４）上記実施例では、基板１０表面とキ
ャップ３０表面とが面一となるようにキャップ３０が取
着され、基板１０の回路配線層１５とキャップ３０の回
路配線層３２との電気的接続を表面実装部品３３ａを介
して行っているが、図４に示すような構成であってもよ
い。本実施例においては基板１０の回路配線層１５とキ
ャップ３０の回路配線層３２との電気的接続には、上記
実施例における表面実装部品３３ａの代わりに、リード
線３６を用いて行う。従って、この場合においては、基
板１０表面とキャップ３０表面とを面一となるようにキ
ャップ３０が取着される必要はない。(4) In the above embodiment, the cap 30 is attached so that the surface of the substrate 10 and the surface of the cap 30 are flush with each other, and the circuit wiring layer 15 of the substrate 10 and the circuit wiring layer 32 of the cap 30 are connected. Although the electrical connection is made through the surface mount component 33a, the configuration shown in FIG. 4 may be used. In this embodiment, the electrical connection between the circuit wiring layer 15 of the substrate 10 and the circuit wiring layer 32 of the cap 30 is performed using the lead wire 36 instead of the surface mount component 33a in the above embodiment. Therefore, in this case, the cap 30 need not be attached so that the surface of the substrate 10 and the surface of the cap 30 are flush with each other.
【００２３】さらに、リード線３６の代わりに図中の破
線で示した外部リード線３７により、端子２０が接続さ
れる外部回路とは別の外部回路と接続する構成としても
よい。以上の実施例においても実装効率を上げることが
できる。Further, instead of the lead wire 36, an external lead wire 37 shown by a broken line in the drawing may be connected to an external circuit different from the external circuit to which the terminal 20 is connected. The mounting efficiency can be improved also in the above embodiments.
【００２４】また、図５に示すように、図４において表
面実装部品３３ｂを設けない構成であってもよい。この
実施例においても、複雑な回路構成が可能となる。 （５）上記実施例では、基板１０とキャップ３０は同じ
材質であるとしたが、全く同一である必要はない。例え
ば、窒化アルミ、アルミナ、ベリリヤ等の組み合わせで
あっても熱膨張係数が同程度であるので、接合部分の信
頼性を高めることができる。Further, as shown in FIG. 5, the surface mount component 33b in FIG. 4 may be omitted. Also in this embodiment, a complicated circuit configuration is possible. (5) Although the substrate 10 and the cap 30 are made of the same material in the above embodiment, they need not be the same. For example, even if a combination of aluminum nitride, alumina, beryllia, etc. is used, the coefficient of thermal expansion is about the same, so the reliability of the bonded portion can be improved.
【００２５】（６）上記実施例では、基板１０及びキャ
ップ３０はセラミックにより形成されていたが、ガラス
エポキシにより形成したものであってもよい。(6) Although the substrate 10 and the cap 30 are made of ceramic in the above embodiment, they may be made of glass epoxy.
【００２６】[0026]
【発明の効果】以上詳述したように本発明によれば、混
成集積回路装置の実装効率を上げ、かつ、生産効率を上
げることができ、また、信頼性を高めることができる優
れた効果がある。As described above in detail, according to the present invention, it is possible to improve the packaging efficiency and production efficiency of the hybrid integrated circuit device, and also to improve the reliability. is there.
【図１】本発明の混成集積回路装置の一実施例を示す断
面図である。FIG. 1 is a sectional view showing an embodiment of a hybrid integrated circuit device of the present invention.
【図２】キャップ表面を基板表面と面一とするキャップ
形状を示す混成集積回路装置の断面図である。FIG. 2 is a cross-sectional view of a hybrid integrated circuit device showing a cap shape in which the cap surface is flush with the substrate surface.
【図３】キャップ上には基板とキャップを跨ぐ表面実装
部品のみ実装されている混成集積回路装置の断面図であ
る。FIG. 3 is a cross-sectional view of a hybrid integrated circuit device in which only a substrate and surface mount components that straddle the cap are mounted on the cap.
【図４】キャップ上にのみ表面実装部品が実装されてい
る混成集積回路装置の断面図である。FIG. 4 is a cross-sectional view of a hybrid integrated circuit device in which surface mount components are mounted only on a cap.
【図５】キャップ上には回路配線層のみ設けられている
混成集積回路装置の断面図である。FIG. 5 is a cross-sectional view of a hybrid integrated circuit device in which only a circuit wiring layer is provided on a cap.
【図６】従来の混成集積回路装置を示す断面図である。FIG. 6 is a cross-sectional view showing a conventional hybrid integrated circuit device.
１０，５０…印刷配線積層基板、１１，６３…内部配
線、１２，６２…ビアホール、１３，５４…収容部、１
４…配線、１５，５９…基板上の回路配線層、１６，５
３…半導体素子、１７，３４，６１…半田、１８，５６
…ワイヤ、１９，５２…ロウ材、２０，５１…端子、３
０，５７…キャップ、３１，５８…シール材、３２…キ
ャップ上の回路配線層、３３ａ…基板とキャップを跨い
で実装されている表面実装部品、３３ｂ…キャップ上に
実装されている表面実装部品、３５…突部、３６…リー
ド線、３７…外部リード線、５５…接着剤、６０…表面
実装部品10, 50 ... Printed wiring laminated substrate, 11, 63 ... Internal wiring, 12, 62 ... Via hole, 13, 54 ... Housing section, 1
4 ... Wiring, 15, 59 ... Circuit wiring layer on substrate, 16, 5
3 ... Semiconductor element, 17, 34, 61 ... Solder, 18, 56
... Wires, 19, 52 ... Brazing materials, 20, 51 ... Terminals, 3
0, 57 ... Cap, 31, 58 ... Sealing material, 32 ... Circuit wiring layer on the cap, 33a ... Surface-mounted component mounted across the substrate and the cap, 33b ... Surface-mounted component mounted on the cap , 35 ... Protrusion, 36 ... Lead wire, 37 ... External lead wire, 55 ... Adhesive agent, 60 ... Surface mount component
Claims (4)
導体素子を搭載し、その収容部開口をキャップにて閉塞
して半導体素子を封止した混成集積回路装置において、 前記キャップ表面に回路配線層を形成した混成集積回路
装置。1. A hybrid integrated circuit device in which a semiconductor element is mounted in a recess formed in a printed wiring board and the opening of the recess is closed by a cap to seal the semiconductor element. A hybrid integrated circuit device in which a wiring layer is formed.
前記回路配線層上に表面実装部品を設けた混成集積回路
装置。2. The hybrid integrated circuit device according to claim 1,
A hybrid integrated circuit device in which a surface mount component is provided on the circuit wiring layer.
印刷配線積層基板はその表面に回路配線層が形成され、
キャップはその表面が印刷配線積層基板の表面と面一と
なるように印刷配線積層基板に取着され、キャップの回
路配線層と印刷配線積層基板の表面に形成した回路配線
層とを表面実装部品を介して電気的に接続した混成集積
回路装置。3. The hybrid integrated circuit device according to claim 2,
The printed wiring laminated board has a circuit wiring layer formed on its surface,
The cap is attached to the printed wiring laminated board so that its surface is flush with the surface of the printed wiring laminated board, and the circuit wiring layer of the cap and the circuit wiring layer formed on the surface of the printed wiring laminated board are surface-mounted components. A hybrid integrated circuit device electrically connected via a.
集積回路装置において、キャップの熱膨張係数が印刷配
線積層基板の熱膨張係数と同程度の材質である混成集積
回路装置。4. The hybrid integrated circuit device according to claim 1, wherein the cap has a coefficient of thermal expansion substantially equal to that of the printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22358593A JPH0778935A (en) | 1993-09-08 | 1993-09-08 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22358593A JPH0778935A (en) | 1993-09-08 | 1993-09-08 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0778935A true JPH0778935A (en) | 1995-03-20 |
Family
ID=16800476
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22358593A Pending JPH0778935A (en) | 1993-09-08 | 1993-09-08 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0778935A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2339337A (en) * | 1995-06-16 | 2000-01-19 | Nec Corp | Semiconductor device mounting in recesses in a circuit board |
| GB2302451B (en) * | 1995-06-16 | 2000-01-26 | Nec Corp | Semiconductor device mounting method and multi-chip module produced by the same |
-
1993
- 1993-09-08 JP JP22358593A patent/JPH0778935A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2339337A (en) * | 1995-06-16 | 2000-01-19 | Nec Corp | Semiconductor device mounting in recesses in a circuit board |
| GB2302451B (en) * | 1995-06-16 | 2000-01-26 | Nec Corp | Semiconductor device mounting method and multi-chip module produced by the same |
| GB2339337B (en) * | 1995-06-16 | 2000-03-01 | Nec Corp | Semiconductor device mounting method and multi-chip module produced by the same |
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