JPH0776131A - Image device - Google Patents
Image deviceInfo
- Publication number
- JPH0776131A JPH0776131A JP18061393A JP18061393A JPH0776131A JP H0776131 A JPH0776131 A JP H0776131A JP 18061393 A JP18061393 A JP 18061393A JP 18061393 A JP18061393 A JP 18061393A JP H0776131 A JPH0776131 A JP H0776131A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- array
- flip
- rigidity
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【発明の利用分野】この発明はＬＥＤヘッドや密着型イ
メージセンサ、液晶シャッタアレイヘッド等の画像装置
に関し、特にフリップチップ接続型の画像装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image device such as an LED head, a contact image sensor, a liquid crystal shutter array head, etc., and more particularly to a flip chip connection type image device.
【０００２】[0002]
【従来技術】ＬＥＤヘッドなどの画像装置において、受
発光アレイを基板にフリップチップ接続することが提案
されている（例えば実開昭６３−１８０，２４９号公
報）。フリップチップ接続の利点は、高速で多数の接続
を行えることにある。しかしながらフリップチップ接続
には以下のような問題点があり、しかもこの点に言及し
た先行技術は見つからなかった。 1) 接続時に受発光アレイのバンプや受発光体などのパ
ターンが見えず、アレイの背面を見て搭載することにな
る。 2) フリップチップ接続ではアレイを加圧しながら接続
するが、圧力が均一に加わらずアレイを破壊することが
ある。2. Description of the Related Art In an image device such as an LED head, it has been proposed to flip-chip connect a light emitting and receiving array to a substrate (for example, Japanese Utility Model Laid-Open No. 63-180,249). The advantage of flip-chip connection is that it enables a large number of connections at high speed. However, the flip-chip connection has the following problems, and the prior art that refers to this point has not been found. 1) At the time of connection, the bumps of the light emitting / receiving array and the pattern of the light emitting / receiving body cannot be seen. 2) In flip-chip connection, the array is connected while applying pressure, but the pressure may not be applied uniformly and the array may be destroyed.
【０００３】上記の1)の点を説明すると、従来例ではア
レイの背面を見ながらコレット等で搬送し、基板のマー
カを見て位置決めすることになる。搭載済みのアレイも
背面しか見えず、搭載済みのアレイのパターンを次のア
レイの位置決めに使うことができない。ところでアレイ
の背面から分かるものはウェハーからアレイを切り出し
た際のラインであり、これは受発光体のパターンとは直
接関係が無い。ダイシング時のライン（アレイの背面形
状）と受発光体のパターンとの間にはダイシング精度だ
けの誤差があり、これは±１００μｍ程度に達する。そ
して受発光アレイの搭載精度はこれよりもはるかに高く
する必要がある。そこでアレイの外形を用いて搭載する
と、画像装置において決定的に重要なアレイの搭載精度
が得られないことになる。Explaining point 1) above, in the conventional example, the array is conveyed by a collet or the like while looking at the back surface of the array and the marker on the substrate is used for positioning. The mounted array can only see the back side, and the pattern of the mounted array cannot be used to position the next array. By the way, what can be seen from the back surface of the array is a line when the array is cut out from the wafer, and this is not directly related to the pattern of the light receiving and emitting bodies. There is an error of only dicing accuracy between the line (back surface shape of the array) and the pattern of the light receiving and emitting body during dicing, which reaches about ± 100 μm. The mounting accuracy of the light emitting and receiving array must be much higher than this. Therefore, if mounting is performed by using the outer shape of the array, the mounting accuracy of the array, which is crucial in the image device, cannot be obtained.
【０００４】上記の2)の点を説明すると、例えばアレイ
には金バンプを形成し、基板には例えば半田バンプを作
り、仮止め後にリフロー炉などでフリップチップ接続を
完成することになる。ここでアレイにかなりの圧力を加
えることが必要で、この圧力は例えばアレイ１個当たり
数Ｋｇ程度に達する。基板には多数のアレイを搭載し、
加圧はリフロー炉を通す際に全てのアレイに同時に加え
る。そして全てのアレイに均一に圧力を加えるのは難し
く、圧力にばらつきが有ると脆弱なＧａＡｓなどの受発
光アレイを損傷する。Explaining the above point 2), for example, gold bumps are formed on the array, solder bumps are formed on the substrate, and after the temporary fixing, the flip chip connection is completed in a reflow furnace or the like. Here, it is necessary to apply a considerable pressure to the array, which pressure reaches, for example, several Kg per array. A large number of arrays are mounted on the board,
Pressurization is applied to all arrays simultaneously as they pass through the reflow oven. It is difficult to apply pressure uniformly to all the arrays, and variations in pressure damage the fragile light emitting and receiving array such as GaAs.
【０００５】[0005]
【発明の課題】請求項１の発明は、フリップチップ接続
型の画像装置において、以下の課題を満たす構造を提供
することにある。 1) 受発光アレイのパターンを見ながら基板に搭載する
ことを可能にし、アレイの搭載精度を高める。 2) フリップチップ接続時に、全ての受発光アレイを均
一に加圧できるようにし、アレイの損傷を防止する。It is an object of the present invention to provide a structure for a flip-chip connection type image device that satisfies the following problems. 1) It is possible to mount on the substrate while observing the pattern of the light emitting and receiving array, and improve the mounting accuracy of the array. 2) When flip-chip connection, all the light emitting and receiving arrays can be pressed uniformly to prevent damage to the arrays.
【０００６】請求項２の発明の課題は、上記に加えて、
この発明で用いる少なくとも２枚の基板に対し、 3) 表面平坦度が高く、反りなどの変形が少なく、かつ
温度変形が小さくなるようにし、 4) しかもこのことを、基板のコストを最小にしながら
実現することにある。The object of the invention of claim 2 is, in addition to the above,
For at least two substrates used in the present invention, 3) the surface flatness is high, the deformation such as warpage is small, and the temperature deformation is small. 4) Moreover, while minimizing the cost of the substrate, It is to be realized.
【０００７】[0007]
【発明の構成】この発明の画像装置は、共通電極配線を
施した第１の基板と、データバスを設けた第２の基板と
の間に受発光アレイを搭載し、該アレイの共通電極を第
１の基板の共通電極配線に接続し、該アレイの個別電極
を第２の基板のデータバスにフリップチップ接続したこ
とを特徴とする。好ましくは、前記第１及び第２の基板
の一方を高剛性低熱膨張率基板で構成し、他方の基板を
低剛性基板で構成する。受発光アレイには例えばＬＥＤ
アレイ、液晶シャッタアレイ、ＰＬＺＴアレイ、ＣＣＤ
アレイなどを用いる。また高剛性低熱膨張率基板として
は例えば、ガラス基板，セラミック基板，あるいは結晶
化ガラス基板などを用い、受発光アレイと熱膨張率が近
似するもしくは熱膨張率が０に近いものを用い、好まし
くは任意の熱膨張率が得られ受発光アレイと熱膨張率を
揃え易い結晶化ガラス基板を用いる。低剛性基板として
は例えばフレキシブルプリント基板やガラスフィルム基
板，あるいは硬質プリント基板などを用い、安価で剛性
の低い硬質プリント基板が好ましい。According to the image device of the present invention, a light emitting / receiving array is mounted between a first substrate provided with a common electrode wiring and a second substrate provided with a data bus, and a common electrode of the array is provided. It is characterized in that it is connected to the common electrode wiring of the first substrate and the individual electrodes of the array are flip-chip connected to the data bus of the second substrate. Preferably, one of the first and second substrates is a high-rigidity low thermal expansion substrate, and the other substrate is a low-rigidity substrate. For the light emitting / receiving array, for example, an LED
Array, liquid crystal shutter array, PLZT array, CCD
An array or the like is used. As the high-rigidity and low-thermal-expansion substrate, for example, a glass substrate, a ceramic substrate, a crystallized glass substrate, or the like is used, and a substrate whose thermal expansion coefficient is close to or close to that of the light-receiving / emitting array is preferably used. A crystallized glass substrate is used that has an arbitrary coefficient of thermal expansion and is easily aligned with the light receiving and emitting array. As the low-rigidity substrate, for example, a flexible printed circuit board, a glass film substrate, or a hard printed circuit board is used, and a hard printed circuit board which is inexpensive and has low rigidity is preferable.
【０００８】[0008]
【発明の作用】この発明の画像装置では、少なくとも２
枚の基板で受発光アレイをサンドイッチし、第１の基板
にアレイを搭載した後に第２の基板にフリップチップ接
続できる構造とする。第１の基板への搭載では、受発光
体のパターン側（アレイの正面）が見えるように並べた
アレイをコレットなどで搬送し搭載する。コレットでピ
ックアップする際にはアレイのパターンが見え、アレイ
のパターンを基準に、第１の基板への搭載位置を定め
る。基板には搭載位置のマーカを設け、このマーカを手
がかりにあるいは既に搭載済みのアレイのパターンを手
がかりに搭載する。このようにすれば、アレイの外形寸
法にとらわれずに、アレイの実際のパターンを基準に第
１の基板に搭載でき、アレイを精密に搭載できる。次い
で第２の基板にフリップチップ接続する。アレイは第１
の基板の搭載時に位置決めが完了しており、もはや位置
ずれの問題はない。フリップチップ接続時のアレイへの
加圧では、第１の基板と第２の基板でアレイをサンドイ
ッチしたので、全てのアレイを均一に加圧できる。この
結果、局所的加圧によるアレイの損傷はなくなる。According to the image device of the present invention, at least 2
The light emitting and receiving array is sandwiched between a single substrate, the array is mounted on the first substrate, and then the second substrate is flip-chip connected. In mounting on the first substrate, an array arranged so that the pattern side (front side of the array) of the light receiving and emitting bodies can be seen is transported by a collet or the like and mounted. When picked up by the collet, the array pattern is visible, and the mounting position on the first substrate is determined based on the array pattern. A marker for the mounting position is provided on the substrate, and the marker is used as a clue or the pattern of the already mounted array is mounted as a clue. With this arrangement, the actual pattern of the array can be mounted on the first substrate as a reference, and the array can be mounted precisely regardless of the outer dimensions of the array. Next, flip chip connection is made to the second substrate. Array is first
Since the positioning is completed when the board is mounted, there is no problem of misalignment. When applying pressure to the array during flip-chip connection, since the array is sandwiched between the first substrate and the second substrate, it is possible to uniformly apply pressure to all arrays. This results in no damage to the array due to local pressure.
【０００９】２枚の基板に全て高精度基板を用いること
は無駄である。また高精度基板，例えばガラス基板やセ
ラミック基板は剛性が高く、２枚の基板を共に高精度基
板とすると基板の変形で力を吸収することができず、外
力や熱応力などがアレイやフリップチップ接続部などに
集中しかえって好ましくない。そこで請求項２の発明で
は、一方の基板のみを高剛性低熱膨張率基板とし、他方
は低剛性基板とする。低剛性基板は高剛性基板に応じて
変形し、高剛性基板で位置精度を出せば低剛性基板はそ
れに従う。そこで高剛性基板の表面平坦度や反りの小さ
さを利用し、低剛性基板はそれに合わせて変形させる。
高剛性基板の熱膨張率が受発光アレイに近ければ、低剛
性基板もそれに応じて熱変形し熱応力などは発生しな
い。また温度変化が有っても、画像装置は全体として同
じ膨張率で変形するだけである。ここで画像装置の用途
によっては、例えば画像装置を２組用い２組の画像を合
成して最終画像とするような場合には、文字通りに温度
変形が小さいことが要求される。そのような場合には、
高剛性基板の熱膨張率を文字通りに０に近づけることが
好ましい。It is wasteful to use high precision substrates for the two substrates. In addition, high precision substrates, such as glass substrates and ceramic substrates, have high rigidity, and if two substrates are both high precision substrates, the forces cannot be absorbed by the deformation of the substrates, and external force or thermal stress may cause array or flip chip. It is not preferable because it concentrates on the connection part. Therefore, in the second aspect of the present invention, only one of the substrates is a high-rigidity low thermal expansion substrate and the other is a low-rigidity substrate. The low-rigidity substrate deforms according to the high-rigidity substrate, and if the high-rigidity substrate provides positional accuracy, the low-rigidity substrate follows it. Therefore, the surface flatness and the small warpage of the high-rigidity substrate are used, and the low-rigidity substrate is deformed accordingly.
If the coefficient of thermal expansion of the high-rigidity substrate is close to that of the light emitting / receiving array, the low-rigidity substrate is also thermally deformed accordingly, and thermal stress does not occur. Further, even if there is a temperature change, the image device as a whole only deforms at the same expansion rate. Here, depending on the use of the image device, for example, when two image devices are used and two sets of images are combined to form the final image, it is required that the temperature deformation is literally small. In such cases,
It is preferable that the coefficient of thermal expansion of the high-rigidity substrate literally approaches zero.
【００１０】[0010]
【実施例】図１〜図５に、最初の実施例を示す。図１に
フリップチップ接続後の画像装置の要部断面を示し、図
において、２は第１の基板で、ガラス基板やセラミック
基板，あるいは結晶化ガラス基板等を用いる。これらの
基板はいずれも、剛性が高く反りが小さくかつプラスチ
ック基板等に比べて熱膨張率が小さい。４は第２の基板
で、フレキシブルプリント基板や透明プラスチック基板
あるいはガラスフィルム基板等の、剛性が低く透明な基
板を用いる。６はＬＥＤアレイで、基板２，４の間にサ
ンドイッチして多数直線状に搭載し、共通電極側を第１
の基板２に、個別電極側を第２の基板４に接続する。８
は第１の基板２に設けた共通電極配線で、１０は銀ペー
スト等の導電性接着剤、１２はＬＥＤアレイ６の共通電
極である。１４はＬＥＤアレイ６の個別電極に設けた金
バンプで、１６は第２の基板４に設けた半田バンプであ
る。そして金バンプ１４と半田バンプ１６とをフリップ
チップ接続する。なおＬＥＤアレイ６側に半田バンプを
設け、基板４側に金バンプを設けても良い。EXAMPLE A first example is shown in FIGS. FIG. 1 shows a cross section of the main part of the image device after flip-chip connection. In the figure, reference numeral 2 denotes a first substrate, which is a glass substrate, a ceramic substrate, a crystallized glass substrate, or the like. Each of these substrates has high rigidity and small warpage, and has a smaller coefficient of thermal expansion than plastic substrates and the like. Reference numeral 4 denotes a second substrate, which is a transparent substrate having low rigidity such as a flexible printed circuit board, a transparent plastic substrate or a glass film substrate. Reference numeral 6 denotes an LED array, which is sandwiched between the substrates 2 and 4 and mounted in a plurality of straight lines with the common electrode side being the first
The individual electrode side of the substrate 2 is connected to the second substrate 4. 8
Is a common electrode wiring provided on the first substrate 2, 10 is a conductive adhesive such as silver paste, and 12 is a common electrode of the LED array 6. Reference numeral 14 is a gold bump provided on the individual electrode of the LED array 6, and 16 is a solder bump provided on the second substrate 4. Then, the gold bump 14 and the solder bump 16 are flip-chip connected. Note that solder bumps may be provided on the LED array 6 side and gold bumps may be provided on the substrate 4 side.
【００１１】図２に、第１の基板２へのＬＥＤアレイ６
の搭載工程を示す。第１の基板２には精密配線は必要で
なく、共通電極配線８とＬＥＤアレイ６の搭載位置を位
置決めするための基板マーカ１８とを設けておく。次に
アレイ６を搭載する部分に導電性接着剤１０を塗布す
る。２０，２０はＬＥＤアレイ６に設けたチップマーカ
で、発光体２２に接続した個別電極と同時に形成し、個
別電極と常に一定の位置関係をもっている。ダイシング
後のＬＥＤアレイ６を、発光体２２側を表にしてトレー
等に収容し、コレット等で１個ずつピックアップして基
板２に搭載する。In FIG. 2, the LED array 6 on the first substrate 2 is shown.
The mounting process of is shown. Precise wiring is not necessary on the first substrate 2, and the common electrode wiring 8 and the substrate marker 18 for positioning the mounting position of the LED array 6 are provided in advance. Next, the conductive adhesive 10 is applied to the portion where the array 6 is mounted. Reference numerals 20 and 20 denote chip markers provided on the LED array 6, which are formed at the same time as the individual electrodes connected to the light-emitting body 22 and always have a fixed positional relationship with the individual electrodes. The LED array 6 after dicing is housed in a tray or the like with the light emitting body 22 side facing up, picked up one by one with a collet or the like, and mounted on the substrate 2.
【００１２】最初のＬＥＤアレイ６の搭載では、基板マ
ーカ１８に対してチップマーカ２０が正しい位置に現れ
るように搭載位置を定める。２番目以降のＬＥＤアレイ
６の搭載では、前に搭載したＬＥＤアレイ６のチップマ
ーカ２０を手がかりにして、次のアレイ６の搭載位置を
定める。ここでも、前のアレイ６のチップマーカ２０に
対して次のアレイ６のチップマーカ２０が所定の位置に
現れるように搭載位置を定めると共に、基板マーカ１８
を用いて搭載位置を確認し、搭載位置の誤差が累積して
いくのを防止する。When mounting the LED array 6 for the first time, the mounting position is determined so that the chip marker 20 appears at the correct position with respect to the substrate marker 18. In mounting the second and subsequent LED arrays 6, the chip marker 20 of the LED array 6 mounted before is used as a clue to determine the mounting position of the next array 6. Also here, the mounting position is determined so that the chip marker 20 of the next array 6 appears at a predetermined position with respect to the chip marker 20 of the previous array 6, and the board marker 18
Check the mounting position using to prevent the mounting position error from accumulating.
【００１３】図３に、フリップチップ接続前の第２の基
板４を示す。２４，２６はデータバスで、真空蒸着Ａｌ
配線やエッチングによる銅配線等を用いる。２８は半田
バンプ１６の列で、ここでＬＥＤアレイ６の金バンプ１
４とフリップチップ接続する。データバス２４，２６は
折り返し配線で、データバス２４はＬＥＤアレイ６の個
別電極に接続し、ＬＥＤアレイ６の個別電極はデータバ
ス２６に接続する。FIG. 3 shows the second substrate 4 before flip-chip connection. 24 and 26 are data buses, which are vacuum deposited Al
A wiring or a copper wiring by etching is used. 28 is a row of solder bumps 16, where the gold bumps 1 of the LED array 6
4 and flip chip connection. The data buses 24 and 26 are return wirings, the data bus 24 is connected to the individual electrodes of the LED array 6, and the individual electrodes of the LED array 6 are connected to the data bus 26.
【００１４】図４に、実施例で用いたＬＥＤアレイ６を
示す。２０は前記のチップマーカ、２２は発光体で、ア
レイ６の１個当たり例えば６４ドット程度設け、１４は
前記の金バンプで、データバス２４に上側の金バンプ１
４−１を接続し、アレイの個別電極で金バンプ１４−１
と金バンプ１４−２とを接続し、下側の金バンプ１４−
２をデータバス２６に接続する。このように発光体２２
の１個当たり２個の金バンプ１４，１４を設け２箇所で
フリップチップ接続することにより、データバス２４，
２６を接続する。FIG. 4 shows the LED array 6 used in the embodiment. Reference numeral 20 is the chip marker, 22 is a light emitting body, and for example, about 64 dots are provided for each of the arrays 6, 14 is the gold bump, and the upper gold bump 1 is connected to the data bus 24.
4-1 is connected, and gold bumps 14-1 are connected to the individual electrodes of the array.
And the gold bump 14-2 are connected to each other, and the lower gold bump 14-
2 is connected to the data bus 26. In this way, the luminous body 22
By providing two gold bumps 14, 14 per one of them, and flip-chip connecting at two places, the data bus 24,
26 is connected.
【００１５】図５に、実施例のＬＥＤヘッドの組立工程
を示す。ＬＥＤアレイ６の外形ラインと実際のパターン
との間には、±１００μｍ程度の位置のばらつきがあ
る。これはアレイ６の外形がダイシングによって定まる
もので、パターンとは特に関係がないことによる。そし
てフリップチップ接続では、ＬＥＤアレイ６の実際のパ
ターンに対して例えば±１０μｍ以下の誤差で搭載する
ことが必要となる。この条件を満たせない場合、アレイ
６，６の変わり目で発光体２２，２２の間隔が変動し白
筋や黒筋等が生じることになる。実施例では、コレット
でＬＥＤアレイ６をピックアップする際に、チップマー
カ２０をパターン認識し、また基板２に対しては、基板
マーカ１８や既に搭載済みのＬＥＤアレイ６のチップマ
ーカ２０を用いて、次のＬＥＤアレイ６の搭載位置を決
定する。このようにすればＬＥＤアレイ６の実際のパタ
ーンを基に搭載位置を決定することになり、例えば±１
０μｍ以下の誤差でＬＥＤアレイ６を搭載できる。基板
２に４０個のＬＥＤアレイ６を搭載することにすると、
前のアレイ６のチップマーカ２０を見て次のアレイ６を
搭載するステップを繰り返し、４０アレイの搭載後に最
後の基板マーカ１８に対するチップマーカ２０の位置を
確認する。搭載が正しく累積搭載誤差がなければ、チッ
プマーカ２０に対して基板マーカ１８は所定の位置に現
れるはずである。FIG. 5 shows an assembly process of the LED head of the embodiment. There is a position variation of about ± 100 μm between the outline of the LED array 6 and the actual pattern. This is because the outer shape of the array 6 is determined by dicing and is not particularly related to the pattern. In the flip-chip connection, it is necessary to mount the LED array 6 with an error of ± 10 μm or less with respect to the actual pattern. If this condition is not satisfied, the spacing between the light-emitting bodies 22, 22 will change at the turn of the arrays 6, 6 and white or black streaks will occur. In the embodiment, when the LED array 6 is picked up by the collet, the chip marker 20 is pattern-recognized, and for the board 2, the board marker 18 or the chip marker 20 of the already mounted LED array 6 is used. The mounting position of the next LED array 6 is determined. In this way, the mounting position is determined based on the actual pattern of the LED array 6, for example ± 1
The LED array 6 can be mounted with an error of 0 μm or less. If 40 LED arrays 6 are mounted on the board 2,
The step of mounting the next array 6 by looking at the chip marker 20 of the previous array 6 is repeated, and after mounting 40 arrays, the position of the chip marker 20 with respect to the last substrate marker 18 is confirmed. If the mounting is correct and there is no accumulated mounting error, the board marker 18 should appear at a predetermined position with respect to the chip marker 20.
【００１６】次に予め半田バンプ１６を設けた第２の基
板４を、第１の基板２に仮止めする。この時半田バンプ
１６のフラッックスにより、バンプ１６とバンプ１４と
が仮止めされる。第２の基板４は透明基板であり、半田
バンプ１６が金バンプ１４に重なるように、あるいは第
２の基板４に設けたマーカが基板マーカ１８等に重なる
ように位置合わせする。この状態でＬＥＤアレイ６は第
１の基板２と第２の基板４とにサンドイッチされ、基板
２，４間に圧力を加えるとこの力がＬＥＤアレイ６に加
わる。この力はフリップチップ接続での仮止めに必要
で、例えばＬＥＤアレイ６の１個当たり数ｋｇ程度とす
る。ＬＥＤアレイ６は２枚の基板２，４に挟まれている
ので４０個のＬＥＤアレイ６にほぼ均一な圧力が加わ
り、局部的に圧力が集中してＬＥＤアレイ６が損傷する
ことがない。この状態で基板２，４間にサンドイッチし
たＬＥＤアレイ６をリフロー炉等に通せば、半田付けに
よるフリップチップ接続が完成する。Next, the second substrate 4 provided with the solder bumps 16 in advance is temporarily fixed to the first substrate 2. At this time, due to the flux of the solder bumps 16, the bumps 16 and 14 are temporarily fixed. The second substrate 4 is a transparent substrate and is aligned so that the solder bumps 16 overlap the gold bumps 14 or the markers provided on the second substrate 4 overlap the substrate markers 18 and the like. In this state, the LED array 6 is sandwiched between the first substrate 2 and the second substrate 4, and when a pressure is applied between the substrates 2 and 4, this force is applied to the LED array 6. This force is necessary for temporary fixing by flip-chip connection, and is, for example, about several kg per LED array 6. Since the LED array 6 is sandwiched between the two substrates 2 and 4, almost uniform pressure is applied to the 40 LED arrays 6 and the pressure is not locally concentrated to damage the LED array 6. In this state, the LED array 6 sandwiched between the substrates 2 and 4 is passed through a reflow furnace or the like to complete flip chip connection by soldering.
【００１７】実施例では第１の基板２を剛性が高く熱膨
張率が小さな基板とし、第２の基板４は剛性の低い基板
とした。基板２，４の両方を剛性の高い基板とすること
は無駄であるし、危険でもある。例えば基板２，４をサ
ンドイッチする際に両者間に力が加わった場合、基板を
２枚とも高剛性の基板とすると力の逃げ場がなく、フリ
ップチップ接続部やＬＥＤアレイ６が損傷することにな
る。これに対して第２の基板４を低剛性の基板としてお
けば、基板４の変形によって力が吸収され、ＬＥＤアレ
イ６等の損傷を防止することができる。次に第１の基板
２はガラスやセラミックあるいは結晶化ガラス等の反り
の小さく表面精度の高い基板である。そして第２の基板
４は低剛性で本来は反り等が大きい精度の低い基板であ
るが、剛性が低いので第１の基板２に応じて変形し、第
１の基板２の精度を用いて第２の基板４の精度を出すこ
とができる。In the embodiment, the first substrate 2 has a high rigidity and a small thermal expansion coefficient, and the second substrate 4 has a low rigidity. It is wasteful and dangerous to use both of the substrates 2 and 4 as a substrate having high rigidity. For example, when a force is applied between the substrates 2 and 4 when sandwiching them, if the two substrates are high-rigidity substrates, there is no escape area for the forces and the flip chip connection part and the LED array 6 are damaged. . On the other hand, if the second substrate 4 is a low-rigidity substrate, the deformation of the substrate 4 absorbs the force, and damage to the LED array 6 and the like can be prevented. Next, the first substrate 2 is a substrate of glass, ceramic, crystallized glass, or the like with a small warpage and a high surface accuracy. The second substrate 4 is a low-rigidity substrate that is originally low in rigidity and has large warpage and the like, but since it has low rigidity, it is deformed in accordance with the first substrate 2, and the second substrate 4 is deformed in accordance with the accuracy of the first substrate 2. The accuracy of the second substrate 4 can be obtained.
【００１８】ガラスやセラミックあるいは結晶化ガラス
等の材質は、第２の基板４の材質であるプラスチックに
比べて熱膨張率が小さく、ＬＥＤアレイ６の熱膨張率に
近い。この結果ＬＥＤアレイ６と第１の基板２との間の
相対的な温度変形は小さく、第２の基板４は剛性が低い
ため第１の基板２にしたがって温度変形し、熱応力等が
小さくなる。そしてこのことは、周囲温度が変化しても
ＬＥＤアレイ６，６間の間隔が変化しないことや金バン
プ１４に対する半田バンプ１６の位置が変化しないこと
を意味する。Materials such as glass, ceramics, and crystallized glass have a smaller coefficient of thermal expansion than the material of the second substrate 4, that is, plastic, and are close to the coefficient of thermal expansion of the LED array 6. As a result, the relative temperature deformation between the LED array 6 and the first substrate 2 is small, and since the second substrate 4 has low rigidity, it is temperature-deformed according to the first substrate 2 and the thermal stress and the like are reduced. . This means that the spacing between the LED arrays 6 and 6 does not change even if the ambient temperature changes, and the position of the solder bump 16 with respect to the gold bump 14 does not change.
【００１９】なお用途によっては、ＬＥＤヘッドの熱膨
張率を文字どおり０にする必要がある。このような場
合、第１の基板２にＳｉＯ2 ９３重量％、ＴｉＯ2 ７重
量％等のＳｉＯ2−ＴｉＯ2ガラス等を用いれば、基板２
の熱膨張率を実質上０にすることができる。Depending on the application, it is necessary to make the coefficient of thermal expansion of the LED head literally zero. In this case, if the first substrate 2 is made of SiO2-TiO2 glass containing 93% by weight of SiO2 and 7% by weight of TiO2, the substrate 2
The coefficient of thermal expansion of can be substantially zero.
【００２０】実施例では、ＬＥＤアレイ６の１個毎に基
板マーカ１８を設けたが、基板マーカ１８は基板２の両
端の２箇所にのみ設けても良い。また第２の基板４は１
層配線としデータバス２４，２６は折り返し配線とした
が、多層配線としても良く、折り返し配線以外のものを
用いても良い。In the embodiment, the board marker 18 is provided for each one of the LED arrays 6, but the board markers 18 may be provided only at two positions on both ends of the board 2. The second substrate 4 is 1
Although the data buses 24 and 26 are layered wirings and are folded wirings, they may be multilayer wirings and other wirings may be used.
【００２１】[0021]
【実施例２】図６に、第２の実施例を示す。図におい
て、３０は硬質プリント基板で第２の基板として用い、
３２はスルーホールでＬＥＤアレイ６からの光を通すた
めのものである。図１〜図５の実施例では、第２の基板
４として透明基板を用いたが、安価な硬質プリント基板
３０でも第２の基板を構成できる。他の点では図１〜図
５の実施例と同様である。Second Embodiment FIG. 6 shows a second embodiment. In the figure, 30 is a hard printed circuit board, which is used as a second circuit board.
Reference numeral 32 is a through hole for passing light from the LED array 6. Although the transparent substrate is used as the second substrate 4 in the embodiments shown in FIGS. 1 to 5, the second substrate can be constituted by an inexpensive rigid printed board 30. The other points are similar to those of the embodiment shown in FIGS.
【００２２】[0022]
【実施例３】図７に、第３の実施例を示す。図におい
て、４０は硬質プリント基板で、４２はガラス基板であ
る。そして硬質プリント基板４０を第１の基板とし、ガ
ラス基板４２に硬質プリント基板３０を貼りつけたもの
を第２の基板とする。このようにした基本的目的は、図
６の実施例ではスルーホール３２のため硬質プリント基
板３０の強度が低下するので、ガラス基板４２により強
度を増加させることにある。またガラス基板４２を用い
ると、ガラス基板４２の側が高剛性で熱膨張率の小さな
基板となり、これに応じて第１の基板には剛性の低い硬
質プリント基板４０を用いた。Third Embodiment FIG. 7 shows a third embodiment. In the figure, 40 is a rigid printed circuit board and 42 is a glass substrate. The hard printed board 40 is used as the first board, and the glass board 42 to which the hard printed board 30 is attached is used as the second board. The basic purpose of doing so is to increase the strength of the glass substrate 42 because the strength of the rigid printed circuit board 30 is reduced due to the through holes 32 in the embodiment of FIG. Further, when the glass substrate 42 is used, the side of the glass substrate 42 becomes a substrate having high rigidity and a small coefficient of thermal expansion, and accordingly, the rigid printed circuit board 40 having low rigidity is used as the first substrate.
【００２３】[0023]
【発明の効果】請求項１の発明では、以下の効果が得ら
れる。 1) 受発光アレイのパターンを見ながら基板に搭載する
ことができ、アレイの搭載精度が高まる。 2) フリップチップ接続時に受発光アレイを均一に加圧
でき、アレイの損傷を防止できる。According to the invention of claim 1, the following effects can be obtained. 1) It can be mounted on the substrate while watching the pattern of the light emitting and receiving array, and the mounting accuracy of the array is improved. 2) The light emitting / receiving array can be uniformly pressed during flip chip connection, and damage to the array can be prevented.
【００２４】請求項２の発明では、上記に加えて、 3) 基板のコストを最小にしながら、基板の表面平坦度
を高め、反りなどの変形を少なくし、かつ温度変形を小
さくできる。According to the invention of claim 2, in addition to the above, 3) it is possible to increase the surface flatness of the substrate, reduce deformation such as warpage, and reduce temperature deformation while minimizing the cost of the substrate.
【図１】 実施例の画像装置の長手方向要部断面図FIG. 1 is a cross-sectional view of essential parts in a longitudinal direction of an image device according to an embodiment.
【図２】 実施例の画像装置での第１の基板の要部平
面図FIG. 2 is a plan view of a main part of a first substrate in the image device according to the embodiment.
【図３】 実施例で画像装置での第２の基板の平面図FIG. 3 is a plan view of the second substrate in the image device according to the embodiment.
【図４】 実施例で用いたＬＥＤアレイの平面図FIG. 4 is a plan view of an LED array used in an example.
【図５】 実施例の画像装置の組立工程を示すフロー
チャートFIG. 5 is a flowchart showing an assembly process of the image device according to the embodiment.
【図６】 第２の実施例の画像装置の短片方向断面図FIG. 6 is a cross-sectional view in the direction of a short piece of an image device according to a second embodiment.
【図７】 第３の実施例の画像装置の短片方向断面図FIG. 7 is a cross-sectional view in the short piece direction of an image device according to a third embodiment.
２ 第１の基板 ４ 第２の基板 ６ ＬＥＤアレイ ８ 共通電極配線 １０ 導電性接着剤 １２ 金メッキ膜 １４ 金バンプ １６ 半田バンプ １８ 基板マーカ ２０ チップマーカ ２２ 発光体 ２４，２６ データバス ２８ 半田バンプの列 ３０ 硬質プリント基板 ３２ スルーホール ４０ 硬質プリント基板 ４２ ガラス基板 2 First Substrate 4 Second Substrate 6 LED Array 8 Common Electrode Wiring 10 Conductive Adhesive 12 Gold Plated Film 14 Gold Bump 16 Solder Bump 18 Substrate Marker 20 Chip Marker 22 Light Emitter 24, 26 Data Bus 28 Row of Solder Bumps 30 rigid printed circuit board 32 through hole 40 rigid printed circuit board 42 glass substrate
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 33/00 Ｎ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 33/00 N
Claims (2)
ータバスを設けた第２の基板との間に受発光アレイを搭
載し、 該アレイの共通電極を第１の基板の共通電極配線に接続
し、 該アレイの個別電極を第２の基板のデータバスにフリッ
プチップ接続したことを特徴とする、画像装置。1. A light emitting / receiving array is mounted between a first substrate provided with common electrode wiring and a second substrate provided with a data bus, and the common electrode of the array is used as the common electrode of the first substrate. An image device, characterized in that it is connected to wiring and individual electrodes of the array are flip-chip connected to a data bus of a second substrate.
低熱膨張率基板で構成し、他方の基板を低剛性基板で構
成したことを特徴とする、請求項１の画像装置。2. The image device according to claim 1, wherein one of the first and second substrates is a high-rigidity low thermal expansion substrate and the other substrate is a low-rigidity substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18061393A JP2918423B2 (en) | 1993-06-25 | 1993-06-25 | Imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18061393A JP2918423B2 (en) | 1993-06-25 | 1993-06-25 | Imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0776131A true JPH0776131A (en) | 1995-03-20 |
| JP2918423B2 JP2918423B2 (en) | 1999-07-12 |
Family
ID=16086301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18061393A Expired - Fee Related JP2918423B2 (en) | 1993-06-25 | 1993-06-25 | Imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2918423B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6087680A (en) * | 1997-01-31 | 2000-07-11 | Siemens Aktiengesellschaft | Led device |
| WO2001082378A1 (en) * | 2000-04-20 | 2001-11-01 | Schott Glas | Carrier substrate for electronic components |
| WO2004062908A3 (en) * | 2003-01-10 | 2004-09-10 | Glaverbel | Glazing comprising electronic elements |
| JP2016190459A (en) * | 2015-03-31 | 2016-11-10 | 株式会社沖データ | Light-emitting device manufacturing method |
| US11099702B2 (en) | 2016-02-05 | 2021-08-24 | Fujitsu Component Limited | Touchscreen and method of manufacturing touchscreen |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104518066B (en) * | 2013-09-30 | 2017-08-08 | 佛山市国星光电股份有限公司 | A kind of LED component and its method for packing with transition substrate |
-
1993
- 1993-06-25 JP JP18061393A patent/JP2918423B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6087680A (en) * | 1997-01-31 | 2000-07-11 | Siemens Aktiengesellschaft | Led device |
| WO2001082378A1 (en) * | 2000-04-20 | 2001-11-01 | Schott Glas | Carrier substrate for electronic components |
| EP1947694A1 (en) * | 2000-04-20 | 2008-07-23 | Schott AG | Supporting substrate for electronic components |
| DE10019888B4 (en) * | 2000-04-20 | 2011-06-16 | Schott Ag | Transparent electronic component arrangement and method for its production |
| WO2004062908A3 (en) * | 2003-01-10 | 2004-09-10 | Glaverbel | Glazing comprising electronic elements |
| US7745838B2 (en) | 2003-01-10 | 2010-06-29 | Agc Glass Europe | Glazing comprising electronics elements |
| JP2016190459A (en) * | 2015-03-31 | 2016-11-10 | 株式会社沖データ | Light-emitting device manufacturing method |
| US11099702B2 (en) | 2016-02-05 | 2021-08-24 | Fujitsu Component Limited | Touchscreen and method of manufacturing touchscreen |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2918423B2 (en) | 1999-07-12 |
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