JPH0774209A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0774209A JPH0774209A JP24197993A JP24197993A JPH0774209A JP H0774209 A JPH0774209 A JP H0774209A JP 24197993 A JP24197993 A JP 24197993A JP 24197993 A JP24197993 A JP 24197993A JP H0774209 A JPH0774209 A JP H0774209A
- Authority
- JP
- Japan
- Prior art keywords
- flux
- substrate
- chip
- soldering
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3489—Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に、フリップチップＩＣを基板にバンプ半田
付けする構造を有する半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a structure in which a flip-chip IC is bump-soldered on a substrate.
【０００２】[0002]
【従来の技術】従来は、フリップチップＩＣを基板に半
田付けする際、接合する部分に、充分にフラックスを供
給することが行われている（例えば、特開平2-257647号
公報）。この方法は、基板に予めクリーム半田を塗布
し、バンプ半田付けされたフリップチップＩＣを基板に
設置して加熱しつつ、フラックスを滴下してリフロー半
田付けしている。2. Description of the Related Art Conventionally, when a flip-chip IC is soldered to a substrate, sufficient flux is supplied to the joining portion (for example, Japanese Patent Laid-Open No. 2-257647). In this method, cream solder is applied to a substrate in advance, a flip-chip IC with bump soldering is placed on the substrate and heated, and flux is dropped to perform reflow soldering.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら上記の方
法では、フラックスが基板と部品との両方に、多量に接
していると、図２に示すように、半田付け工程中、もし
くは半田付け工程に入る前にＩＣ部品その他が浮遊し、
位置ずれを起こすという問題がある。対象とするＩＣは
微細なピッチの電極であり、わずかなずれは製品不良に
つながる。また、加熱中にフラックスを滴下すると、フ
ラックス中の溶剤成分が急激に気化して潜熱を奪い、半
田の表面温度が急下降して、接触不良やウィスカー、ブ
リッジ等を発生させてしまい、半田付けの信頼性を低下
させるという問題もある。それに加えて、その加熱され
た部分に低温のフラックスを供給したことによって発生
した突沸による半田ボールを発生させたり、半田付けさ
れる前にＩＣチップと基板間に発生した蒸気の膨張によ
り、部品が所定の箇所からずれてしまう。そのため、近
年のより微細化したＩＣにとっては製品の歩留りの低
下、信頼性の低下等の問題を生じる。However, in the above method, when a large amount of flux is in contact with both the substrate and the component, as shown in FIG. 2, the soldering process starts or the soldering process starts. IC parts and others float in front,
There is a problem of causing misalignment. The target IC is an electrode with a fine pitch, and a slight deviation leads to a product defect. Also, if flux is dropped during heating, the solvent component in the flux will rapidly vaporize and take latent heat, causing the surface temperature of the solder to drop sharply, resulting in poor contact, whiskers, bridges, etc. There is also the problem of reducing the reliability of. In addition to that, solder balls are generated due to bumping generated by supplying low-temperature flux to the heated part, or the steam generated between the IC chip and the substrate before being soldered expands the parts. It deviates from the predetermined place. Therefore, in recent years, ICs that have been made finer have problems such as a decrease in product yield and a decrease in reliability.
【０００４】[0004]
【課題を解決するための手段】上記の課題を解決するた
め本発明の第一の構成は、微細ピッチのフリップチップ
ＩＣを基板にバンプ半田付けする半導体装置の製造方法
において、前記フリップチップＩＣの電極に半田層を形
成しておく半田盛り工程と、前記基板上のチップ実装予
定部分に、前記フリップチップＩＣと前記基板との隙間
よりも薄い半田付け用フラックス薄膜を形成するフラッ
クス薄膜形成工程と、該フリップチップＩＣを、該基板
上に配置して仮加熱し、軽くバンプ半田付けする仮止め
工程と、前記仮止め工程後に、仮止めされた前記フリッ
プチップＩＣと該基板との間を充分覆うだけのフラック
スを付与するフラックス供給工程と、仮止めされた該フ
リップチップＩＣを完全にバンプ半田付けするリフロー
工程とを有することである。また第二の構成は、第一の
構成において、前記半田付け用フラックス薄膜が、印刷
技術もしくはディップ法もしくは滴下法により薄く形成
されることである。また第三の構成は、前記フラックス
供給工程が、前記フリップチップＩＣと前記基板との隙
間に対して、滴下法により毛管現象を利用して該隙間を
フラックスで満たすことである。また第四の構成は、前
記仮止め工程および前記リフロー工程が、レーザー加熱
の投入電力と時間調整で加熱温度を制御することであ
る。In order to solve the above-mentioned problems, a first structure of the present invention is a method for manufacturing a semiconductor device in which a flip-chip IC having a fine pitch is bump-soldered on a substrate, and the flip-chip IC A soldering step of forming a solder layer on the electrodes, and a flux thin film forming step of forming a soldering flux thin film thinner than a gap between the flip chip IC and the substrate on a portion where a chip is to be mounted on the substrate. , A temporary fixing step of arranging the flip chip IC on the substrate, temporarily heating it, and lightly bump soldering, and a sufficient distance between the temporarily fixed flip chip IC and the substrate after the temporary fixing step. It has a flux supply step of applying a flux sufficient to cover it and a reflow step of completely bump soldering the temporarily fixed flip chip IC. It is. The second configuration is that in the first configuration, the soldering flux thin film is formed thin by a printing technique, a dipping method, or a dropping method. A third configuration is that the flux supplying step fills the gap between the flip chip IC and the substrate with flux by using a capillary phenomenon by a dropping method. A fourth configuration is that the temporary fixing step and the reflow step control the heating temperature by adjusting the input power and time of laser heating.
【０００５】[0005]
【作用】バンプ半田付けされたフリップチップＩＣが位
置ずれしないよう基板に仮止めする仮止め工程を行う。
そのために仮止め工程においてフラックスを薄く塗布し
ておく。このフラックスの塗布はスクリーン印刷の手法
を利用したり、刷毛塗りなどで実施する。この仮止め形
成とすることでフリップチップＩＣの位置ずれを生じな
いで本格的なバンプ半田付けを実施できる。それでその
後に充分なフラックスを供給して、本格的な半田付けの
リフロー工程を実施する。仮加熱およびリフロー加熱は
レーザー加熱で実施すると温度制御が容易である。また
他部分の温度上昇を生じない。Operation: A temporary fixing process is performed to temporarily fix the flip-chip IC soldered to the bumps to the substrate so as not to be displaced.
Therefore, the flux is thinly applied in the temporary fixing step. The flux is applied by using a screen printing method or brush coating. By this temporary fixing formation, full-scale bump soldering can be carried out without causing displacement of the flip chip IC. Then, after that, a sufficient flux is supplied to perform a full-scale soldering reflow process. If the temporary heating and the reflow heating are performed by laser heating, temperature control is easy. Moreover, the temperature of other parts does not rise.
【０００６】[0006]
【発明の効果】仮止め工程でフリップチップＩＣが位置
ずれを生じることがなくなり、半田付けの信頼性も向上
し、製品の歩留りもよくなる。The flip chip IC is prevented from being displaced in the temporary fixing process, the reliability of soldering is improved, and the yield of products is improved.
【０００７】[0007]
【実施例】以下、本発明を具体的な実施例に基づいて説
明する。図１は本発明の製造工程の主要部分を示す工程
図であり、半導体装置の断面図を模式的に示している。
基板１の表面には、図示しない前工程で既に形成された
配線パターンの一部である半田付け予定部分の電極２が
形成されている。EXAMPLES The present invention will be described below based on specific examples. FIG. 1 is a process diagram showing a main part of a manufacturing process of the present invention, and schematically shows a cross-sectional view of a semiconductor device.
On the surface of the substrate 1, electrodes 2 to be soldered portions, which are a part of the wiring pattern already formed in the previous step (not shown), are formed.
【０００８】まず半田盛り工程で、従来より実施される
方法で、フリップチップＩＣ（以下ＩＣチップと記す）
４の電極部分に半田バンプ５を形成しておく。（図示し
ないが、図１(b) のＩＣチップ４は、半田バンプ５が形
成された状態を示す。）First, in a soldering step, a flip chip IC (hereinafter referred to as an IC chip) is formed by a method conventionally used.
The solder bumps 5 are formed on the electrode portions of 4. (Although not shown, the IC chip 4 of FIG. 1B shows a state in which the solder bumps 5 are formed.)
【０００９】フラックス薄膜形成工程では、基板の電極
２の部分にフラックスが薄く塗られる。この塗布厚さ
は、ＩＣチップ４が搭載された際に、半田バンプ５によ
って設けられたＩＣチップ４との隙間がフラックスによ
って埋まってしまわない程度の、およそ数１０μｍ程度
の膜厚であればよい（図１(a))。この薄膜の形成は刷毛
塗りでもディップによっても良く、ＩＣチップ４に接触
しなければどのような方法によっても良い。In the flux thin film forming step, the flux is thinly applied to the electrode 2 portion of the substrate. The coating thickness may be a film thickness of about several tens of μm so that when the IC chip 4 is mounted, the gap between the solder bumps 5 and the IC chip 4 is not filled with the flux. (Fig. 1 (a)). The thin film may be formed by brush coating or dipping, and may be formed by any method as long as it does not contact the IC chip 4.
【００１０】そして予め半田を盛ったＩＣチップ４を、
半田面と基板電極２とを向かい合わせて位置合わせし、
配置する。これはもちろん微細なＩＣに対する設置であ
るため、マウント治具により実施する。ＩＣチップ４は
フラックス３の粘着力により固定されるので、搬送中な
どにおいて図２のように移動することはない。Then, the IC chip 4 on which the solder is put in advance is
Position the solder side and the board electrode 2 facing each other,
Deploy. Since this is, of course, an installation on a fine IC, it is carried out by a mounting jig. Since the IC chip 4 is fixed by the adhesive force of the flux 3, it does not move during transportation or the like as shown in FIG.
【００１１】この状態で、仮止め工程において、ここで
はレーザー照射６により加熱を行う。レーザー加熱は従
来より各分野で実施利用される手法で、微細なスポット
加熱や瞬時加熱が実現できる便利な加熱方法である。こ
のレーザー光６を目的のＩＣチップ４上に照射してほぼ
瞬間的に加熱させてバンプ半田５を溶かし、基板電極２
と仮半田付けさせる。ここで、たとえフラックスの急激
な突沸が発生したとしても、チップとフラックスとの間
には隙間があるので、チップが突沸の泡によって移動さ
れることはない。ＩＣチップ４はシリコンであり、熱の
良導体であり熱分布も小さいので、レーザー照射は短時
間で済むが、ある程度の広がった面積をもつため、レー
ザー光６の照射条件は、例えば２３０℃、３秒である
（図１(c))。In this state, in the temporary fixing step, heating is performed here by laser irradiation 6. Laser heating is a method conventionally used in various fields and is a convenient heating method that can realize fine spot heating and instantaneous heating. The target IC chip 4 is irradiated with this laser light 6 and is heated almost instantaneously to melt the bump solder 5, and the substrate electrode 2
And tentatively solder it. Here, even if the sudden bumping of the flux occurs, there is a gap between the tip and the flux, so the tip is not moved by the bubbles of the bumping. Since the IC chip 4 is made of silicon, is a good conductor of heat and has a small heat distribution, the laser irradiation can be completed in a short time, but since the IC chip 4 has a certain expanded area, the irradiation condition of the laser light 6 is, for example, 230 ° C., 3 Seconds (Fig. 1 (c)).
【００１２】仮止め状態になったＩＣチップ４は、設定
した位置からずれるおそれは無くなる。そこでＩＣチッ
プ４を所定の半田形状に半田付けするために、フラック
スを充分に供給する。フラックスを滴下させると、基板
とＩＣとの隙間にフラックスが毛管現象により充填され
る。そのため内部の電極部にも十分のフラックスが供給
される。その適性量は、図１(d) に模式的に示すように
仮止めされたＩＣチップ４と基板１との隙間が完全に埋
まる程度の量である。ただし、ＩＣチップ４の上にフラ
ックスが多量に存在すると、半田付け温度に影響するの
でＩＣチップ上に付着しないことが望ましい。The IC chip 4 in the temporarily fixed state has no risk of being displaced from the set position. Therefore, in order to solder the IC chip 4 into a predetermined solder shape, sufficient flux is supplied. When the flux is dropped, the gap is filled with the flux by the capillarity. Therefore, sufficient flux is also supplied to the internal electrode portion. The appropriate amount is such that the gap between the temporarily fixed IC chip 4 and the substrate 1 is completely filled, as schematically shown in FIG. 1 (d). However, if a large amount of flux is present on the IC chip 4, it will affect the soldering temperature, so it is desirable that it does not adhere to the IC chip.
【００１３】そしてリフロー工程として、再びＩＣチッ
プ４をレーザー光で加熱してバンプ半田５が完全に溶け
て基板電極２と充分半田付けされるまで照射加熱する。
この場合のレーザー光６の照射条件は、例として２３０
℃、１０秒である（図１(e))。ここでも、たとえフラッ
クスが突沸しても、仮止め工程によりＩＣチップ４があ
る程度半田で基板電極に接合しているので移動してしま
うことはない。また、十分なフラックスが供給されてい
るので、リフロー半田付けの際にチップ自重で半田が潰
れてしまうこともなく、セルフアライメント性も向上す
る。Then, as a reflow process, the IC chip 4 is heated again by laser light to irradiate and heat the bump solder 5 until it is completely melted and soldered to the substrate electrode 2.
The irradiation condition of the laser beam 6 in this case is 230 as an example.
C. and 10 seconds (FIG. 1 (e)). Even in this case, even if the flux is bumped, the IC chip 4 does not move in the temporary fixing process because it is bonded to the substrate electrode by solder to some extent. Further, since sufficient flux is supplied, the solder is not crushed by the weight of the chip during reflow soldering, and the self-alignment property is improved.
【００１４】以上のように、本発明による半田付け方法
は、半田付けを実施する部分のみに加熱されるので、不
必要な熱が要らず経済的であり、また他の部品等を劣化
させる心配がない。そのため、ガラス基板上にＩＣを搭
載するＣＯＧ（Chip On Glas) などにおいて、本発明は
威力を発揮する。また、この製造手法を実施すること
で、近年要求される狭いピッチの電極を持つＩＣ部品を
精度よく実装でき、また、高い信頼性の接続部をもつ実
装部品を供給できる。As described above, since the soldering method according to the present invention heats only the portion to be soldered, unnecessary heat is not required and it is economical, and there is a risk of degrading other parts and the like. There is no. Therefore, the present invention is effective in COG (Chip On Glas) in which an IC is mounted on a glass substrate. Further, by implementing this manufacturing method, it is possible to accurately mount an IC component having electrodes with a narrow pitch, which is required in recent years, and to supply a mounted component having a highly reliable connection portion.
【図１】本発明の半導体装置の製造方法の実施例の主要
な工程図。FIG. 1 is a main process diagram of an embodiment of a method for manufacturing a semiconductor device of the present invention.
【図２】従来の工程に生じる、ＩＣのずれを示す説明
図。FIG. 2 is an explanatory diagram showing an IC shift that occurs in a conventional process.
１ 基板 ２ 電極 ３ フラックス ４ フリップチップＩＣ（ＩＣチップ） ５ 半田バンプ ６ レーザー光（レーザー照射加熱） 1 substrate 2 electrode 3 flux 4 flip chip IC (IC chip) 5 solder bump 6 laser light (laser irradiation heating)
Claims (4)
にバンプ半田付けする半導体装置の製造方法において、 前記フリップチップＩＣの電極に半田層を形成しておく
半田盛り工程と、 前記基板上のチップ実装予定部分に、前記フリップチッ
プＩＣと前記基板との隙間よりも薄い半田付け用フラッ
クス薄膜を形成するフラックス薄膜形成工程と、 該フリップチップＩＣを、該基板上に配置して仮加熱
し、軽くバンプ半田付けする仮止め工程と、 前記仮止め工程後に、仮止めされた前記フリップチップ
ＩＣと該基板との間を充分覆うだけのフラックスを付与
するフラックス供給工程と、 仮止めされた該フリップチップＩＣを完全にバンプ半田
付けするリフロー工程とを有することを特徴とする半導
体装置の製造方法。1. A method of manufacturing a semiconductor device in which a fine-pitch flip-chip IC is bump-soldered on a substrate, a soldering step of forming a solder layer on an electrode of the flip-chip IC, and a chip mounting on the substrate. A flux thin film forming step of forming a soldering flux thin film that is thinner than a gap between the flip chip IC and the substrate at a predetermined portion, the flip chip IC is placed on the substrate, temporarily heated, and lightly bumped. A temporary fixing step of soldering, a flux supplying step of applying a flux sufficient to cover between the temporarily fixed flip chip IC and the substrate after the temporary fixing step, and the temporarily fixed flip chip IC And a reflow step of completely bump-soldering the semiconductor.
形成されることを特徴とする請求項１に記載の半導体装
置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the soldering flux thin film is formed thin by a printing technique, a dipping method, or a dropping method.
法により毛管現象を利用して該隙間をフラックスで満た
すことを特徴とする請求項１に記載の半導体装置の製造
方法。3. The flux supplying step according to claim 1, wherein the gap between the flip chip IC and the substrate is filled with the flux by utilizing a capillary phenomenon by a dropping method. Manufacturing method of semiconductor device.
は、 レーザー加熱の投入電力と時間調整で加熱温度を制御す
ることを特徴とする請求項１に記載の半導体装置の製造
方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein in the temporary fixing step and the reflow step, the heating temperature is controlled by adjusting the input power and time of laser heating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24197993A JP3269211B2 (en) | 1993-09-01 | 1993-09-01 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24197993A JP3269211B2 (en) | 1993-09-01 | 1993-09-01 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0774209A true JPH0774209A (en) | 1995-03-17 |
| JP3269211B2 JP3269211B2 (en) | 2002-03-25 |
Family
ID=17082440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24197993A Expired - Lifetime JP3269211B2 (en) | 1993-09-01 | 1993-09-01 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3269211B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007266396A (en) * | 2006-03-29 | 2007-10-11 | Showa Denko Kk | Flip-chip type semiconductor light-emitting device, the flip-chip type semiconductor light-emitting device mounting method, flip-chip type semiconductor light-emitting device mounting structure, and light-emitting diode lamp |
| EP2671251A2 (en) * | 2011-02-02 | 2013-12-11 | Pac Tech - Packaging Technologies GmbH | Method and device for electrically contact-connecting connection areas of two substrates |
-
1993
- 1993-09-01 JP JP24197993A patent/JP3269211B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007266396A (en) * | 2006-03-29 | 2007-10-11 | Showa Denko Kk | Flip-chip type semiconductor light-emitting device, the flip-chip type semiconductor light-emitting device mounting method, flip-chip type semiconductor light-emitting device mounting structure, and light-emitting diode lamp |
| EP2671251A2 (en) * | 2011-02-02 | 2013-12-11 | Pac Tech - Packaging Technologies GmbH | Method and device for electrically contact-connecting connection areas of two substrates |
| CN103477424A (en) * | 2011-02-02 | 2013-12-25 | 派克泰克封装技术有限公司 | Method and device for the electrical bonding of connection areas of two substrates by laser soldering using a gaseous flux medium |
| JP2014506012A (en) * | 2011-02-02 | 2014-03-06 | パック テック−パッケージング テクノロジーズ ゲーエムベーハー | Method and apparatus for electrically contacting terminal surfaces of two substrates by laser soldering using a gas flux medium |
| US9649711B2 (en) | 2011-02-02 | 2017-05-16 | Pac Tech-Packaging Technologies Gmbh | Method and device for electrically contacting terminal faces of two substrates by laser soldering using a gaseous flux medium |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3269211B2 (en) | 2002-03-25 |
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