JPH0774066A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reject the propagation of dislocation within device structure formed by direct adhesion onto different kinds of substrates and suppress the dislocation on direct adhesion by placing a dislocation reduction region between a first semiconductor substrate and a second semiconductor substrate. CONSTITUTION:P-InGaAs etching stop layer 11, p<+>-InGaAsP layer 12, p-InP layer 13, undope InGaAsP activation layer 14, and n-InP layer 15 are allowed to grow successively on p-InP substrate 1. Then, InGaP single distortion layer 5 and n-InP layer 9 are allowed to grow successively. After that, the surfaces of n-GaAs substrate 2a and the n-InP layer 9 are washed, are subjected to HF treatment, rinsing, and drying and then washed surfaces face each other and a weight is placed on it before annealing. A miss-fit dislocation occurs at the adhesion interface between the n-GaAs substrate 2a and the n-InP layer 9 and laser is operation for a long time at a high temperature, thus achieving propagation into the n-InP layer 9. However, their propagation is rejected by the InGaP single distortion layer 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、格子定数の異なる異種
半導体基体を接着して構成される半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device formed by bonding different kinds of semiconductor substrates having different lattice constants.

【０００２】[0002]

【従来の技術】格子定数の異なる異種半導体を材料とす
る異種デバイスをモノリシックに集積できれば光電子集
積化素子等の新しい機能を持ったデバイスを生み出すこ
とが出来る。しかし、第一の半導体基板上に格子定数の
異なる第二の半導体層を結晶成長によって積層する場
合、基板と成長層の格子定数差及び熱膨張係数差によっ
て成長層内に転位等の欠陥が発生し、デバイスとしての
実用化が不可能となる。しかし近年、アプライド フィ
ジックス レターズ（Applied Physics Letters)、５８
１９６１（１９９１)）に記載のように、ＩｎＰとＧａ
Ａｓのような格子定数差の大きい半導体を高温・加圧下
で直接接着することにより、集積化素子の実用化を可能
とすると思われる半導体装置が得られることが示され
た。この場合にも、接着界面ではＩｎＰとＧａＡｓの格
子定数差及び熱膨張係数差を緩和するために転位が発生
するが、その量は少なく、またそれらの転位は成長層中
には貫通しにくい性質を持ち、デバイス特性に与える影
響が小さいとみられる。2. Description of the Related Art If heterogeneous devices made of different semiconductors having different lattice constants can be monolithically integrated, a device having a new function such as an optoelectronic integrated device can be produced. However, when a second semiconductor layer having a different lattice constant is stacked on the first semiconductor substrate by crystal growth, defects such as dislocations occur in the growth layer due to the difference in the lattice constant and the thermal expansion coefficient between the substrate and the growth layer. However, practical application as a device becomes impossible. However, in recent years, Applied Physics Letters, 58
1961 (1991)) as described in InP and Ga.
It has been shown that by directly bonding a semiconductor such as As having a large difference in lattice constant under high temperature and pressure, a semiconductor device that is considered to be able to be put into practical use as an integrated device can be obtained. Also in this case, dislocations are generated at the bonding interface to relax the difference in lattice constant and the difference in thermal expansion coefficient between InP and GaAs, but the amount thereof is small and the dislocations are unlikely to penetrate into the growth layer. It seems that the effect on device characteristics is small.

【０００３】また、更にアプライド フィジックス レ
ターズ(Applied Physics Letters)、６２ １０３８（１
９９３)）に記載のように、接着を行う基板の間に中間
層を形成し、接着強度や界面の電気的特性を向上させよ
うとする試みも報告されている。In addition, Applied Physics Letters, 62 1038 (1)
993)), an attempt has been made to form an intermediate layer between substrates to be bonded to improve the bonding strength and the electrical characteristics of the interface.

【０００４】[0004]

【発明が解決しようとする課題】しかし、上記のような
性質の転位であっても、素子作製プロセス中の高温過程
を経た場合、及びデバイスを高温動作等の過酷な条件下
で動作した場合、構造中のそれらの転位が成長層中に伝
播しデバイス特性に悪影響を与える可能性が有る。また
中間層を形成する場合も、適切な材料を選ばなければ逆
に転位発生の増加につながる恐れがある。However, even with the dislocations having the above-mentioned properties, when the device undergoes a high temperature process during the device manufacturing process and the device is operated under severe conditions such as high temperature operation, These dislocations in the structure can propagate into the growth layer and adversely affect device properties. Further, also in the case of forming the intermediate layer, if appropriate materials are not selected, there is a possibility that the generation of dislocations may increase.

【０００５】本発明の目的は、異種基板上に直接接着に
よって形成されるデバイス構造中における転位の伝播を
阻止すること、および直接接着時の転位の発生を抑制す
ることにある。An object of the present invention is to prevent the propagation of dislocations in a device structure formed by direct bonding on a foreign substrate and to suppress the generation of dislocations during direct bonding.

【０００６】[0006]

【課題を解決するための手段】上記目的は、接着を行う
二種の半導体基板の間に、転位低減領域を形成する第一
の手段、あるいは基板間の物性差を緩和する緩和層を形
成する第二の手段によって達成される。The above object is to provide a first means for forming a dislocation reduction region, or a relaxing layer for relaxing a difference in physical properties between substrates, between two kinds of semiconductor substrates to be bonded. It is achieved by the second means.

【０００７】[0007]

【作用】本発明の第一の手段によれば、第一の半導体基
板上に、必要ならばデバイス構造を形成した後、転位低
減領域を形成する。その表面に第二の半導体基板を直接
接着する。この時、転位低減領域と第二の半導体基板と
の接着界面でミスフィット転位が発生する。この接着さ
れた構造を用いてデバイスを作製した場合、デバイスを
特に高温動作等の過酷な条件で動作すると、従来の接着
方法では界面のミスフィット転位がデバイス構造内に伝
播してしまう。しかし、本発明では転位低減領域が転位
の伝播を阻止し、デバイスの動作特性に影響しない。According to the first means of the present invention, the dislocation reduction region is formed on the first semiconductor substrate after forming the device structure if necessary. The second semiconductor substrate is directly adhered to the surface. At this time, misfit dislocations occur at the bonding interface between the dislocation reduction region and the second semiconductor substrate. When a device is manufactured using this bonded structure, if the device is operated under severe conditions such as high temperature operation, misfit dislocations at the interface will propagate into the device structure by the conventional bonding method. However, in the present invention, the dislocation reduction region blocks the propagation of dislocations and does not affect the operating characteristics of the device.

【０００８】また本発明の第二の手段によれば、第一の
半導体基板上に、必要ならばデバイス構造を形成した
後、第三の半導体層を形成する。その表面に第二の半導
体基板を直接接着する。この第三の半導体は第一の半導
体基板と第二の半導体基板の物性差を緩和するために形
成され、例えば、第一の半導体基板および第二の半導体
基板より熱膨張係数が大きい特徴を持つ。この第三の半
導体層によって、直接接着後第一の半導体基板と第二の
半導体基板の間に双方の物性差によって生じる応力が緩
和され、接着界面でのミスフィット転位の発生が抑えら
れる。According to the second means of the present invention, a third semiconductor layer is formed on the first semiconductor substrate after forming a device structure if necessary. The second semiconductor substrate is directly adhered to the surface. The third semiconductor is formed to reduce the difference in physical properties between the first semiconductor substrate and the second semiconductor substrate, and has a characteristic that the coefficient of thermal expansion is larger than those of the first semiconductor substrate and the second semiconductor substrate, for example. . The third semiconductor layer alleviates the stress caused by the physical property difference between the first semiconductor substrate and the second semiconductor substrate after direct bonding, and suppresses the occurrence of misfit dislocations at the bonding interface.

【０００９】[0009]

【実施例】（実施例１）以下、本発明の一実施例を図１
により説明する。(Embodiment 1) An embodiment of the present invention will be described below with reference to FIG.
Will be described.

【００１０】有機金属気相成長（ＭＯＣＶＤ）法によ
り、図１(ａ)に示すようにｐ−ＩｎＰ基板１上にｐ−Ｉ
ｎＧａＡｓエッチングストップ層１１(厚さ０.３μ
ｍ)，ｐ+−ＩｎＧａＡｓＰ層１２（厚さ０.３μｍ），
ｐ−ＩｎＰ層１３(厚さ１.５μｍ)，アンドープＩｎＧ
ａＡｓＰ活性層１４(波長１.５５μｍ），ｎ−ＩｎＰ層
１５（厚さ２.０μｍ)を順次成長する。ＩｎＰ層１３お
よび１５はクラッド層として機能し、ｐ+−ＩｎＧａＡ
ｓＰ 層１２はオーミックコンタクトを得るための層
で、これらとＩｎＧａＡｓＰ活性層１４は長波長帯レー
ザ構造を成すためのものである。引き続きＩｎＧａＰ単
一歪層５，ｎ−ＩｎＰ層９(厚さ２.０μｍ）を順次成長
する。単一歪層５の組成はＩｎ_0.9Ｇａ_0.1Ｐとし、厚み
は臨界膜厚以下の１０ｎｍとした。As shown in FIG. 1A, p-I is formed on the p-InP substrate 1 by the metal organic chemical vapor deposition (MOCVD) method.
nGaAs etching stop layer 11 (thickness 0.3 μm
m), p + -InGaAsP layer 12 (thickness 0.3 μm),
p-InP layer 13 (thickness: 1.5 μm), undoped InG
An aAsP active layer 14 (wavelength 1.55 μm) and an n-InP layer 15 (thickness 2.0 μm) are sequentially grown. The InP layers 13 and 15 function as a cladding layer, and p + -InGaA
The sP layer 12 is a layer for obtaining an ohmic contact, and these and the InGaAsP active layer 14 are for forming a long wavelength band laser structure. Subsequently, the InGaP single strain layer 5 and the n-InP layer 9 (thickness 2.0 μm) are sequentially grown. The composition of the single strained layer 5 was In _0.9 Ga _0.1 P, and the thickness was 10 nm, which is less than the critical film thickness.

【００１１】この後、ｎ−ＧａＡｓ基板２ａとｎ−Ｉｎ
Ｐ層９の表面を硫酸と過酸化水素の混合溶液で洗浄し、
更に、ＨＦ希釈液で処理した後、水洗してスピンナ乾燥
する。これらを洗浄した面を向かい合わせて重ね、４０
ｇ／cm² 程度の重しをしてアニール炉内に置く。この
時、ｎ−ＧａＡs基板２ａおよびｐ−ＩnＰ基板１のどち
らが上でもよい。炉内にＨ₂ ガスを流しながら温度を４
５０℃に昇温し、３０分保持する。こうして図１(ｂ)に
示すように、ｎ−ＧａＡｓ基板２ａとｐ−ＩｎＰ基板１
が接着される。接着後、ｐ−ＩｎＰ基板１を塩酸でエッ
チング除去し、更に、ｐ−ＩｎＧａＡｓ層１１を硫酸と
過酸化水素の混合溶液でエッチング除去した。その後、
通常の半導体レーザ作製プロセスを経て電極等を形成
し、レーザを作製した。After that, the n-GaAs substrate 2a and the n-In
The surface of the P layer 9 is washed with a mixed solution of sulfuric acid and hydrogen peroxide,
Further, after being treated with an HF diluting solution, it is washed with water and spinner dried. Lay these washed surfaces face to face and place
Place a weight of about g / cm ² in the annealing furnace. At this time, either the n-GaAs substrate 2a or the p-InP substrate 1 may be on top. The temperature is set to 4 while flowing H ₂ gas into the furnace.
The temperature is raised to 50 ° C. and kept for 30 minutes. Thus, as shown in FIG. 1B, the n-GaAs substrate 2a and the p-InP substrate 1 are
Are glued together. After the adhesion, the p-InP substrate 1 was removed by etching with hydrochloric acid, and the p-InGaAs layer 11 was further removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. afterwards,
Electrodes and the like were formed through a normal semiconductor laser manufacturing process to manufacture a laser.

【００１２】本実施例によれば、ｎ−ＧａＡｓ基板２ａ
とｎ−ＩｎＰ層９の接着界面ではミスフィット転位が発
生し、レーザを高温で長時間動作させるとｎ−ＩｎＰ層
９中へ伝播する。しかしそれらはＩｎＧａＰ単一歪層５
によって伝播を阻止され、レーザ構造中にほとんど到達
しない。従って大部分のレーザの特性は劣化することは
なかった。According to this embodiment, the n-GaAs substrate 2a is used.
Misfit dislocations are generated at the bonding interface between the n-InP layer 9 and the n-InP layer 9, and propagate into the n-InP layer 9 when the laser is operated at high temperature for a long time. However, they are InGaP single strained layer 5
Is prevented from propagating by and almost never reaches the laser structure. Therefore, the characteristics of most lasers did not deteriorate.

【００１３】一方、図１０に示す従来例では、単一歪層
がないためレーザを高温で連続発振させるとミスフィッ
ト転位がレーザ構造中へ伝播し、駆動電流が増加し動作
しなくなるチップが多くあった。即ち、ＩｎＧａＰ単一
歪層によってデバイスを過酷な条件下で動作させた時の
劣化が抑制された。On the other hand, in the conventional example shown in FIG. 10, since there is no single strain layer, when the laser is continuously oscillated at a high temperature, misfit dislocations propagate into the laser structure and the driving current increases, so that many chips do not operate. there were. That is, the InGaP single strained layer suppressed the deterioration when the device was operated under severe conditions.

【００１４】本実施例はＩｎＧａＰ単一歪層を用いた
が、同様の効果をもたらすものであれば他の材料による
単一歪層を用いてもよい。ＩｎＧａＰ単一歪層の組成と
膜厚は、ＩｎＰ層に対して適当な歪応力を生じ、且つ臨
界膜厚以内であればこれに限らない。また、本実施例は
長波長レーザを作製する場合について示したが、種々の
デバイスを作製する全ての場合について本発明の適用が
可能であり、デバイス構造を接着後に形成してもよい。
更に、本実施例はＧａＡｓ基板とＩｎＰ基板を接着する
例のみ示したが、他の二種の基板を接着する場合につい
ても適当な単一歪層を用いることにより本発明の適用が
可能であり、接着方法も本実施例に限らない。Although the InGaP single strained layer is used in this embodiment, a single strained layer made of another material may be used as long as the same effect can be obtained. The composition and film thickness of the InGaP single strained layer are not limited to these as long as they generate an appropriate strain stress on the InP layer and are within the critical film thickness. Further, although the present embodiment shows the case of manufacturing a long wavelength laser, the present invention can be applied to all cases of manufacturing various devices, and the device structure may be formed after bonding.
Further, although the present embodiment shows only an example in which a GaAs substrate and an InP substrate are bonded together, the present invention can be applied to the case where other two types of substrates are bonded together by using an appropriate single strain layer. The bonding method is not limited to this embodiment.

【００１５】（実施例２）以下、本発明の第二の実施例
を図２により説明する。(Second Embodiment) A second embodiment of the present invention will be described below with reference to FIG.

【００１６】基本的な接着方法および層構造は実施例１
と同様であるが、本実施例ではＩｎＧａＰ単一歪層５と
ｎ−ＩｎＰ層９の間に更にｎ−ＩｎＰ層６ａ(厚さ０.５
μｍ)，ＩｎＧａＰ単一歪層７，ｎ−ＩｎＰ層６ｂ(厚さ
０.５μｍ)，ＩｎＧａＰ単一歪層８を成長した。単一歪
層７および８の組成および膜厚は単一歪層５と同じとし
た。The basic bonding method and layer structure are described in Example 1.
However, in this embodiment, an n-InP layer 6a (having a thickness of 0.5) is further provided between the InGaP single strain layer 5 and the n-InP layer 9.
.mu.m), InGaP single strained layer 7, n-InP layer 6b (thickness 0.5 .mu.m), and InGaP single strained layer 8 were grown. The composition and film thickness of the single strained layers 7 and 8 were the same as those of the single strained layer 5.

【００１７】本実施例によると、ＩｎＧａＰ単一歪層を
三層に増やすことにより、より確実に転位の伝播が阻止
された。従って過酷な条件下での動作による劣化が更に
抑制された。According to the present embodiment, by increasing the InGaP single strained layer to three layers, dislocation propagation was prevented more reliably. Therefore, the deterioration due to the operation under severe conditions was further suppressed.

【００１８】本実施例では単一歪層の組成および膜厚は
全て同じとしたが、前述の歪応力と臨界膜厚の関係を満
たせばそれぞれ他の異なる組成，膜厚、および材料を用
いてもよい。また単一歪層の導入回数はこれに限らな
い。In this embodiment, the composition and the film thickness of the single strained layer are all the same, but if the above-mentioned relationship between the strain stress and the critical film thickness is satisfied, another different composition, film thickness and material are used. Good. The number of times the single strained layer is introduced is not limited to this.

【００１９】（実施例３）以下、本発明の第三の実施例
を図３により説明する。(Embodiment 3) A third embodiment of the present invention will be described below with reference to FIG.

【００２０】基本的な接着方法および層構造は実施例２
と同様であるが、本実施例ではＩｎＧａＰ歪層５〜８の
代りに歪超格子層５１〜８１を形成した。歪超格子層５
１〜８１はＩｎ_0.9Ｇａ_0.1Ｐ層（５０Å）とＩｎＰ層
（５０Å）の三周期で構成した。このように歪超格子層
を形成した場合でも実施例２と同様の効果が得られた。The basic bonding method and layer structure are described in Example 2.
However, in this example, strained superlattice layers 51 to 81 were formed in place of the InGaP strained layers 5 to 8. Strained superlattice layer 5
1 to 81 are composed of three cycles of an In _0.9 Ga _0.1 P layer (50 Å) and an InP layer (50 Å). Even when the strained superlattice layer was formed in this way, the same effect as in Example 2 was obtained.

【００２１】本実施例では歪超格子層は全て同じ層構造
を持つものとしたが、新たな転位を発生するものでなけ
れば、それぞれ他の異なる層構造を持った歪超格子を用
いてもよい。In this embodiment, all strained superlattice layers have the same layer structure. However, strained superlattices having different layer structures may be used as long as new dislocations are not generated. Good.

【００２２】（実施例４）以下、本発明の第四の実施例
を図４により説明する。(Fourth Embodiment) A fourth embodiment of the present invention will be described below with reference to FIG.

【００２３】ＭＯＣＶＤ法により、図４(ａ)に示すよう
にｐ−ＩｎＰ基板１上にｐ−InGaAsエッチングストップ
層１１，ｐ+−ＩｎＧａＡｓＰ層１２，ｐ−ＩｎＰ層１
３，アンドープＩｎＧａＡｓＰ活性層１４，ｎ−ＩｎＰ
層１５、およびｎ−ＧａＳｂ層１０ｘ（厚さ１００Å）
を順次成長する。この後、ｎ−ＧａＳｂ層１０ｘの表面
を実施例１と同様の方法で洗浄し、ｎ−Ｓｉ基板３をＨ
Ｆ希釈液で処理した後水洗してスピンナ乾燥する。これ
らを洗浄した面を向かい合わせて重ね、第一の実施例と
同様の方法で接着する。こうして図４(ｂ)に示すよう
に、ｎ−Ｓｉ基板３とｐ−ＩｎＰ基板１がｎ−ＧａＳｂ
層１０ｘを介して接着された構造が得られる。ここで、
ＧａＳｂはＳｉおよびＩｎＰより熱膨張係数が大きいた
め、ｎ−Ｓｉ基板３とｎ−ＧａＳｂ層１０ｘの界面では
引っ張り応力が、ｎ−ＧａＳｂ層１０ｘとｎ−ＩｎＰ層
１５の界面では圧縮応力がかかる。このように引っ張り
と圧縮両方向の応力が生じることによって、ｎ−Ｓｉ基
板３とｐ−ＩｎＰ基板１の間の格子定数差等の物性差が
緩和される。また、ＧａＳｂは弾性定数が小さく変形し
やすいため、ｎ−Ｓｉ基板３とｐ−ＩｎＰ基板１の間の
物性差を吸収する効果も生じ、この結果、ミスフィット
転位の発生が抑えられ、更に接着界面にかかる歪の量が
低減される。接着後、ｐ−ＩｎＰ基板１を塩酸でエッチ
ング除去し、更にｐ−ＩｎＧａＡｓ層１１を硫酸と過酸
化水素の混合溶液でエッチング除去した。その後、通常
の半導体レーザ作製プロセスを経て電極等を形成し、長
波長レーザを作製した。As shown in FIG. 4A, the p-InGaAs etching stop layer 11, the p + -InGaAsP layer 12, and the p-InP layer 1 are formed on the p-InP substrate 1 by the MOCVD method.
3, undoped InGaAsP active layer 14, n-InP
Layer 15 and n-GaSb layer 10x (thickness 100Å)
To grow sequentially. After that, the surface of the n-GaSb layer 10x is washed by the same method as in Example 1, and the n-Si substrate 3 is exposed to H.
After treatment with the F diluent, washing with water and spinner drying. These washed surfaces are faced to each other and stacked, and bonded in the same manner as in the first embodiment. Thus, as shown in FIG. 4B, the n-Si substrate 3 and the p-InP substrate 1 are n-GaSb.
A structure is obtained which is bonded via the layer 10x. here,
Since GaSb has a larger thermal expansion coefficient than Si and InP, tensile stress is applied to the interface between the n-Si substrate 3 and the n-GaSb layer 10x, and compressive stress is applied to the interface between the n-GaSb layer 10x and the n-InP layer 15. The tensile and compressive stresses thus generated alleviate the physical property difference such as the lattice constant difference between the n-Si substrate 3 and the p-InP substrate 1. Further, since GaSb has a small elastic constant and is easily deformed, it also has an effect of absorbing a physical property difference between the n-Si substrate 3 and the p-InP substrate 1. As a result, the occurrence of misfit dislocations is suppressed, and further adhesion The amount of strain on the interface is reduced. After the adhesion, the p-InP substrate 1 was removed by etching with hydrochloric acid, and the p-InGaAs layer 11 was removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. Then, electrodes and the like were formed through a normal semiconductor laser manufacturing process to manufacture a long wavelength laser.

【００２４】本実施例によれば、ＧａＳｂ層１０ｘによ
り接着界面でのミスフィット転位の発生が抑制され、ま
た界面の歪の量が低減されるため、レーザを高温で長時
間動作させても新たにミスフィット転位が発生すること
もなく、特性は全く劣化しなかった。即ち、図１１に示
す従来例と比べて、ＧａＳｂ層１０ｘによってデバイス
を過酷な条件下で動作させた時の劣化が抑制された。According to the present embodiment, the GaSb layer 10x suppresses the occurrence of misfit dislocations at the adhesive interface and reduces the amount of strain at the interface. Therefore, even if the laser is operated at high temperature for a long period of time, No misfit dislocations were generated and the characteristics were not deteriorated at all. That is, as compared with the conventional example shown in FIG. 11, the GaSb layer 10x suppressed deterioration when the device was operated under severe conditions.

【００２５】本実施例は、長波長レーザを作製する場合
について示したが、種々のデバイスを作製する全ての場
合について本発明の適用が可能であり、デバイス構造を
接着後に形成してもよい。また、本実施例はＳｉ基板と
ＩｎＰ基板を接着する例のみ示したが、他の二種の基板
を接着する場合についても適当な熱膨張係数を持つ材料
を介することにより本発明の適用が可能であり、接着方
法も本実施例に限らない。Although the present embodiment shows the case of producing a long wavelength laser, the present invention can be applied to all cases of producing various devices, and the device structure may be formed after bonding. Further, this embodiment shows only an example of adhering the Si substrate and the InP substrate, but the present invention can be applied to the case of adhering two other types of substrates by interposing a material having an appropriate thermal expansion coefficient. Therefore, the bonding method is not limited to this embodiment.

【００２６】（実施例５）以下、本発明の第五の実施例
を図５により説明する。(Fifth Embodiment) A fifth embodiment of the present invention will be described below with reference to FIG.

【００２７】ＭＯＣＶＤ法により、図５(ａ)に示すよう
にｐ−ＧａＡｓ基板２ｂ上にｐ−ＩｎＧａＰエッチング
ストップ層２１（厚さ０.３μｍ），ｐ+−ＧａＡｓ層２
２（厚さ０.３μｍ），ｐ−ＡｌＧａＡｓ層２３（厚さ
１.０μｍ），アンドープＭＱＷ（Ｍulti-Ｑuantum Wel
l）活性層２４，ｎ−ＡｌＧａＡｓ層２５（厚さ１.０μ
ｍ），ｎ−ＧａＡｓ層２６（厚さ１.０μｍ）を順次成
長する。ＭＱＷとは組成の異なる二種の半導体薄膜を交
互に積層したもので、例えば、ＧａＡｓ（７ｎｍ）とＡ
ｌ_0.2Ｇａ_0.8Ａｓ（５ｎｍ）の四周期で構成すると発振
波長は８３０ｎｍとなり、Ａｌ_0.1Ｇａ_0.9Ａｓ(８ｎｍ)
とＡｌ_0.3Ｇａ_0.7Ａｓ(５ｎｍ)の四周期で構成すると発
振波長７８０ｎｍの活性層が得られる。本実施例ではＭ
ＱＷは波長８３０ｎｍの構造とした。また、ＡｌＧａＡ
ｓ層２３および２５はクラッド層として機能し、ｐ+−
ＧａＡｓ 層２２はオーミックコンタクトを得るための
もので、これらとＭＱＷ活性層２４は短波長帯レーザ構
造を成すためのものである。By the MOCVD method, as shown in FIG. 5A, the p-InGaP etching stop layer 21 (thickness 0.3 μm) and the p + -GaAs layer 2 are formed on the p-GaAs substrate 2b.
2 (thickness 0.3 μm), p-AlGaAs layer 23 (thickness 1.0 μm), undoped MQW (Multi-Quantum Wel)
l) Active layer 24, n-AlGaAs layer 25 (thickness 1.0 μm
m) and an n-GaAs layer 26 (thickness 1.0 μm) are sequentially grown. MQW is a stack of two types of semiconductor thin films having different compositions, and is composed of, for example, GaAs (7 nm) and A
When it is composed of four periods of _0.2 Ga _0.8 As (5 nm), the oscillation wavelength is 830 nm, and Al _0.1 Ga _0.9 As (8 nm)
And Al _0.3 Ga _0.7 As (5 nm) for four periods, an active layer with an oscillation wavelength of 780 nm is obtained. In this embodiment, M
The QW has a structure with a wavelength of 830 nm. In addition, AlGaA
The s layers 23 and 25 function as cladding layers, and p +-
The GaAs layer 22 is for obtaining ohmic contact, and these and the MQW active layer 24 are for forming a short wavelength band laser structure.

【００２８】一方、ＭＯＣＶＤ法により、ｎ−ＧａＰ基
板４上にｎ−ＩｎＰ層１０ｙ（厚さ３００Å）を成長す
る。この後、ｎ−ＧａＡｓ層２６の表面とｎ−ＩｎＰ層
10ｙの表面を実施例１と同様の方法で洗浄する。これら
を洗浄した面を向かい合わせて重ね、実施例１と同様の
方法で接着する。On the other hand, the n-InP layer 10y (thickness 300Å) is grown on the n-GaP substrate 4 by the MOCVD method. After that, the surface of the n-GaAs layer 26 and the n-InP layer
The surface of 10y is washed in the same manner as in Example 1. These washed surfaces are faced to each other and stacked, and bonded in the same manner as in Example 1.

【００２９】こうして図５(ｂ)に示すように、ｎ−Ｇａ
Ｐ基板４とｐ−ＧａＡｓ基板２ｂがｎ−ＩｎＰ層１０ｙ
を介して接着された構造が得られる。ここで、ＩnＰは
ＧaＰおよびＧａＡｓより熱膨張係数が小さいため、ｎ
−ＧａＰ基板４とｎ−ＩｎＰ層１０ｘの界面では圧縮応
力が、ｎ−ＩｎＰ層１０ｙとｎ−ＧａＡｓ層２６の界面
では引っ張り応力がかかる。このように引っ張りと圧縮
両方向の応力が生じることによって、ｎ−ＧａＰ基板４
とｐ−ＧａＡｓ基板２ｂの間の格子定数差等の物性差が
緩和される。その結果、界面でのミスフィット転位の発
生が抑えられ、更にｎ−ＧａＰ基板４およびｐ−ＧａＡ
ｓ基板２ｂにかかる歪の量が低減される。Thus, as shown in FIG. 5B, n-Ga
The P substrate 4 and the p-GaAs substrate 2b are the n-InP layer 10y.
A structure adhered via is obtained. Since InP has a smaller coefficient of thermal expansion than GaP and GaAs, n
Compressive stress is applied at the interface between the -GaP substrate 4 and the n-InP layer 10x, and tensile stress is applied at the interface between the n-InP layer 10y and the n-GaAs layer 26. The tensile and compressive stresses are generated in this way, so that the n-GaP substrate 4 is
The difference in the physical properties such as the difference in lattice constant between the p-type GaAs substrate 2b and the p-GaAs substrate 2b is reduced. As a result, the occurrence of misfit dislocations at the interface is suppressed, and the n-GaP substrate 4 and p-GaA are further suppressed.
The amount of strain applied to the s substrate 2b is reduced.

【００３０】接着後、ｐ−ＧａＡｓ基板２ｂを硫酸と過
酸化水素の混合溶液でエッチング除去し、更にｐ−Ｉｎ
ＧａＰ層２１を塩酸でエッチング除去した。その後、通
常の半導体レーザ作製プロセスを経て電極等を形成し、
レーザを作製した。After the adhesion, the p-GaAs substrate 2b is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and p-In is further added.
The GaP layer 21 was removed by etching with hydrochloric acid. After that, electrodes etc. are formed through a normal semiconductor laser manufacturing process,
A laser was produced.

【００３１】本実施例の様に、第四実施例とは逆に熱膨
張係数の小さい材料を介して接着した場合でも、ｎ−Ｉ
ｎＰ層１０ｙを形成しないで接着した従来の例と比べて
信頼性が向上する効果が得られた。もちろん作製するデ
バイスの種類や接着方法，接着する基板の種類等は本実
施例に限らず、他の二種の基板を接着する場合にも適当
な熱膨張係数を持つ材料を介することにより本発明の適
用が可能である。As in the case of this embodiment, even if the material is adhered through a material having a small coefficient of thermal expansion, contrary to the fourth embodiment, n-I
The reliability was improved compared to the conventional example in which the nP layer 10y was adhered without being formed. Of course, the types of devices to be manufactured, the bonding method, the types of substrates to be bonded, etc. are not limited to those in the present embodiment, and the present invention can be applied to other two types of substrates by interposing a material having an appropriate thermal expansion coefficient. Can be applied.

【００３２】（実施例６）本発明の第六の実施例を図６
により説明する。(Embodiment 6) A sixth embodiment of the present invention is shown in FIG.
Will be described.

【００３３】ＭＯＣＶＤ法により、図６(ａ)に示すよう
にｐ−ＧａＡｓ基板２ｂ上にｐ−ＩｎＧａＰエッチング
ストップ層２１，ｐ+−ＧａＡｓ層２２，ｐ−ＡｌＧａ
Ａs層２３，アンドープＭＱＷ活性層２４，ｎ−ＡｌＧ
ａＡｓ層２５，ｎ−ＧａＡｓ層２６を順次成長する。一
方、分子線エピタキシ(ＭＢＥ)法により、ｎ−Ｓｉ基板
３上にｎ−ＧａＮ層１０ｚ(厚さ２００Å)を成長する。
この後、ｎ−ＧａＡｓ層２６の表面とｎ−ＧａＮ層１０
ｚの表面を第一実施例と同様の方法で洗浄する。これら
を洗浄した面を向かい合わせて重ね、第一実施例と同様
の方法で接着する。こうして図６(ｂ)に示すように、ｎ
−Ｓｉ基板３とｐ−ＧａＡｓ基板２ｂがｎ−ＧａＮ層１
０ｚを介して接着された構造が得られる。ここで、Ｇａ
ＮはＳｉおよびＧａＡｓより格子定数が小さいため、ｎ
−Ｓｉ基板３とｎ−ＧａＮ層10ｚの界面では引っ張り応
力が、ｎ−ＧａＮ層１０ｚとｎ−ＧａＡｓ層２６の界面
では圧縮応力がかかる。このように引っ張りと圧縮両方
向の応力が生じることによって、ｎ−Ｓｉ基板３とｐ−
ＧａＡｓ基板２ｂの間の格子定数差等の物性差が緩和さ
れる。その結果、界面でのミスフィット転位の発生が抑
えられ、更にｎ−Ｓｉ基板３およびｐ−ＧａＡｓ基板２
ｂにかかる歪の量が低減される。By the MOCVD method, as shown in FIG. 6A, the p-InGaP etching stop layer 21, the p + -GaAs layer 22, and the p-AlGa are formed on the p-GaAs substrate 2b.
As layer 23, undoped MQW active layer 24, n-AlG
The aAs layer 25 and the n-GaAs layer 26 are sequentially grown. On the other hand, the n-GaN layer 10z (thickness 200Å) is grown on the n-Si substrate 3 by the molecular beam epitaxy (MBE) method.
After this, the surface of the n-GaAs layer 26 and the n-GaN layer 10
The surface of z is cleaned in the same manner as in the first embodiment. These cleaned surfaces are faced to each other and overlapped, and they are adhered in the same manner as in the first embodiment. Thus, as shown in FIG. 6B, n
-Si substrate 3 and p-GaAs substrate 2b are n-GaN layers 1
A structure bonded via 0z is obtained. Where Ga
Since N has a smaller lattice constant than Si and GaAs, n
A tensile stress is applied at the interface between the -Si substrate 3 and the n-GaN layer 10z, and a compressive stress is applied at the interface between the n-GaN layer 10z and the n-GaAs layer 26. As a result of the tensile stress and the compressive stress in both directions, the n-Si substrate 3 and the p-
Differences in physical properties such as a lattice constant difference between the GaAs substrates 2b are alleviated. As a result, the occurrence of misfit dislocations at the interface is suppressed, and the n-Si substrate 3 and the p-GaAs substrate 2 are further suppressed.
The amount of strain on b is reduced.

【００３４】接着後、ｐ−ＧａＡｓ基板２ｂを硫酸と過
酸化水素の混合溶液でエッチング除去し、更にｐ−Ｉｎ
ＧａＰ層２１を塩酸でエッチング除去した。その後、通
常の半導体レーザ作製プロセスを経て電極等を形成し、
短波長レーザを作製した。After the adhesion, the p-GaAs substrate 2b is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and p-In is further added.
The GaP layer 21 was removed by etching with hydrochloric acid. After that, electrodes etc. are formed through a normal semiconductor laser manufacturing process,
A short wavelength laser was produced.

【００３５】本実施例の様に、格子定数の小さい材料を
介して接着した場合でも、第四および第五実施例に記載
の場合と同様に、ｎ−ＧａＮ層１０ｚを形成しないで接
着した従来の例と比べて信頼性が向上する効果が得られ
た。もちろん作製するデバイスの種類や接着方法，接着
する基板の種類等は本実施例に限らず、他の二種の基板
を接着する場合についても適当な格子定数を持つ材料を
介することにより本発明の適用が可能である。Even when bonding is performed through a material having a small lattice constant as in this embodiment, as in the cases described in the fourth and fifth embodiments, the conventional bonding without forming the n-GaN layer 10z is performed. The effect of improving reliability was obtained as compared with the example. Of course, the types of devices to be manufactured, the bonding method, the types of substrates to be bonded, etc. are not limited to those in the present embodiment, and also in the case of bonding other two types of substrates, the material of the present invention can be used by interposing a material having an appropriate lattice constant. Applicable.

【００３６】（実施例７）本発明の第七の実施例を同様
に図７により説明する。(Embodiment 7) A seventh embodiment of the present invention will be described with reference to FIG.

【００３７】ＭＯＣＶＤ法により、図７(ａ)に示すよう
にｐ−ＩｎＰ基板１上にｐ−InGaAsエッチングストップ
層１１，ｐ+−ＩｎＧａＡｓＰ 層１２，ｐ−ＩｎＰ層１
３，アンドープＩｎＧａＡｓＰ活性層１４，ｎ−ＩｎＰ
層１５，ＩｎＧａＰ単一歪層５，ｎ−ＩｎＰ層６ａ，Ｉ
ｎＧａＰ単一歪層７，ｎ−ＩｎＰ層６ｂ，ＩｎＧａＰ単
一歪層８，ｎ−ＩｎＰ層９、およびｎ−ＧａＳｂ層１０
ｘを順次成長する。この後、ｎ−ＧａＳｂ層１０ｘの表
面を第一実施例と同様の方法で洗浄し、ｎ−Ｓｉ基板３
をＨＦ希釈液で処理した後水洗してスピンナ乾燥する。As shown in FIG. 7A, the p-InGaAs etching stop layer 11, the p + -InGaAsP layer 12, and the p-InP layer 1 are formed on the p-InP substrate 1 by the MOCVD method.
3, undoped InGaAsP active layer 14, n-InP
Layer 15, InGaP single strained layer 5, n-InP layer 6a, I
nGaP single strain layer 7, n-InP layer 6b, InGaP single strain layer 8, n-InP layer 9, and n-GaSb layer 10
grow x sequentially. After that, the surface of the n-GaSb layer 10x is washed by the same method as in the first embodiment, and the n-Si substrate 3 is formed.
Is treated with HF diluted solution, washed with water and dried by spinner.

【００３８】これらを洗浄した面を向かい合わせて重
ね、第一実施例と同様の方法で接着する。こうして図７
(ｂ)に示すように、ｎ−Ｓｉ基板３とｐ−ＩｎＰ基板１
がＩｎＧａＰ単一歪層５〜８およびｎ−ＧａＳｂ層１０
ｘを介して接着された構造が得られる。接着後、ｐ−Ｉ
ｎＰ基板１を塩酸でエッチング除去し、更にｐ−ＩｎＧ
ａＡｓ層１１を硫酸と過酸化水素の混合溶液でエッチン
グ除去した。その後、通常の半導体レーザ作製プロセス
を経て電極等を形成し、長波長レーザを作製した。These cleaned surfaces are superposed facing each other and bonded in the same manner as in the first embodiment. Thus, FIG.
As shown in (b), the n-Si substrate 3 and the p-InP substrate 1
Are InGaP single strained layers 5-8 and n-GaSb layer 10
A structure bonded via x is obtained. After adhesion, p-I
The nP substrate 1 is removed by etching with hydrochloric acid, and then p-InG
The aAs layer 11 was removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. Then, electrodes and the like were formed through a normal semiconductor laser manufacturing process to manufacture a long wavelength laser.

【００３９】本実施例では、ｎ−ＧａＳｂ層１０ｘによ
り接着界面でのミスフィット転位の発生が抑制され、且
つ、単一歪層によって転位の伝播が阻止されるため、レ
ーザの劣化がより確実に抑制されて、劣化する素子がほ
とんどなくなった。In the present embodiment, the n-GaSb layer 10x suppresses the generation of misfit dislocations at the adhesive interface, and the single strained layer prevents the propagation of dislocations. Almost no elements were suppressed and deteriorated.

【００４０】本実施例は、第四実施例と同様にＧａＳｂ
層を介することによってミスフィット転位の発生を抑制
するが、ＧａＳｂの代りに実施例５に記載のような熱膨
張係数の小さい材料や、第六実施例に記載のような格子
定数の小さい材料等その他の材料を用いることも可能で
ある。また、単一歪層によって転位の伝播を阻止してい
るが、各々の単一歪層の代りに実施例３に記載のような
歪超格子層を用いることも可能であり、またその導入回
数は本実施例に限らない。更に、接着する基板の種類や
デバイス構造，接着方法も本実施例に限らない。This embodiment is similar to the fourth embodiment in GaSb.
Although the occurrence of misfit dislocations is suppressed by interposing a layer, a material having a small coefficient of thermal expansion as described in Example 5 or a material having a small lattice constant as described in Example 6 instead of GaSb. Other materials can also be used. Although dislocation propagation is blocked by the single strained layers, it is possible to use strained superlattice layers as described in Example 3 instead of the single strained layers, and the number of times of introduction thereof. Is not limited to this embodiment. Furthermore, the type of substrate to be bonded, the device structure, and the bonding method are not limited to those in this embodiment.

【００４１】（実施例８）本発明を光電子集積化素子
（ＯＥＩＣ）に適用した場合について、図８により説明
する。(Embodiment 8) A case where the present invention is applied to an optoelectronic integrated device (OEIC) will be described with reference to FIG.

【００４２】図８(ａ)に示すように、ｎ−ＧａＡｓ基板
２ａ上の一部にアンドープＧａＡｓ層３１(厚さ１.０μ
ｍ），ｐ−ＡｌＧａＡｓ層３２(厚さ０.３μｍ），アン
ドープＧａＡｓ層３３（厚さ１.０μｍ），ｎ−ＧａＡ
ｓチャネル層３４（厚さ０.３μｍ），ｎ+−ＧａＡｓコ
ンタクト層３５（厚さ０.１μｍ）を選択成長し、レー
ザの駆動回路として機能する電界効果トランジスタ（Ｆ
ＥＴ）を形成する。このＦＥＴおよび周辺部をＳｉＯ₂
膜３６でコーティングする。As shown in FIG. 8A, an undoped GaAs layer 31 (thickness 1.0 μm) is formed on a part of the n-GaAs substrate 2a.
m), p-AlGaAs layer 32 (thickness 0.3 μm), undoped GaAs layer 33 (thickness 1.0 μm), n-GaA
The s-channel layer 34 (thickness 0.3 μm) and the n + -GaAs contact layer 35 (thickness 0.1 μm) are selectively grown, and the field effect transistor (F
ET) is formed. The FET and the peripheral portion of SiO ₂
Coat with membrane 36.

【００４３】一方同図（ｂ）のようにｐ−ＩｎＰ基板１
上の一部にｐ−ＩｎＧａＡｓエッチングストップ層１
１，ｐ−ＩｎＰ層１３，アンドープＩｎＧａＡｓＰ活性
層１４，ｎ−ＩｎＰ層１５，ＩｎＧａＰ単一歪層５，ｎ
−ＩｎＰ層６ａ，ＩｎＧａＰ単一歪層７，ｎ−ＩｎＰ層
６ｂ，ＩｎＧａＰ単一歪層８，ｎ−ＩｎＰ層９を成長
し、側面にＳｉＯ₂ 膜３６を形成する。この後、ＧａＡ
ｓ基板２ａの露出部分とｎ−ＩｎＰ層９の表面を実施例
１と同様の方法で洗浄する。これらの洗浄した面を、図
９(ａ)に示すように向かい合わせて重ね、実施例１と同
様の方法で接着する。接着後、ＩｎＰ基板１を塩酸でエ
ッチング除去し、更にＩｎＧａＡｓ層１１を硫酸と過酸
化水素の混合溶液でエッチング除去する。On the other hand, as shown in FIG. 3B, p-InP substrate 1
P-InGaAs etching stop layer 1 on the upper part
1, p-InP layer 13, undoped InGaAsP active layer 14, n-InP layer 15, InGaP single strain layer 5, n
-InP layer 6a, InGaP single strained layer 7, n-InP layer 6b, grown InGaP single strained layer 8, n-InP layer 9, an SiO ₂ film 36 on the side surface. After this, GaA
The exposed portion of the s substrate 2a and the surface of the n-InP layer 9 are cleaned by the same method as in the first embodiment. These washed surfaces are faced to each other as shown in FIG. After the adhesion, the InP substrate 1 is removed by etching with hydrochloric acid, and the InGaAs layer 11 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide.

【００４４】本実施例ではレーザ構造はＢＨ（Ｂuried
Ｈeterostructure）構造とし、エッチングによって図９
(ｂ)のようなメサ形状を形成し、側面を半絶縁性ＩｎＰ
層１６とｎ−ＩｎＰ層１７で埋め込む。更にｐ−ＩｎＰ
層１３ａ，ｐ+−InGaAsP層１２を成長し、ＳｉＯ₂ 膜３
６を追加形成する。その後、ＦＥＴ部にコーティングし
たＳｉＯ₂ 膜３６を選択エッチングし、電極３７を形成
してＯＥＩＣを作製した。In this embodiment, the laser structure is BH (Buried).
Heterostructure) structure and etching
The mesa shape as shown in (b) is formed, and the side surface is semi-insulating InP.
The layer 16 and the n-InP layer 17 are embedded. Furthermore, p-InP
The layer 13a and the p + -InGaAsP layer 12 are grown, and the SiO ₂ film 3 is formed.
6 is additionally formed. After that, the SiO ₂ film 36 coated on the FET portion was selectively etched to form an electrode 37, thereby manufacturing an OEIC.

【００４５】本実施例によるＯＥＩＣでＦＥＴによる半
導体レーザ駆動動作を確認した。更にレーザの動作特性
は、高温駆動状態でも劣化することはなかった。これ
は、単一歪層によって転位の伝播が阻止されたことによ
る。本発明の適用は本実施例で示したＯＥＩＣの構造に
限らない。The operation of driving the semiconductor laser by the FET was confirmed by the OEIC according to this example. Furthermore, the operating characteristics of the laser did not deteriorate even at high temperature driving. This is because dislocation propagation was blocked by the single strained layer. The application of the present invention is not limited to the structure of the OEIC shown in this embodiment.

【００４６】[0046]

【発明の効果】本発明ではミスフィット転位の発生を抑
える層、若しくは伝播を抑える層を形成した後に異種基
板の接着を行うため、接着後のミスフィット転位による
結晶の劣化が抑えられる。このため、接着した構造を用
いてデバイスを作製した場合、デバイス特性が転位の影
響を受けない。According to the present invention, since the heterogeneous substrates are bonded after forming the layer for suppressing the generation of misfit dislocations or the layer for suppressing the propagation thereof, the deterioration of the crystal due to the misfit dislocations after the bonding can be suppressed. Therefore, when the device is manufactured by using the bonded structure, the device characteristics are not affected by the dislocation.

【００４７】また、本発明はいかなる組合せの異種基板
の接着にも適用が可能で、それぞれの組合せで基板間の
物性差に応じ、それを緩和するのに適した層を形成する
ことにより、結晶の劣化が抑制される。Further, the present invention can be applied to adhesion of heterogeneous substrates in any combination, and by forming a layer suitable for alleviating the physical property difference between the substrates in each combination, a crystal is formed. Is suppressed.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例を示す半導体装置の断面図。FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention.

【図２】本発明の第二実施例を示す半導体装置の断面
図。FIG. 2 is a sectional view of a semiconductor device showing a second embodiment of the present invention.

【図３】本発明の第三実施例を示す半導体装置の断面
図。FIG. 3 is a sectional view of a semiconductor device showing a third embodiment of the present invention.

【図４】本発明の第四実施例を示す半導体装置の断面
図。FIG. 4 is a sectional view of a semiconductor device showing a fourth embodiment of the present invention.

【図５】本発明の第五実施例を示す半導体装置の断面
図。FIG. 5 is a sectional view of a semiconductor device showing a fifth embodiment of the present invention.

【図６】本発明の第六実施例を示す半導体装置の断面
図。FIG. 6 is a sectional view of a semiconductor device showing a sixth embodiment of the present invention.

【図７】本発明の第七実施例を示す半導体装置の断面
図。FIG. 7 is a sectional view of a semiconductor device showing a seventh embodiment of the present invention.

【図８】本発明を光電子集積化素子に適用した場合の半
導体装置の断面図。FIG. 8 is a sectional view of a semiconductor device when the present invention is applied to an optoelectronic integrated element.

【図９】本発明を光電子集積化素子に適用した場合の半
導体装置の断面図。FIG. 9 is a sectional view of a semiconductor device when the present invention is applied to an optoelectronic integrated device.

【図１０】従来の半導体装置の断面図。FIG. 10 is a sectional view of a conventional semiconductor device.

【図１１】従来の他の半導体装置の断面図。FIG. 11 is a cross-sectional view of another conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１…ｐ−ＩｎＰ基板、３…ｎ−Ｓｉ基板、５，７，８…
ＩｎＧａＰ単一歪層、６ａ，６ｂ，９，１５…ｎ−Ｉｎ
Ｐ層、１０ｘ…ｎ−ＧａＳｂ層、１１…ｐ−ＩｎＧａＡ
ｓエッチングストップ層、１２…ｐ+−ＩｎＧａＡｓＰ
層、１３…ｐ−ＩｎＰ層、１４…アンド−プＩｎＧａＡ
ｓＰ活性層。1 ... p-InP substrate, 3 ... n-Si substrate, 5, 7, 8 ...
InGaP single strained layer, 6a, 6b, 9, 15 ... n-In
P layer, 10x ... n-GaSb layer, 11 ... p-InGaA
s Etching stop layer, 12 ... p + -InGaAsP
Layer, 13 ... p-InP layer, 14 ... And-type InGaA
sP active layer.

Claims (15)

【特許請求の範囲】[Claims] 【請求項１】第一の半導体基板と、第二の半導体基板と
を接着してなる半導体装置において、前記第一の半導体
基板と前記第二の半導体基板との間に転位低減領域が配
設されていることを特徴とする半導体装置。1. A semiconductor device in which a first semiconductor substrate and a second semiconductor substrate are bonded to each other, and a dislocation reduction region is provided between the first semiconductor substrate and the second semiconductor substrate. A semiconductor device characterized by being provided. 【請求項２】請求項１において、前記転位低減領域を複
数層有する半導体装置。2. The semiconductor device according to claim 1, wherein the dislocation reduction region has a plurality of layers. 【請求項３】請求項１または２において、前記転位低減
領域が単層の歪薄膜を有する半導体装置。3. The semiconductor device according to claim 1, wherein the dislocation reduction region has a single-layer strain thin film. 【請求項４】請求項１または２において、前記転位低減
領域が歪超格子層を有する半導体装置。4. The semiconductor device according to claim 1, wherein the dislocation reduction region has a strained superlattice layer. 【請求項５】請求項１，２，３または４において、前記
第一の半導体基板および前記転位低減領域がIII−Ｖ 族
化合物よりなる半導体装置。5. The semiconductor device according to claim 1, 2, 3 or 4, wherein the first semiconductor substrate and the dislocation reduction region are made of a III-V group compound. 【請求項６】請求項１，２，３，４または５において、
前記第二の半導体基板がＳｉである半導体装置。6. The method according to claim 1, 2, 3, 4 or 5.
A semiconductor device in which the second semiconductor substrate is Si. 【請求項７】第一の半導体基体の上に転位低減領域を形
成する工程と、前記転位低減領域の表面と第二の半導体
基体の表面とを密着させてこれらを直接接着する工程を
含むことを特徴とする半導体装置の製造方法。7. A step of forming a dislocation reduction region on a first semiconductor substrate, and a step of adhering a surface of the dislocation reduction region and a surface of a second semiconductor substrate directly to each other. A method for manufacturing a semiconductor device, comprising: 【請求項８】第一の半導体基板と、第二の半導体基板と
を直接接着してなる半導体装置において、前記第一の半
導体基板および前記第二の半導体基板より熱膨張係数が
大きい、第三の半導体層を介して直接接着してなること
を特徴とする半導体装置。8. A semiconductor device in which a first semiconductor substrate and a second semiconductor substrate are directly adhered to each other, wherein a thermal expansion coefficient is larger than those of the first semiconductor substrate and the second semiconductor substrate. A semiconductor device characterized by being directly bonded via the semiconductor layer of. 【請求項９】第一の半導体基板と、第二の半導体基板と
を直接接着してなる半導体装置において、前記第一の半
導体基板および前記第二の半導体基板より熱膨張係数が
小さい、第三の半導体層を介して直接接着してなること
を特徴とする半導体装置。9. A semiconductor device in which a first semiconductor substrate and a second semiconductor substrate are directly adhered to each other, wherein a thermal expansion coefficient is smaller than those of the first semiconductor substrate and the second semiconductor substrate. A semiconductor device characterized by being directly bonded via the semiconductor layer of. 【請求項１０】第一の半導体基板と、第二の半導体基板
とを直接接着してなる半導体装置において、前記第一，
第二の半導体基板の格子定数よりも小さい格子定数を有
する第三の半導体層を介して直接接着してなることを特
徴とする半導体装置。10. A semiconductor device comprising a first semiconductor substrate and a second semiconductor substrate directly bonded to each other, wherein:
A semiconductor device, which is directly bonded via a third semiconductor layer having a lattice constant smaller than that of the second semiconductor substrate. 【請求項１１】請求項８，９または１０において、前記
第三の半導体層は、前記第一の半導体基板および前記第
二の半導体基板より弾性定数が小さい半導体装置。11. The semiconductor device according to claim 8, 9 or 10, wherein the third semiconductor layer has a smaller elastic constant than the first semiconductor substrate and the second semiconductor substrate. 【請求項１２】請求項８，９，１０または１１におい
て、前記第一の半導体基板がIII−Ｖ 族化合物よりなる
半導体装置。12. The semiconductor device according to claim 8, 9, 10 or 11, wherein the first semiconductor substrate is made of a III-V group compound. 【請求項１３】請求項８，９，１０，１１または１２に
おいて、前記第二の半導体基板はＳｉである半導体装
置。13. The semiconductor device according to claim 8, 9, 10, 11 or 12, wherein the second semiconductor substrate is Si. 【請求項１４】請求項８，９，１０または１１におい
て、前記第一の半導体基体の上に前記第三の半導体層を
形成する工程と、前記第三の半導体層の表面と前記第二
の半導体基体の表面とを密着させてこれらを直接接着す
る工程を含む半導体装置の製造方法。14. The method according to claim 8, 9, 10 or 11, wherein the step of forming the third semiconductor layer on the first semiconductor substrate, the surface of the third semiconductor layer and the second semiconductor layer. A method of manufacturing a semiconductor device, which includes a step of closely adhering to a surface of a semiconductor substrate and directly adhering them. 【請求項１５】請求項１，２，３，４，５，６，８，
９，１０，１１，１２または１３において、前記半導体
装置が、半導体光素子あるいは光電子集積化素子である
半導体装置。15. Claims 1, 2, 3, 4, 5, 6, 8,
9. The semiconductor device according to 9, 10, 11, 12 or 13, wherein the semiconductor device is a semiconductor optical element or an optoelectronic integrated element.