JPH0770999B2 - Voltage controlled oscillator - Google Patents
Voltage controlled oscillatorInfo
- Publication number
- JPH0770999B2 JPH0770999B2 JP3018748A JP1874891A JPH0770999B2 JP H0770999 B2 JPH0770999 B2 JP H0770999B2 JP 3018748 A JP3018748 A JP 3018748A JP 1874891 A JP1874891 A JP 1874891A JP H0770999 B2 JPH0770999 B2 JP H0770999B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- signal
- controlled oscillator
- voltage controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は位相固定ループ（ＰＬ
Ｌ，Phase Locked Loop）等に用いられる電圧制御発振
回路に関する。本発明は電圧制御発振回路の特にフリー
ラン周波数の安定化を計った回路に関する。BACKGROUND OF THE INVENTION The present invention relates to a phase locked loop (PL
The present invention relates to a voltage controlled oscillator circuit used for L, Phase Locked Loop, etc. The present invention relates to a voltage-controlled oscillator circuit, particularly to a circuit in which the free-run frequency is stabilized.
【０００２】[0002]
【従来の技術】従来より電圧制御発振回路は非常に多く
発表されている。図３に例としてＰＬＬ用１チップ相補
ＭＯＳ集積回路（ＣＭＯＳ・ＩＣ）に用いられている電
圧制御発振回路を掲げる。ＮチャネルトランジスタＮ1
のゲートに加えられる制御電圧によりコンデンサＣ1に
流入する電流を制御し発振周波数をコントロールする。
抵抗Ｒ1，Ｒ2はそれぞれ制御電圧感度係数、フリーラン
周波数を決定する。2. Description of the Related Art A large number of voltage-controlled oscillator circuits have been published. FIG. 3 shows, as an example, a voltage controlled oscillator circuit used in a one-chip complementary MOS integrated circuit for PLL (CMOS IC). N-channel transistor N 1
The control voltage applied to the gate of control the current flowing into the capacitor C 1 to control the oscillation frequency.
The resistors R 1 and R 2 determine the control voltage sensitivity coefficient and the free-run frequency, respectively.
【０００３】また他の例として図４には特公昭５６−８
６５０９により公知の電圧制御発振回路を示す。該回路
はリングオシレータに流入する電流をソースに接続され
たトランジスタＴ41〜Ｔ46のゲート電圧により制御し発
振周波数を制御するものである。この回路は図４の回路
に比較し外付部品が不要で消費電力、実装スペースも小
さい利点があるが正確で安定な発振回路は作りにくい。
また図３の回路でも安定度は充分とは言えない。As another example, FIG. 4 shows a Japanese Patent Publication Sho 56-8.
6509 shows a known voltage controlled oscillator circuit. This circuit controls the oscillation frequency by controlling the current flowing into the ring oscillator by the gate voltage of the transistors T 41 to T 46 connected to the sources. Compared to the circuit shown in FIG. 4, this circuit does not require external parts and consumes less power and has a smaller mounting space, but it is difficult to make an accurate and stable oscillation circuit.
Also, the circuit of FIG. 3 cannot be said to have sufficient stability.
【０００４】[0004]
【発明が解決しようとする課題】一般に電圧制御発振回
路にし安定度の要求されるのはフリーラン周波数及び電
圧制御感度係数である。前者は電圧制御発振回路の制御
端子に加えられる電圧（制御電圧）が基準レベルにとき
の発振周波数である。基準レベルは通常制御可能な入力
電圧範囲の中央、例えばＣＭＯＳ・ＩＣでは電源電圧の
１／２に選ばれ、制御電圧をＶC・基準レベルの電圧を
ＶSとしてΔＶCを ΔＶC＝ＶC−ＶS ……………(1) と定義すればフリーラン周波数はΔＶC＝０のときの発
振周波数と言い直しても良い。電圧制御感度係数ＫVは ｆO＝ｆC＋ＫV・ΔＶ ………(2) として定義される。ｆCはフリーラン周波数、ｆOは電圧
制御発振回路の発振周波数である。Generally, it is the free-run frequency and the voltage control sensitivity coefficient that are required to have stability in the voltage control oscillator circuit. The former is the oscillation frequency when the voltage (control voltage) applied to the control terminal of the voltage controlled oscillator circuit is at the reference level. The reference level is usually selected at the center of the controllable input voltage range, for example, 1/2 of the power supply voltage in a CMOS IC, and the control voltage is V C and the reference level voltage is V S , and ΔV C is ΔV C = V C −V S ………… (1) The free-run frequency may be rephrased as the oscillation frequency when ΔV C = 0. The voltage control sensitivity coefficient K V is defined as f O = f C + K V · ΔV (2) f C is a free run frequency, and f O is an oscillation frequency of the voltage controlled oscillator circuit.
【０００５】フリーラン周波数ｆCのドリフトはＰＬＬ
においては系のキャプチャレンジのドリフトとなって悪
影響があらわれる。また、回路部品定数のばらつきによ
るｆCのばらつきは無視できない程度に大きく、従来は
コスト高を覚悟した上で高制度部品を用いるか、組立後
に半固定抵抗や半固定コンデンサにより調整、合せ込み
をする必要があった。また電圧制御感度係数ＫVのドリ
フトはＰＬＬを構成した場合、系の応答速度のドリフト
となって悪影響があらわれる。The drift of the free-run frequency f C is due to the PLL
In, the adverse effect appears as a drift of the capture range of the system. In addition, the variation of f C due to the variation of the circuit component constant is so large that it cannot be ignored, and in the past, it was necessary to use high precision components with high cost in mind, or to adjust and adjust with a semi-fixed resistor or semi-fixed capacitor after assembly. Had to do. Further, the drift of the voltage control sensitivity coefficient K V becomes a drift of the response speed of the system when the PLL is configured, and adversely appears.
【０００６】これ等のドリフトの原因は周囲温度の変
化、使用電源の変動、部品定数の経時変化等である。特
にｆCの変動はこれ等の要因により大きくドリフトす
る。一方ＫVは回路の構成部品の相対精度により決まる
様にすることができ半導体集積回路技術等により素子値
の絶対精度はなくとも相対的に充分なトラッキング特性
を持たせることによりその変動を小さくできる。The causes of these drifts are changes in the ambient temperature, fluctuations in the power supply used, changes in the component constants over time, and the like. Especially, the fluctuation of f C largely drifts due to these factors. On the other hand, K V can be determined by the relative accuracy of the components of the circuit, and its variation can be reduced by providing a relatively sufficient tracking characteristic without absolute accuracy of the element value by semiconductor integrated circuit technology or the like. .
【０００７】本発明は従来の電圧制御発振回路のドリフ
トを押える回路方式に関するものであって回路の構成部
品の定数のばらつき変動による発振回路の定数（ｆC，
ＫV）の変動を小さくし回路の安定性を増大することに
ある。The present invention relates to a circuit system that suppresses the drift of a conventional voltage controlled oscillator circuit, and the oscillator circuit constant (f C ,
The purpose is to reduce the fluctuation of K V ) and increase the stability of the circuit.
【０００８】本発明の他の目的は回路定数の絶対精度に
対しての変動を抑えることにより集積回路化しやすい電
圧制御発振回路を提供することにある。Another object of the present invention is to provide a voltage controlled oscillator circuit which can be easily integrated into an integrated circuit by suppressing the fluctuation of the circuit constant with respect to the absolute accuracy.
【０００９】[0009]
【課題を解決するための手段】本発明は、少なくとも以
下の構成要件 ａ．第１，第２の端子（１０９，１１０）に与えられた
信号を受けてそれ等の信号を合成し出力する第１の手段
−１０１ ｂ．前記手段１０１と同じ特性を有する第２の手段−１
０３ ｃ．前記第１の信号合成手段１０１の信号により発振周
波数を制御される第１の発振回路−１０２ ｄ．前記発振回路１０２と同じ特性を持ち前記第２の信
号合成手段１０３の信号により制御される第２の発振回
路−１０４ ｅ．基準となる周波数の信号を発する手段−１０７を有
し、前記第２の発振回路１０４の出力は前記基準となる
周波数の信号を発する手段１０７より発せられる信号と
位相を比較し、その結果により前記第２の発振回路１０
４の出力周波数を調整すべく前記第２の信号合成手段１
０３の第２の入力端子１１２に信号を加える。また前記
第２の信号合成手段１０３の第１の入力端子１１１には
基準レベルとなるレベル信号を与え前記第１の信号合成
手段１０１の第２の入力端子１１０には前記第２の信号
合成手段１０３の第２の入力端子１１２に印加される信
号を与える。さらに前記第１の信号合成手段１０１の第
１の入力端子１０９を制御端子、第一の発振回路１０２
の出力を出力とすることを特徴とする。The present invention provides at least the following requirements a. First means for receiving signals given to the first and second terminals (109, 110) and synthesizing those signals and outputting them-b. Second means-1 having the same characteristics as the means 101
03 c. First oscillator circuit 102 whose oscillation frequency is controlled by the signal of the first signal synthesizer 101 d. A second oscillating circuit-104 having the same characteristics as the oscillating circuit 102 and controlled by the signal of the second signal synthesizing means 103 e. It has a means-107 for emitting a signal of a reference frequency, and the output of the second oscillating circuit 104 compares the phase with a signal emitted by the means 107 for emitting a signal of the reference frequency, and as a result, Second oscillator circuit 10
The second signal synthesizing means 1 for adjusting the output frequency of
A signal is applied to the second input terminal 112 of 03. Further, a level signal as a reference level is given to the first input terminal 111 of the second signal synthesizing means 103, and the second signal synthesizing means is applied to the second input terminal 110 of the first signal synthesizing means 101. A signal is applied to the second input terminal 112 of 103. Further, the first input terminal 109 of the first signal synthesizing means 101 is a control terminal, and the first oscillating circuit 102 is
Is output.
【００１０】[0010]
【実施例】図１は本発明の概念を示す図である。１０
１，１０３は同一の特性を有する様に設計された信号合
成手段で例えば端子１０９に与えられる信号（以下、電
圧値として話をすすめる。電流値、電荷値等他の物理量
でも話は同じである。）をＶ11、端子１１０に加わる信
号電圧をＶ21、信号合成手段１０１の出力端子１１４に
あらわれる電圧をＶ01とすると Ｖ01＝ｆ（Ｖ11，Ｖ21） …………(3) ｆは任意関数 の様な特性を有する回路である。以下、簡単のために Ｖ01＝ａＶ11＋ｂＶ21＋ｃ ……(4) とする。（ａ，ｂ，ｃは定数） 同様に端子１１１、端子１１２に加えられる電圧をそれ
ぞれＶ12，Ｖ22 とし信号合成手段１０３の出力端子１
１５の電圧をＶ02としたとき Ｖ02＝ａＶ12＋ｂＶ22＋ｃ ………(5) とする。１０２，１０４は特性のそろった電圧制御発振
回路であり出力信号の周波数Ｆ1，Ｆ2 は Ｆ1＝ＫV Ｖ01＋ｄ …………………(6) Ｆ2＝ＫV Ｖ02＋ｄ …………………(7) とする（ｄは定数）。１０７は位相比較回路で電圧制御
発振回路１０４の出力と安定な周波数の発振をする発振
回路（例えば水晶発振回路）の出力信号と位相比較をし
その位相差に比較した量の信号を出力する。１０５はロ
ーパスフィルタ（ＬＰＦ）で位相比較回路の出力から希
望する信号成分のみをとり出すために通常入れられる。
ＬＰＦ１０５の出力は第２の信号合成回路１０３の第２
の入力端子１１２に負帰還する。すなわち第２の電圧制
御発振回路１０４、位相比較回路１０６、ＬＰＦ１０
５、信号合成手段１０３はＰＬＬを構成し第２の電圧制
御発振回路の発振周波数は発振回路１０７の発振周波数
ｆｒｅｆと等しくなる。電圧制御発振回路１０４の出力
周波数は位相比較回路１０６、ＬＰＦ１０５の特性によ
りｆｒｅｆと位相まで完全に一致させることもできる
し、またｆｒｅｆの突発的な変化に対しては追従しない
様にすることもできる。発振回路１０７は通常、充分安
定な発振をする回路を用いるので系の応答を速くしても
問題はない。また電圧制御発振回路１０４の出力周波数
とｆｒｅｆは周波数のみ追従し、位相は誤差があっても
よいから回路の構成はかなり自由度がある。発振回路１
０７が不安定でジッタ等を有する時は系の設計によりそ
の影響を軽減できる。FIG. 1 is a diagram showing the concept of the present invention. 10
Reference numerals 1 and 103 denote signal synthesizing means designed to have the same characteristics. For example, a signal given to the terminal 109 (hereinafter, referred to as a voltage value will be described. The same applies to other physical quantities such as a current value and a charge value. .) the V 11, V 21 a signal voltage applied to the terminal 110, the voltage appearing at the output terminal 114 of the signal combining means 101 and V 01 V 01 = f (V 11, V 21) ............ (3) f is a circuit having characteristics such as an arbitrary function. Hereinafter, for simplicity, it is assumed that V 01 = aV 11 + bV 21 + c (4). (A, b, and c are constants) Similarly, the voltages applied to the terminals 111 and 112 are V 12 and V 22 , respectively, and the output terminal 1 of the signal synthesizing means 103.
When the voltage of 15 is V 02 , V 02 = aV 12 + bV 22 + c (5). 102,104 frequencies F 1 of the output signal is a voltage controlled oscillator having a uniform characteristic, F 2 is F 1 = K V V 01 + d ..................... (6) F 2 = K V V 02 + d ………………… (7) (d is a constant). Reference numeral 107 denotes a phase comparison circuit, which compares the output of the voltage controlled oscillation circuit 104 with the output signal of an oscillation circuit (for example, a crystal oscillation circuit) that oscillates at a stable frequency, and outputs a signal of an amount compared with the phase difference. Reference numeral 105 is a low-pass filter (LPF), which is normally inserted in order to extract only a desired signal component from the output of the phase comparison circuit.
The output of the LPF 105 is the second signal of the second signal combining circuit 103.
Is negatively fed back to the input terminal 112 of the. That is, the second voltage controlled oscillator circuit 104, the phase comparison circuit 106, the LPF 10
5. The signal synthesizing means 103 constitutes a PLL, and the oscillation frequency of the second voltage controlled oscillation circuit becomes equal to the oscillation frequency fref of the oscillation circuit 107. The output frequency of the voltage controlled oscillator circuit 104 can be made to completely match the fref and the phase depending on the characteristics of the phase comparison circuit 106 and the LPF 105, and it is also possible not to follow a sudden change in fref. . Since the oscillator circuit 107 normally uses a circuit that oscillates sufficiently stably, there is no problem even if the response of the system is fast. Further, since the output frequency of the voltage controlled oscillator circuit 104 and fref follow only the frequency and there may be an error in the phase, there is a considerable degree of freedom in the circuit configuration. Oscillation circuit 1
When 07 is unstable and has jitter, etc., its influence can be reduced by designing the system.
【００１１】さて、電源電圧の変動、温度特性、経時変
化等により電圧制御発振回路１０４のフリーラン周波数
が変動した場合を考えよう。このとき系は自動的に端子
１１２に加わる電圧を上げ下げして電圧制御発振回路１
０４の発振周波数はｆｒｅｆを保つ。また第２の信号合
成手段１０３の第１の制御端子１１１に任意の電圧値を
与えた場合もその電圧値にかかわらず第２の電圧制御発
振回路の発振周波数はｆｒｅｆとなる様、端子１１２の
電圧は自動的に調整される。Now, let us consider a case where the free-run frequency of the voltage controlled oscillator circuit 104 fluctuates due to fluctuations in the power supply voltage, temperature characteristics, changes over time, and the like. At this time, the system automatically raises and lowers the voltage applied to the terminal 112 to change the voltage controlled oscillation circuit 1
The oscillation frequency of 04 keeps fref. Further, even if an arbitrary voltage value is given to the first control terminal 111 of the second signal synthesizing means 103, the oscillation frequency of the second voltage controlled oscillator circuit becomes fref regardless of the voltage value. The voltage is adjusted automatically.
【００１２】従って、第２の信号合成回路の第１の入力
端子１１１に基準となる電圧ＶSを与えると第２の入力
端子１１２は自動的にレベル調整され電圧制御発振回路
１０４の発振周波数ｆｒｅｆに等しくなる。図１に示す
様に第２の信号合成手段１０３の第２の入力端子１１２
の電圧を第１の信号合成手段１０１の第２の入力端子１
１０にも与えると第１、第２の信号合成手段、電圧制御
発振回路はそれぞれ特性がそろっているので第１の電圧
制御発振回路１０２の発振周波数は第１の信号合成手段
１０１の第１の入力端子１０９に与えられる電圧がＶS
のときｆｒｅｆとなる。ｆｒｅｆを希望するフリーラン
周波数ｆCに等しく設定しておけば端子１０９の電圧が
ＶSのとき電圧制御発振回路１０２の発振周波数はｆCと
なる。従って図１の回路全体を端子１０９を制御端子、
１１３を出力端子とする電圧制御発振回路とすればフリ
ーラン周波数がｆCの電圧制御回路を実現できたことに
なる。 回路内の２つの信号合成手段１０１，１０３、
電圧制御発振回路１０２，１０４の特性は等しいと仮定
して議論をしてきたが、この仮定は極めて妥当なもので
ある。特にモノシリック集積回路化した場合、各々は数
ミリ角のチップ上に高精度で対称性よく作り込むことが
できる。各々の回路は同時に製造されるため経時変化が
あったとしても同一の経過時間であり特性が各々で異な
ってくることは少ない。また電源電圧や温度変化に対し
ても同一の電源にて使用されるし、また、きわめて近い
場所に配置されているため双方に温度差を生じ特性が異
なってくることも少ない。集積回路の設計時に各々の回
路の対称性を充分配慮しておけば、各特性の変動は互い
にキャンセルしあってドリフトの少ない安定な電圧制御
発振回路を実現できる。Therefore, when the reference voltage V S is applied to the first input terminal 111 of the second signal synthesis circuit, the level of the second input terminal 112 is automatically adjusted and the oscillation frequency fref of the voltage controlled oscillation circuit 104 is adjusted. Is equal to As shown in FIG. 1, the second input terminal 112 of the second signal combining means 103.
To the second input terminal 1 of the first signal combining means 101.
10, the characteristics of the first and second signal synthesizing means and the voltage controlled oscillator circuit are the same, so that the oscillation frequency of the first voltage controlled oscillator circuit 102 is the same as that of the first signal synthesizing means 101. The voltage applied to the input terminal 109 is V S
In case of, it becomes fref. If fref is set equal to the desired free-run frequency f C , the oscillation frequency of the voltage controlled oscillator circuit 102 becomes f C when the voltage at the terminal 109 is V S. Therefore, the entire circuit of FIG.
If a voltage-controlled oscillator circuit having 113 as an output terminal is used, it means that a voltage control circuit having a free-run frequency f C can be realized. Two signal combining means 101, 103 in the circuit,
Although the discussion has been made on the assumption that the characteristics of the voltage controlled oscillator circuits 102 and 104 are equal, this assumption is extremely valid. In particular, in the case of forming a monolithic integrated circuit, each can be built on a chip of several millimeters square with high accuracy and good symmetry. Since each circuit is manufactured at the same time, even if there is a change with time, the same elapsed time is obtained and the characteristics rarely differ from each other. Further, the same power source is used for the power supply voltage and the temperature change, and since they are arranged at extremely close places, it is unlikely that a temperature difference occurs between them and the characteristics are different. If the symmetry of each circuit is sufficiently taken into consideration when designing the integrated circuit, it is possible to realize a stable voltage controlled oscillation circuit with less drift by canceling the fluctuations in each characteristic.
【００１３】図２は以上の本発明の考え方にもとづき半
導体集積回路により実現できる電圧制御発振回路の具体
例を示す図である。２０１は信号合成回路でトランジス
タＴ1及びＴ2のゲート電圧を変えることにより各々のド
レイン電流を変える。Ｔ1，Ｔ2のドレイン電流は合成
（加算）されトランジスタＴ13に流れ込み電圧に変換さ
れる。この電圧は第１の電圧制御発振回路の制御電圧で
あり、ＭＯＳトランジスタで構成される電圧制御発振回
路２０２に入力される。この回路はトランジスタＴ7，
Ｔ10，Ｔ8，Ｔ11，……Ｔ9，Ｔ12により構成される奇数
段のインバータによりリングオシレータを構成し、各々
のトランジスタのソースさらにトランジスタＴ4，Ｔ5，
…Ｔ6，Ｔ15，Ｔ16，…Ｔ17を直列に入れ、これ等のト
ランジスタのゲート電位を制御することによりリングオ
シレータに電源より流入する電流を制御し発振周波数を
制御するものである。本発明の例では端子２１２，２１
４の電位が低くなる程Ｔ13のドレイン電圧（電圧制御発
振回路２０２の制御電圧）が上昇し発振周波数が上が
る。すなわち(4)式においてａ，ｂが負、(6)式において
ＫVが正の場合である。端子２１２，２１４のレベルが
高い時に高い周波数で発振させたければ例えば２０１，
２０２の回路のトランジスタの極性をすべて逆（Ｐチャ
ネルトランジスタをＮチャネルに、Ｎチャネルトランジ
スタをＰチャネルに）にすれば、ａ，ｂが負、ＫVが負
となり達成できる。２０５，２０６は出力を得るための
バッファ回路である。FIG. 2 is a diagram showing a specific example of a voltage controlled oscillator circuit which can be realized by a semiconductor integrated circuit based on the above idea of the present invention. A signal combining circuit 201 changes the drain current of each of the transistors T 1 and T 2 by changing the gate voltage thereof. The drain currents of T 1 and T 2 are combined (added) and flow into the transistor T 13 to be converted into a voltage. This voltage is the control voltage of the first voltage controlled oscillator circuit and is input to the voltage controlled oscillator circuit 202 composed of MOS transistors. This circuit consists of a transistor T 7 ,
T 10, T 8, T 11 , ...... T 9, constitute a ring oscillator by an odd number of stages of the inverter constituted by the T 12, the source further transistor of each of the transistors T 4, T 5,
... T 6, T 15, T 16, ... put T 17 in series, and controls the oscillation frequency by controlling the current flowing from the power supply to the ring oscillator by controlling a gate potential of the transistor of this like. In the example of the present invention, the terminals 212, 21
As the potential of 4 decreases, the drain voltage of T 13 (control voltage of the voltage controlled oscillator circuit 202) increases and the oscillation frequency increases. That is, this is the case where a and b are negative in the equation (4) and K V is positive in the equation (6). If you want to oscillate at a high frequency when the levels of the terminals 212 and 214 are high, for example, 201,
If the polarities of the transistors of the circuit 202 are all reversed (P channel transistor is N channel, N channel transistor is P channel), a and b are negative and K V is negative, which can be achieved. 205 and 206 are buffer circuits for obtaining outputs.
【００１４】２０３，２０４はそれぞれ２０１，２０２
と同様の回路構成を持つ信号合成回路、電圧制御発振回
路である。内部構成は同じなので図では内部を省略して
ある。第２の電圧制御発振回路の出力はバッファ２０７
を通し位相比較回路２０８に入力される。２１１は水晶
発振回路でフリーラン周波数の基準となる周波数ｆｒｅ
ｆ（＝ｆＣ）を発振する発振回路である。通常はこの信
号は位相比較回路２０８に入力され第２の電圧制御発振
回路２０４の出力と位相比較されるとともに他の回路の
タイミングクロック、システムクロックなどと共用され
る。もし他の回路の要求するクロック信号等の周波数と
希望するｆＣが異なる場合はノード２１９または２１８
の一方か双方に分周回路や周波数変換回路を入れること
により水晶発振回路２１１の発振周波数の整数倍、整数
分の１、それ等の差、整数分の整等にｆＣを設定するこ
とが可能である。分周回路や周波数変換回路はデジタル
回路で構成でき半導体集積回路化に際して何ら障害は生
じない。２１７はローパスフィルタで位相比較回路２０
８の出力に含まれる高周波成分を除去する。出力は第２
の信号合成回路２０３の第２の入力端子２１５に帰還さ
れる。第１の入力端子２１３にはｆＣを発振させたい入
力信号レベル（基準レベル）を与えるべく電源電圧を分
圧する抵抗Ｒ１１，Ｒ１２が接続されている。抵抗は半
導体集積回路内に正確なものは作りにくいが相対精度は
非常に高く作ることが可能である。この端子には例えば
ツエナーダイオードによる基準電圧等のもっと正確な電
圧源を接続しても良い。第１及び第２の信号の信号合成
回路の第２の入力端子２１４，２１５にはローパスフィ
ルタ２１７内部の異なったところから信号をとり出し接
続しているが抵抗Ｒ４はＰＬＬ系の安定化のために必要
な抵抗であって図１の場合と本質的に異なるものではな
い。Reference numerals 203 and 204 denote 201 and 202, respectively.
The signal synthesizing circuit and the voltage controlled oscillating circuit have the same circuit configuration. Since the internal structure is the same, the inside is omitted in the figure. The output of the second voltage controlled oscillator circuit is the buffer 207.
Is input to the phase comparison circuit 208 through. Reference numeral 211 is a crystal oscillation circuit, which is a frequency fre which is a reference of the free-run frequency
It is an oscillation circuit that oscillates f (= f C ). Normally, this signal is input to the phase comparison circuit 208 to be phase-compared with the output of the second voltage controlled oscillation circuit 204, and is also used as a timing clock or system clock for other circuits. If the frequency of the clock signal or the like required by another circuit is different from the desired f C, the node 219 or 218
It is possible to set f C to an integral multiple of the oscillation frequency of the crystal oscillation circuit 211, an integer fraction, a difference between them, or an integer fraction adjustment by inserting a frequency divider circuit or a frequency conversion circuit in one or both of them. It is possible. The frequency dividing circuit and the frequency converting circuit can be configured by digital circuits, and no trouble occurs when the semiconductor integrated circuit is formed. Reference numeral 217 is a low-pass filter, which is a phase comparison circuit 20.
The high frequency component included in the output of 8 is removed. Output is second
Is fed back to the second input terminal 215 of the signal combining circuit 203. Resistors R 11 and R 12 for dividing the power supply voltage are connected to the first input terminal 213 so as to provide an input signal level (reference level) for oscillating f C. It is difficult to make an accurate resistor in the semiconductor integrated circuit, but the relative accuracy can be made very high. A more accurate voltage source such as a reference voltage by a Zener diode may be connected to this terminal. Signals are taken out from different points in the low-pass filter 217 and connected to the second input terminals 214 and 215 of the signal combining circuit for the first and second signals, but the resistor R 4 stabilizes the PLL system. The resistance required for this purpose is not essentially different from the case of FIG.
【００１５】図２の構成を見ると抵抗Ｒ１１〜Ｒ１５、
コンデンサＣ１１〜Ｃ１３、水晶発振子Ｘを除けばすべ
てＭＯＳトランジスタで構成されている。抵抗、コンデ
ンサは絶対精度が要求されることは無い。従って抵抗は
半導体集積回路に内蔵できる。また必要とする発振周波
数のレンジによっても異なるがコンデンサＣ１１も内蔵
が可能であることが多い。低い周波数が必要なときは出
力端子２１６に分周回路を接続することにより、ＰＬＬ
系は高い周波数で発振させておけばＣ１も小容量で済み
集積回路化が容易となる。Looking at the configuration of FIG. 2, the resistors R 11 to R 15 ,
Except for the capacitors C 11 to C 13 and the crystal oscillator X, they are all composed of MOS transistors. Absolute accuracy is not required for resistors and capacitors. Therefore, the resistor can be built in the semiconductor integrated circuit. Also, the capacitor C 11 can often be incorporated , though it depends on the required oscillation frequency range. When a low frequency is required, connect a frequency divider circuit to the output terminal 216,
If the system is oscillated at a high frequency, C 1 will also have a small capacity and integration into an integrated circuit will be easy.
【００１６】以上述べた様に本発明によれば高精度部品
を用いることなくきわめて安定な電圧制御発振回路を実
現できる。高精度の部品を用いる必要が無いから半導体
集積回路化がきわめて容易となり実装上、製造上のメリ
ットが大きい。As described above, according to the present invention, an extremely stable voltage controlled oscillator circuit can be realized without using high precision parts. Since it is not necessary to use high-precision parts, it is extremely easy to form a semiconductor integrated circuit, and there are great advantages in terms of mounting and manufacturing.
【００１７】本発明による例（図１，２）と従来例（図
３，４）を比較すると本発明の方がかなり複雑になって
おり従来例に比較してあまりメリットが無い様に思われ
るかも知れない。しかし事実は逆なのであって半導体集
積回路上に図２の回路を構成する場合そのチップ上に占
める面積はわずかである。図４の従来例の様に外付部品
を必要とするときは半導体集積回路上のボンディングパ
ッドの面積や出力トランジスタ（例えば図４のコンデン
サＣ1（外付）を駆動するＰ4，Ｐ5，Ｎ2，Ｎ3、抵抗
Ｒ1，Ｒ2（外付）を駆動するＰ1，Ｎ1）に大きなものが
必要となりそれ等の占める面積の方が本発明の回路に比
べはるかに大きくなっているのである。また本発明では
水晶発振回路の様な安定な発振回路を必要とするが、通
常大規模集積回路では電圧制御発振回路の他に安定な基
準パルス列が必要な場合が多く、これと共用すれば良い
ので本発明を実施するにあたって障害とはならない。ま
た本発明では図１のノード１１６または１１７、図２の
ノード２１８，２１９に直列な分周回路または周波数変
換回路を入れ、その分周比等を論理回路で制御すること
により同一の回路で任意にフリーラン周波数を設定する
ことができる。Comparing the example according to the present invention (FIGS. 1 and 2) with the conventional example (FIGS. 3 and 4), the present invention is considerably complicated, and it seems that there is not much advantage compared with the conventional example. May. However, the fact is the opposite, and when the circuit of FIG. 2 is formed on the semiconductor integrated circuit, the area occupied on the chip is small. When external parts are required as in the conventional example of FIG. 4, the area of the bonding pad on the semiconductor integrated circuit and the output transistor (for example, P 4 , P 5 , which drives the capacitor C 1 (external) of FIG. 4), N 2 and N 3 and resistors R 1 and R 2 (external) for driving P 1 and N 1 are required to be large, and the area occupied by them is much larger than that of the circuit of the present invention. Is there. Further, although the present invention requires a stable oscillation circuit such as a crystal oscillation circuit, a large-scale integrated circuit usually requires a stable reference pulse train in addition to the voltage controlled oscillation circuit, and it may be used together with this. Therefore, it does not hinder the implementation of the present invention. Further, in the present invention, a serial frequency dividing circuit or frequency converting circuit is inserted in the node 116 or 117 in FIG. 1 or the nodes 218 and 219 in FIG. 2 and the frequency dividing ratio and the like are controlled by a logic circuit so that the same circuit can be used. You can set the free-run frequency to.
【００１８】[0018]
【発明の効果】この様に本発明は集積回路の容易な電圧
制御発振回路を安定化する方法を示し、デジタル集積回
路にも容易に組込める電圧制御発振回路を示した。本発
明を実施すればコスト、実装スペースを減少でき機器を
実現していく上で大いに貢献できる。As described above, the present invention shows a method for stabilizing an easy voltage controlled oscillator circuit of an integrated circuit, and a voltage controlled oscillator circuit which can be easily incorporated in a digital integrated circuit. By implementing the present invention, the cost and the mounting space can be reduced, and it can greatly contribute to the realization of equipment.
【図１】[Figure 1]
【図２】本発明の実施例を示す図。FIG. 2 is a diagram showing an embodiment of the present invention.
【図３】[Figure 3]
【図４】従来の電圧制御発振回路を示す図である。FIG. 4 is a diagram showing a conventional voltage controlled oscillator circuit.
１０１，２０１…第１の信号合成回路 １０３，２０３…第２の信号合成回路 １０２，２０２…第１の電圧制御発振回路 １０４，２０４…第２の電圧制御発振回路 １０６，２０８…位相比較回路 １０５，２１７…ローパスフィルタ １０７，２１１…基準周波数発振回路 １０９，２１２…第１の信号合成回路の第１の入力端
子。制御端子 １１０，２１４…第１の信号合成回路の第２の入力端子 １１１，２１３…第２の信号合成回路の第１の入力端子 １１２，２１５…第２の信号合成回路の第２の入力端子 １１３，２１６…出力端子101, 201 ... First signal synthesizing circuit 103, 203 ... Second signal synthesizing circuit 102, 202 ... First voltage controlled oscillation circuit 104, 204 ... Second voltage controlled oscillation circuit 106, 208 ... Phase comparison circuit 105 , 217 ... Low-pass filter 107, 211 ... Reference frequency oscillation circuit 109, 212 ... First input terminal of first signal combining circuit. Control terminals 110, 214 ... Second input terminals of first signal combining circuit 111, 213 ... First input terminals of second signal combining circuit 112, 215 ... Second input terminals of second signal combining circuit 113, 216 ... Output terminals
Claims (1)
れる第１の電圧制御発振器を備え入力信号に同期する第
１の位相固定ループと、前記第１の電圧制御発振器と同
等の特性を有し第２の合成信号により発振周波数が制御
される第２の電圧制御発振器を備え基準信号に同期する
第２の位相固定ループとを備える電圧制御発振回路にお
いて、 第１の制御信号と前記第２の位相固定ループ内で発生さ
れる前記第２の電圧制御発振器の出力と前記基準信号を
同期化させるために前記第２の位相固定ループ内で発生
される第２の制御信号とをそれぞれ電流に変換して加算
し前記第１の合成信号を出力する第１の信号加算回路
と、 前記第２の制御信号と基準電圧とをそれぞれ電流に変換
して加算し前記第２の合成信号を出力する第２の信号加
算回路とを有し、 前記第２の制御信号は前記第２の位相固定ループを構成
するローパスフィルタの出力であること を特徴とする電
圧制御発振回路。 1. An oscillation frequency is controlled by a first composite signal.
A first voltage controlled oscillator that is synchronized with the input signal
1 phase-locked loop and the same as the first voltage-controlled oscillator.
Oscillation frequency is controlled by the second composite signal with characteristics such as
With a second voltage controlled oscillator synchronized to a reference signal
In a voltage controlled oscillator circuit including a second phase locked loop
There are, generated of the first control signal and in the second phase locked loop
The output of the second voltage controlled oscillator and the reference signal
Occurs in the second phase-locked loop to synchronize
Second control signal is converted to current and added
And a first signal adding circuit for outputting the first combined signal
And converting the second control signal and the reference voltage into currents, respectively.
A second signal adder for adding and outputting the second combined signal.
An arithmetic circuit, and the second control signal constitutes the second phase-locked loop.
A voltage-controlled oscillator circuit characterized by being the output of a low-pass filter .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3018748A JPH0770999B2 (en) | 1991-02-12 | 1991-02-12 | Voltage controlled oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3018748A JPH0770999B2 (en) | 1991-02-12 | 1991-02-12 | Voltage controlled oscillator |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57136684A Division JPS5927615A (en) | 1982-08-05 | 1982-08-05 | Voltage controlled oscillating circuit |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8155247A Division JP2737747B2 (en) | 1996-06-17 | 1996-06-17 | Voltage controlled oscillator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04211519A JPH04211519A (en) | 1992-08-03 |
| JPH0770999B2 true JPH0770999B2 (en) | 1995-07-31 |
Family
ID=11980274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3018748A Expired - Lifetime JPH0770999B2 (en) | 1991-02-12 | 1991-02-12 | Voltage controlled oscillator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770999B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4131861A (en) * | 1977-12-30 | 1978-12-26 | International Business Machines Corporation | Variable frequency oscillator system including two matched oscillators controlled by a phase locked loop |
| JPS5924191Y2 (en) * | 1979-07-13 | 1984-07-18 | 三洋電機株式会社 | Synthesizer-receiver AFC circuit |
| ES8306299A1 (en) * | 1980-02-28 | 1982-09-01 | Gen Electric | Frequency converter and phase locked loop circuit |
-
1991
- 1991-02-12 JP JP3018748A patent/JPH0770999B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04211519A (en) | 1992-08-03 |
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