JPH0770651B2 - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH0770651B2 JPH0770651B2 JP4320873A JP32087392A JPH0770651B2 JP H0770651 B2 JPH0770651 B2 JP H0770651B2 JP 4320873 A JP4320873 A JP 4320873A JP 32087392 A JP32087392 A JP 32087392A JP H0770651 B2 JPH0770651 B2 JP H0770651B2
- Authority
- JP
- Japan
- Prior art keywords
- package
- groove
- semiconductor
- chip
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体パッケージに関
し、特に半導体チップを封止するパッケージの構造に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a package structure for encapsulating a semiconductor chip.
【０００２】[0002]
【従来の技術】従来の半導体パッケージは、図５に示す
ように、ヒートシンク２と一体に形成されたヘッダー３
上に溝１を設け、半導体チップ４と溝１とが重複するよ
うにソルダー５を用いて固着している（例えば、実開昭
５９−１０７１５７号公報）。2. Description of the Related Art A conventional semiconductor package has a header 3 integrally formed with a heat sink 2, as shown in FIG.
The groove 1 is provided on the upper side, and the semiconductor chip 4 and the groove 1 are fixed to each other by using the solder 5 (for example, Japanese Utility Model Laid-Open No. 59-107157).
【０００３】また、図６（Ａ），（Ｂ）に示すように、
半導体チップ４を搭載するキャビティ７内に中央部より
各コーナー部に向かって傾斜した溝１、あるいは各コー
ナー部の溝終端部に一段低く、且つ広い溝を設けること
により、応力が半導体チップ４のコーナーに集中するこ
とを防いでいる（例えば、実開平２−１０１５３５号公
報）。前述２例はいずれも半導体チップ搭載部に溝を設
けている。Further, as shown in FIGS. 6 (A) and 6 (B),
By providing a groove 1 inclined from the central portion toward each corner portion or a groove end portion of each corner portion having a lower and wider groove in the cavity 7 in which the semiconductor chip 4 is mounted, stress of the semiconductor chip 4 is reduced. It is prevented from concentrating on the corner (for example, Japanese Utility Model Laid-Open No. 2-101535). In each of the above two examples, a groove is provided in the semiconductor chip mounting portion.
【０００４】半導体チップ搭載部以外にも溝を設けた従
来技術は図７に示すように金属平板８の表面のみに溝１
を設けている（例えば実開平２−１３７０４７号公
報）。In the prior art in which a groove is provided in addition to the semiconductor chip mounting portion, the groove 1 is formed only on the surface of the metal flat plate 8 as shown in FIG.
Is provided (for example, Japanese Utility Model Laid-Open No. 2-137047).
【０００５】[0005]
【発明が解決しようとする課題】この従来の溝を設けた
半導体パッケージでは、半導体チップ搭載部のみに溝を
設けた場合、パッケージの使用温度環境が大幅に変化し
た時、パッケージ全体に熱応力が発生した状態では、パ
ッケージ全体に起こる反りを抑えられない。そのため、
半導体チップ以外の部材にも熱膨張係数の差によって発
生する熱ストレスがかかって、クラックが発生するとい
う問題点があった。In this conventional semiconductor package having a groove, when the groove is provided only in the semiconductor chip mounting portion, thermal stress is applied to the entire package when the operating temperature environment of the package changes significantly. When it occurs, the warpage that occurs in the entire package cannot be suppressed. for that reason,
There has been a problem in that members other than the semiconductor chip are also subjected to thermal stress caused by the difference in thermal expansion coefficient and cracks are generated.
【０００６】また、前述した反りは、パッケージ表面の
チップ搭載部のみならず裏面にも発生し、パッケージの
電気信号入出力部のセラミックのクラックを引き起こす
という問題点があった。Further, there is a problem that the above-mentioned warpage occurs not only on the chip mounting portion on the front surface of the package but also on the back surface thereof, which causes cracks in the ceramic of the electric signal input / output portion of the package.
【０００７】本発明の目的は、パッケージ周囲の熱環境
の変化によって発生する熱応力によるパッケージの反り
を低く抑えた半導体パッケージを提供することにある。An object of the present invention is to provide a semiconductor package in which the warpage of the package due to the thermal stress generated by the change in the thermal environment around the package is suppressed.
【０００８】[0008]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体パッケージは、溝を有する半導
体チップ搭載用の半導体パッケージであって、溝は、パ
ッケージのチップ搭載面及び部品搭載面以外の表裏面に
設けられ、パッケージ全体に加わる応力を分散させるも
のである。In order to achieve the above object, a semiconductor package according to the present invention is a semiconductor package for mounting a semiconductor chip having a groove, the groove being a chip mounting surface and a component mounting surface of the package. It is provided on the front and back surfaces except for the purpose of dispersing the stress applied to the entire package.
【０００９】また、溝を有する半導体チップ搭載用の半
導体パッケージであって、溝は、パッケージのチップ搭
載面及び部品搭載面及びパッケージの裏面に設けられ、
チップ及び部品とパッケージとの間に加わる応力，パッ
ケージ全体に加わる応力を分散させるものである。Further, in a semiconductor package for mounting a semiconductor chip having a groove, the groove is provided on a chip mounting surface of the package, a component mounting surface and a back surface of the package,
It disperses the stress applied between the chip and components and the package, and the stress applied to the entire package.
【００１０】また、溝を有する半導体チップ搭載用の半
導体パッケージであって、溝は、パッケージにおける半
導体チップ以外の基板及び部品の搭載面に設けられ、基
板及び部品とパッケージとの間に加わる応力を分散させ
るものである。Further, in a semiconductor package for mounting a semiconductor chip having a groove, the groove is provided on a mounting surface of a substrate and a component other than the semiconductor chip in the package, and stress applied between the substrate and the component and the package is applied. It is to disperse.
【００１１】また、半導体チップ以外の基板及び部品が
ソルダーで接合される半導体パッケージであって、ソル
ダーは、パッケージにメッシュ状に塗布され、その形状
を保った状態で基板及び部品をパッケージに接合し、基
板及び基板とパッケージ間に加わる応力を分散させるも
のである。Further, in a semiconductor package in which substrates and components other than semiconductor chips are joined by a solder, the solder is applied to the package in a mesh shape, and the substrate and components are joined to the package while maintaining its shape. The stress applied between the substrate and the substrate and the package is dispersed.
【００１２】[0012]
【作用】パッケージのチップ搭載面以外のパッケージの
表裏面に溝が設けられており、この溝により、パッケー
ジの反りを抑える。Function: Grooves are provided on the front and back surfaces of the package other than the chip mounting surface of the package, and the groove suppresses warpage of the package.
【００１３】[0013]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【００１４】（実施例１）図１は、本発明の実施例１を
示す図である。(Embodiment 1) FIG. 1 is a diagram showing Embodiment 1 of the present invention.
【００１５】図において、ヒートシンク２上にヘッダー
３が一体化して形成され、ヘッダー３上に半導体チップ
４がソルダー５で搭載されている。そして、ヘッダー３
上のチップ搭載部以外の面に溝１が設けられ、かつヒー
トシンク２の裏面に方形の溝１が設けられている。In the figure, a header 3 is integrally formed on a heat sink 2, and a semiconductor chip 4 is mounted on the header 3 by a solder 5. And header 3
The groove 1 is provided on the surface other than the upper chip mounting portion, and the rectangular groove 1 is provided on the back surface of the heat sink 2.
【００１６】本発明によれば、パッケージ全体が熱環境
の変化により反りが発生しても、ヘッダーの反りを溝１
により抑制できるという効果があり、チップクラック等
の問題点を解決できる。According to the present invention, even if the entire package warps due to a change in the thermal environment, the warpage of the header is prevented by the groove 1.
This has the effect that it can be suppressed by, and problems such as chip cracks can be solved.
【００１７】（実施例２）図２は、本発明の実施例２を
示す図である。(Second Embodiment) FIG. 2 is a diagram showing a second embodiment of the present invention.
【００１８】本実施例では、内部整合回路基板或いはチ
ップコンデンサ等のチップ以外の部材を搭載する部材搭
載面であるヒートシンク２と一体化して形成されたヘッ
ダー３上に溝１を設け、溝１が設けられたヘッダー３上
にソルダー５を用いてセラミック基板６を固着させる。
溝１が設けられているため、基板６とヘッダー３との間
には、空間ができ、ヘッダー３と基板６の接触面積が小
さくなり、パッケージの周囲の熱環境が低温になった
時、ヘッダー３と基板６の熱膨張係数の差による収縮差
によって発生する熱応力が分散され、基板６のクラック
を防止できると共に、さらにその原因となるヘッダー３
の反りを抑制できるという効果を有する。In this embodiment, the groove 1 is provided on the header 3 formed integrally with the heat sink 2 which is a member mounting surface for mounting a member other than a chip such as an internal matching circuit board or a chip capacitor. The ceramic substrate 6 is fixed onto the provided header 3 by using the solder 5.
Since the groove 1 is provided, a space is created between the substrate 6 and the header 3, the contact area between the header 3 and the substrate 6 is reduced, and when the thermal environment around the package is low, the header is 3 and the substrate 6 disperse the thermal stress generated by the difference in the contraction due to the difference in the coefficient of thermal expansion between the substrate 3 and the substrate 6, and prevent the header 6 from cracking.
This has the effect of suppressing the warp of the.
【００１９】（実施例３）図３は、本発明の実施例３を
示す図である。(Third Embodiment) FIG. 3 is a diagram showing a third embodiment of the present invention.
【００２０】本実施例では、ヘッダー３には溝を設け
ず、ヘッダー３と基板６（或いはチップ以外のチップコ
ンデンサ等の部品）を固着させるソルダー５をメッシュ
状に塗布し、そのままの形状を保って基板６をヘッダー
３に接合している。したがって、セラミック基板６を固
着した時に溝を設けた時と同様な空間を作ることができ
る。これにより実施例２と同様の効果を有する。In the present embodiment, the header 3 is not provided with a groove, and the solder 5 for fixing the header 3 and the substrate 6 (or a chip capacitor or other component other than the chip) to each other is applied in the form of a mesh to maintain its shape. Board 6 is joined to header 3. Therefore, when the ceramic substrate 6 is fixed, the same space as when the groove is provided can be created. This has the same effect as that of the second embodiment.
【００２１】（実施例４）図４は、本発明の実施例４を
示す図である。(Fourth Embodiment) FIG. 4 is a diagram showing a fourth embodiment of the present invention.
【００２２】本実施例では、ヘッダー３のチップ搭載部
及び部材搭載部に溝１を設け、かつヒートシンク２の裏
面に方形の溝１を設けている。In this embodiment, the groove 1 is provided in the chip mounting portion and the member mounting portion of the header 3, and the rectangular groove 1 is provided on the back surface of the heat sink 2.
【００２３】本実施例によれば、パッケージ全体，チッ
プ搭載部，部材搭載部の反りを抑制でき、それぞれのク
ラックを防止できる。According to this embodiment, the warpage of the entire package, the chip mounting portion, and the member mounting portion can be suppressed, and the cracks in each can be prevented.
【００２４】[0024]
【発明の効果】以上説明したように本発明は、半導体チ
ップ搭載部以外の面とパッケージ裏面に溝を設けること
により、またチップ以外の内部整合回路基板，チップコ
ンデンサ等の部材を搭載する面に溝を設け、あるいは部
材をパッケージに固着するソルダーをメッシュ状にする
ことにより、パッケージ周囲の熱環境の変化によって発
生する熱応力によるパッケージの反りを従来の１５０μ
ｍから５０μｍに減少させ、チップ及び部材クラック発
生を防止でき、信頼度を向上できるという効果を有す
る。As described above, according to the present invention, by providing the groove on the surface other than the semiconductor chip mounting portion and the back surface of the package, the surface on which members other than the chip such as the internal matching circuit board and the chip capacitor are mounted is mounted. By providing a groove or using a mesh-like solder for fixing the members to the package, the package warpage due to the thermal stress generated by the change in the thermal environment around the package can be reduced to 150 μm.
m to 50 μm, chip and member cracking can be prevented, and reliability can be improved.
【図１】本発明の実施例１を示す図であり、（Ａ）は
（Ｂ），（Ｃ）のＡ−Ａ’線断面図、（Ｂ）は同平面
図、（Ｃ）は同裏面図である。1A and 1B are views showing a first embodiment of the present invention, in which FIG. 1A is a sectional view taken along line AA ′ of FIGS. 1B and 1C, FIG. It is a figure.
【図２】本発明の実施例２を示す図であり、（Ａ）は
（Ｂ）のＢ−Ｂ’線断面図、（Ｂ）は同平面図である。2A and 2B are views showing a second embodiment of the present invention, in which FIG. 2A is a sectional view taken along line BB ′ in FIG. 2B, and FIG.
【図３】本発明の実施例３を示す図であり、（Ａ）はソ
ルダーの塗布状態を示す平面図、（Ｂ）は搭載状態を示
す側面図である。3A and 3B are views showing a third embodiment of the present invention, in which FIG. 3A is a plan view showing a solder coating state, and FIG. 3B is a side view showing a mounting state.
【図４】本発明の実施例４を示す図であり、（Ａ）は平
面図、（Ｂ）は断面図である。4A and 4B are views showing a fourth embodiment of the present invention, in which FIG. 4A is a plan view and FIG. 4B is a sectional view.
【図５】従来例を示す断面図である。FIG. 5 is a cross-sectional view showing a conventional example.
【図６】従来例を示す図であり、（Ａ）は（Ｂ）のＣ−
Ｃ’線断面図、（Ｂ）は同平面図である。FIG. 6 is a diagram showing a conventional example, in which (A) is C- of (B).
C'line sectional drawing, (B) is the same top view.
【図７】従来例を示す断面図である。FIG. 7 is a cross-sectional view showing a conventional example.
１ 溝 ２ ヒートシンク ３ ヘッダー ４ 半導体チップ ５ ソルダー ６ セラミック基板 ７ キャビティ ８ 金属平板 1 groove 2 heat sink 3 header 4 semiconductor chip 5 solder 6 ceramic substrate 7 cavity 8 metal flat plate
Claims (4)
パッケージであって、 溝は、パッケージのチップ搭載面及び部品搭載面以外の
表裏面に設けられ、パッケージ全体に加わる応力を分散
させるものであることを特徴とする半導体パッケージ。1. A semiconductor package for mounting a semiconductor chip having a groove, wherein the groove is provided on the front and back surfaces other than the chip mounting surface and the component mounting surface of the package to disperse stress applied to the entire package. A semiconductor package characterized by the above.
パッケージであって、 溝は、パッケージのチップ搭載面及び部品搭載面及びパ
ッケージの裏面に設けられ、チップ及び部品とパッケー
ジとの間に加わる応力，パッケージ全体に加わる応力を
分散させるものであることを特徴とする半導体パッケー
ジ。2. A semiconductor package for mounting a semiconductor chip having a groove, wherein the groove is provided on a chip mounting surface of the package, a component mounting surface and a back surface of the package, and stress applied between the chip and the component and the package. , A semiconductor package characterized by dispersing stress applied to the entire package.
パッケージであって、 溝は、パッケージにおける半導体チップ以外の基板及び
部品の搭載面に設けられ、基板及び部品とパッケージと
の間に加わる応力を分散させるものであることを特徴と
する半導体パッケージ。3. A semiconductor package for mounting a semiconductor chip having a groove, wherein the groove is provided on a mounting surface of a substrate and a component other than the semiconductor chip in the package, and stress applied between the substrate and the component and the package is provided. A semiconductor package characterized by being dispersed.
ダーで接合される半導体パッケージであって、 ソルダーは、パッケージにメッシュ状に塗布され、その
形状を保った状態で基板及び部品をパッケージに接合
し、基板及び基板とパッケージ間に加わる応力を分散さ
せるものであることを特徴とする半導体パッケージ。4. A semiconductor package in which a substrate and components other than a semiconductor chip are bonded by a solder, wherein the solder is applied to the package in a mesh shape, and the substrate and the component are bonded to the package while maintaining the shape. A semiconductor package which disperses stress applied between the substrate and the substrate and the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4320873A JPH0770651B2 (en) | 1992-11-30 | 1992-11-30 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4320873A JPH0770651B2 (en) | 1992-11-30 | 1992-11-30 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06169037A JPH06169037A (en) | 1994-06-14 |
| JPH0770651B2 true JPH0770651B2 (en) | 1995-07-31 |
Family
ID=18126219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4320873A Expired - Fee Related JPH0770651B2 (en) | 1992-11-30 | 1992-11-30 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770651B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4678941B2 (en) * | 2000-12-14 | 2011-04-27 | 日本インター株式会社 | Composite semiconductor device |
| JP4467380B2 (en) | 2004-08-10 | 2010-05-26 | 富士通株式会社 | Semiconductor package, printed circuit board on which semiconductor package is mounted, and electronic apparatus having such printed circuit board |
| JP4637671B2 (en) * | 2005-07-15 | 2011-02-23 | 京セラ株式会社 | Ceramic laminate and gas sensor including the same |
| JP4957163B2 (en) * | 2006-10-10 | 2012-06-20 | 株式会社村田製作所 | Composite parts |
-
1992
- 1992-11-30 JP JP4320873A patent/JPH0770651B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06169037A (en) | 1994-06-14 |
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