JPH0758676A - Adaptive maximum likelihood series estimating device - Google Patents
Adaptive maximum likelihood series estimating deviceInfo
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- JPH0758676A JPH0758676A JP5202294A JP20229493A JPH0758676A JP H0758676 A JPH0758676 A JP H0758676A JP 5202294 A JP5202294 A JP 5202294A JP 20229493 A JP20229493 A JP 20229493A JP H0758676 A JPH0758676 A JP H0758676A
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ディジタル通信の受信
機等において、伝送路の歪みを補償し正しい送信信号を
得る等化器等に用いられる適応最尤系列推定器、特に搬
送波の周波数オフセットによる位相変動を補償しながら
等化を行う位相補償型適応等化器等に適用される適応最
尤系列推定器に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive maximum likelihood sequence estimator used in an equalizer or the like for compensating for distortion of a transmission line to obtain a correct transmission signal in a receiver for digital communication, and more particularly, a carrier frequency offset. The present invention relates to an adaptive maximum likelihood sequence estimator applied to a phase compensation type adaptive equalizer or the like that performs equalization while compensating for the phase fluctuation due to.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
例えば次のような文献に記載されるものがあった。 文献；アイイーイーイー トランスアクション オン
コミュニケーションズ（IEEE Transaction on Communic
ations）、ＣＯＭ−２２［５］（1974-5）（米）Ｇ．Ｕ
ｎｇｅｒｂｏｅｃｋ“アダプティブ マキシマム−ライ
クリフッド レシーバ フォア キャリイ−モデュレイ
ティッド データ−トランスミッション システムズ(A
daptive Maximum-LikelihoodReceiver for Carrier-Mod
ulated Data-Transmission Systems)”Ｐ．６２４−６
３６ 近年、ディジタル移動通信の開発が急速に行われている
が、陸上移動通信では遅延を伴なう多数の干渉波と移動
端末が高速に移動することによって周波数選択性フェー
ジングが発生し、受信信号波形が著しく歪むため、等化
器によってこの歪みを補償する必要がある。この等化器
に適用される最尤系列推定は、周波数選択性フェージン
グのように、伝送路の遅延特性に起因して歪んだ受信信
号波形から、正しい送信データを得るための最も有効な
等化方式の一つである。2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Literature; IEE TRANSACTION ON
Communications (IEEE Transaction on Communic
ations), COM-22 [5] (1974-5) (US) G.I. U
ngerboeck "Adaptive Maximum-Like Lifted Receiver Fore Carry-Modulated Data-Transmission Systems (A
daptive Maximum-Likelihood Receiver for Carrier-Mod
Calculated Data-Transmission Systems) "P.624-6
36 In recent years, digital mobile communication has been rapidly developed, but in land mobile communication, a large number of interfering waves with delays and high-speed movement of mobile terminals cause frequency-selective fading, resulting in reception signals. Since the waveform is significantly distorted, it is necessary to compensate for this distortion by the equalizer. The maximum likelihood sequence estimation applied to this equalizer is the most effective equalization for obtaining correct transmission data from the received signal waveform distorted due to the delay characteristic of the transmission line, such as frequency selective fading. This is one of the methods.
【０００３】図２は、従来のディジタル移動通信におけ
る送受信機の構成例を示すブロック図である。この送受
信機は、入力データｂmに基づき信号ｓc（ｔ）を送信す
る送信機１０を有し、該信号ｓc(ｔ）が伝送路２０を介
して受信機３０に受信されるようになっている。送信機
１０は、符号化器１１、送信ローパスフィルタ（以下、
送信ＬＰＦという）１２、及び変調器１３より構成され
ている。また、受信機３０は、復調器３１、受信ローパ
スフィルタ（以下、受信ＬＰＦという）３２、適応等化
器３３、及び復号器３４より構成されている。送信機１
０では、入力データｂmを符号化器１１で送信シンボル
ｘnに変換し、送信ＬＰＦ１２により帯域制限して送信
複素ベースバンド信号ｓ（ｔ）を生成し、変調器１３へ
送る。変調器１３では、信号ｓ（ｔ)を周波数ｆcなる搬
送波によって変調し、信号ｓc(ｔ）を伝送路２０を介し
て受信機３０へ送信する。受信機３０では、復調器３１
で送信搬送波周波数ｆc と等しい周波数によって同期検
波を行い、伝送路２０を通った信号ｒc(ｔ）を複素ベー
スバンド信号ｒ（ｔ）に変換し、さらに受信ＬＰＦ３２
を通して帯域制限された受信複素ベースバンド信号ｙ
（ｔ）を得る。この信号ｙ（ｔ）をシンボル間隔Ｔでサ
ンプリングする。適応等化器３３では、信号ｙ（ｔ)の
サンプル値ｙnから周波数選択性フェージングによる伝
送路２０の特性を補償し、送信シンボルを推定する。こ
こで、送信搬送波周波数と受信機３０の復調周波数の周
波数オフセットや位相ジッタにより、受信信号の位相が
変動するので、適応等化器３３は、最尤系列推定によ
り、受信信号の位相変動を補償しながら送信シンボルの
推定を行う。最後に、復号器３４で送信シンボルの推定
値ＥＸn(但し、Ｅは推定を表す）を復号し、送信された
データＥｂm を得る。最尤系列推定は、ある有限区間で
の受信信号系列ＶＹN＝｛ｙ1，ｙ2，…，ｙN}(但し、Ｖ
はベクトルを表す）が得られたときに、伝送路２０のイ
ンパルス応答ｈ（ｔ)を既知としてＶＹNを実現する確率
（尤度）の最も大きい送信シンボル系列ＶＸN＝｛ｘ1，
ｘ2，…，ｘN｝を推定するものであり、前記文献に記載
されているように、畳み込み符号の復号法として知られ
るビタビ・アルゴリズムを用いて効率的に計算される。FIG. 2 is a block diagram showing an example of the configuration of a transceiver in conventional digital mobile communication. The transceiver includes a transmitter 10 for transmitting a signal s c (t) on the basis of input data b m, as the signal s c (t) is received by the receiver 30 via the transmission path 20 Has become. The transmitter 10 includes an encoder 11, a transmission low-pass filter (hereinafter,
The transmission LPF) 12 and the modulator 13. The receiver 30 includes a demodulator 31, a reception low-pass filter (hereinafter referred to as reception LPF) 32, an adaptive equalizer 33, and a decoder 34. Transmitter 1
At 0, the input data b m is converted into the transmission symbol x n by the encoder 11, the band is limited by the transmission LPF 12, and the transmission complex baseband signal s (t) is generated and sent to the modulator 13. The modulator 13 modulates the signal s (t) with a carrier having a frequency f c , and transmits the signal s c (t) to the receiver 30 via the transmission line 20. In the receiver 30, the demodulator 31
At the same time, synchronous detection is performed at a frequency equal to the transmission carrier frequency f c , the signal r c (t) that has passed through the transmission line 20 is converted into a complex baseband signal r (t), and the reception LPF 32
Received complex baseband signal y band-limited through
Get (t). This signal y (t) is sampled at symbol intervals T. The adaptive equalizer 33 compensates the characteristics of the transmission line 20 due to frequency selective fading from the sample value y n of the signal y (t) and estimates the transmission symbol. Here, since the phase of the received signal changes due to the frequency offset and the phase jitter of the transmission carrier frequency and the demodulation frequency of the receiver 30, the adaptive equalizer 33 compensates the phase fluctuation of the received signal by the maximum likelihood sequence estimation. While estimating the transmitted symbols. Finally, the decoder 34 decodes the estimated value EX n of the transmission symbol (where E represents the estimation) to obtain the transmitted data Eb m . Maximum likelihood sequence estimation is performed by using a received signal sequence VY N = {y 1 , y 2 , ..., Y N } (where V
Is a vector), the transmission symbol sequence VX N = {x 1 , where the probability (likelihood) of realizing VY N is the highest with the impulse response h (t) of the transmission line 20 known.
x 2 , ..., X N } is estimated, and is efficiently calculated using the Viterbi algorithm known as a decoding method of a convolutional code, as described in the above-mentioned document.
【０００４】図３は、図２中の適応等化器３３に適応さ
れる従来の適応最尤系列推定器の機能ブロック図であ
る。この適応最尤系列推定器は、例えば、ディジタル・
シグナル・プロセッサ（以下、ＤＳＰという）を用いた
プログラム制御等により構成されるもので、位相回転部
４０、遅延手段５０、ビタビ・アルゴリズム処理部６
０、伝送路推定部７０、及び位相推定部８０を備えてい
る。なお、各機能ブロック間を接続する実線は実数、一
点鎖線は複素数、二点鎖線は複素ベクトルをそれぞれ表
す。位相回転部４０は、位相推定値Ｅφnに基づき、受
信信号のサンプル値Ｙnを位相回転させて周波数オフセ
ットや位相ジッタによる位相変動を補償した受信信号の
サンプル値ｃｒn(但し、ｃは補償を表す）を出力する機
能を有し、演算手段４１及び乗算手段４２より構成され
ている。遅延手段５０は、ビタビ・アルゴリズムの判定
遅延を補償するためのもので、受信信号のサンプル値ｃ
ｒn を所定時間遅延し、その遅延した値ｃｒn-M を伝送
路推定部７０及び位相推定部８０へ与える機能を有して
いる。ビタビ・アルゴリズム処理部６０は、サンプル値
ｃｒn を入力し、伝送路推定部７０からの伝送路２０の
インパルス応答推定値Ｅｈj(ｊ＝０，１，…，Ｌ）に基
づき、ビタビ・アルゴリズムに従って送信シンボルの推
定を行い、推定送信シンボル系列ＥＸn-M を出力する機
能を有している。FIG. 3 is a functional block diagram of a conventional adaptive maximum likelihood sequence estimator adapted to the adaptive equalizer 33 in FIG. This adaptive maximum likelihood sequence estimator is, for example, a digital
It is configured by program control using a signal processor (hereinafter referred to as DSP), and includes a phase rotation unit 40, a delay unit 50, a Viterbi algorithm processing unit 6.
0, the transmission path estimation unit 70, and the phase estimation unit 80. A solid line connecting the functional blocks represents a real number, a one-dot chain line represents a complex number, and a two-dot chain line represents a complex vector. The phase rotation unit 40 phase-rotates the sample value Y n of the received signal based on the estimated phase value Eφ n to compensate the phase variation due to the frequency offset and the phase jitter cr n (where c is the compensation value). Which has a function of outputting), and is composed of a calculation means 41 and a multiplication means 42. The delay means 50 is for compensating the decision delay of the Viterbi algorithm, and is a sample value c of the received signal.
It has a function of delaying r n for a predetermined time and giving the delayed value cr nM to the transmission path estimation unit 70 and the phase estimation unit 80. The Viterbi algorithm processing unit 60 inputs the sample value cr n, and based on the impulse response estimation value Eh j (j = 0, 1, ..., L) of the transmission path 20 from the transmission path estimation unit 70, the Viterbi algorithm processing unit 60. The transmission symbol is estimated in accordance with the above, and the estimated transmission symbol sequence EX nM is output.
【０００５】伝送路推定部７０では、実際の伝送路２０
のインパルス応答が未知であるため、それを推定して伝
送路のインパルス応答推定値Ｅｈj をビタビ・アルゴリ
ズム処理部６０へ与える機能を有し、受信信号再生手段
７１、インパルス応答適応更新手段７２、及び減算手段
７３より構成されている。In the transmission path estimation unit 70, the actual transmission path 20
Since the impulse response is unknown, it has a function of estimating it and giving the impulse response estimation value Eh j of the transmission path to the Viterbi algorithm processing section 60. The reception signal reproducing means 71, the impulse response adaptive updating means 72, And subtraction means 73.
【０００６】受信信号再生手段７１では、推定送信シン
ボル系列｛ＥＸn，ＥＸn-1，…，ＥＸn-L｝と伝送路２
０のインパルス応答推定値Ｅｈjとから、次式（１）の
ような受信信号の推定値Ｅｒn を発生する。In the received signal reproducing means 71, the estimated transmission symbol sequence {EX n , EX n-1 , ..., EX nL } and the transmission line 2 are used.
From the impulse response estimation value Eh j of 0, the estimation value Er n of the received signal is generated as in the following equation (1).
【数１】 これを減算手段７３で、次式（２）のように、位相変動
を補償した受信信号ｃｒnから差し引いて誤差信号ｅnを
得る。 ｅn＝ｃｒn−Ｅｒn ・・・（２） インパルス応答適応更新手段７２では、次式（３）で示
されるＬＭＳ（リースト・ミーン・スケヤーズ）アルゴ
リズムにより、伝送路２０のインパルス応答推定値Ｅｈ
j を更新する。 Ｅｈj n+1＝Ｅｈj n＋β・ｅn・ＥＸ* n-j ・・・（３） 但し、ｊ＝０，１，…，Ｌ *；複素共役 β；ステップサイズと呼ばれる正の定数 位相推定部８０は、周波数オフセットや位相ジッタによ
る位相変動量を次式（４）により推定し、その位相推定
値Ｅφn+1 を位相回転部４０へ与え、該位相回転部４０
でその位相変動量を補償させるように働く。 Ｅφn+1＝Ｅφn＋α・Ｉｍ［ｅn・ｃｒ* n］ ・・・（４） 但し、Ｉｍ［ ］；複素数の虚数部 α；正の定数 位相推定部８０及び位相回転部４０による位相変動量の
補償は、１次の位相同期ループと等価である。そのた
め、位相推定部８０は、位相同期ループ（ＰＬＬ）の位
相誤差検出回路８１、ループフィルタ８２、及び電圧制
御発振器（以下、ＶＣＯという）８３より構成されてい
るといえる。位相誤差検出回路８１は、遅延手段５０の
出力ｃｒn-M からその複素共役ｃｒ* n-Mを求める複素共
役算出手段８１ａと、複素共役ｃｒ* n-Mと推定誤差ｅ
n-M とを乗算する乗算手段８１ｂと、その乗算結果より
虚数部を抽出して位相誤差△φn を出力する虚数部抽出
手段８１ｃとで、構成されている。ループフィルタ８２
は、位相誤差△φn に対して乗数αを乗算する乗算手段
８２ａで構成されている。ＶＣＯ８３は、乗算手段８２
ａの出力に対して前の時刻の位相推定値Ｅφn-1を加算
する加算手段８３ａと、該加算手段８３ａの出力を遅延
するレジスタ等の遅延手段８３ｂとで、構成されてい
る。[Equation 1] This is subtracted by the subtraction means 73 from the received signal cr n in which the phase fluctuation is compensated, as in the following equation (2), to obtain the error signal e n . e n = cr n -Er the n · · · (2) the impulse response adaptive update means 72, by LMS (Least Mean Sukeyazu) algorithm represented by the following formula (3), the impulse response estimate Eh of the transmission line 20
Update j . Eh j n + 1 = Eh j n + β · e n · EX * nj ··· (3) where, j = 0,1, ..., L *; positive constant phase estimator called step size; complex conjugate beta The reference numeral 80 estimates the phase fluctuation amount due to the frequency offset and the phase jitter by the following equation (4), gives the phase estimation value Eφ n + 1 to the phase rotation unit 40, and the phase rotation unit 40
Works to compensate for the amount of phase fluctuation. Eφ n + 1 = Eφ n + α · Im [e n · cr * n] ··· (4) where, Im []; the imaginary part of the complex alpha; positive constant phase estimator 80 and phase by the phase rotation section 40 The fluctuation compensation is equivalent to a first-order phase locked loop. Therefore, it can be said that the phase estimation unit 80 includes a phase error detection circuit 81 of a phase locked loop (PLL), a loop filter 82, and a voltage controlled oscillator (hereinafter, referred to as VCO) 83. Phase error detecting circuit 81, a complex conjugate calculation unit 81a for obtaining the complex conjugate cr * nM from the output cr nM delay means 50, the complex conjugate cr * nM and the estimated error e
It is composed of a multiplication means 81b for multiplying by nM and an imaginary part extraction means 81c for extracting an imaginary part from the multiplication result and outputting a phase error Δφ n . Loop filter 82
Is composed of a multiplication means 82a for multiplying the phase error Δφ n by a multiplier α. The VCO 83 is the multiplication means 82.
The addition means 83a adds the phase estimation value Eφ n-1 at the previous time to the output of a, and the delay means 83b such as a register that delays the output of the addition means 83a.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、従来の
適応最尤系列推定器では、位相誤差検出回路８１におい
て位相を補償した受信信号ｃｒnと伝送路２０の誤差信
号ｅnとから位相誤差△Ｅφn を検出している。そのた
め、伝送路推定部７０及び位相推定部８０の推定動作が
十分行われているとき、誤差信号ｅn が非常に小さな値
となり、例えば固定小数点演算のＤＳＰを用いて適応最
尤系列推定器を実現した場合、（４）式においてｅn・
ｃｒnを計算すると、計算精度が悪くなることがあり、
それを解決することが困難であった。本発明は、前記従
来技術が持っていた課題として、伝送路及び位相の推定
動作が十分行われているとき、位相誤差検出に用いる伝
送路の誤差信号が小さな値になるという点について解決
し、例えば固定小数点演算のＤＳＰ等で実現しても、位
相誤差検出の計算精度の劣化しない優れた適応最尤系列
推定器を提供することを目的とする。However, in the conventional adaptive maximum likelihood sequence estimator, the phase error ΔEφ is calculated from the received signal cr n whose phase is compensated in the phase error detection circuit 81 and the error signal e n of the transmission line 20. n is detected. Therefore, when the estimation operations of the transmission path estimation unit 70 and the phase estimation unit 80 are sufficiently performed, the error signal e n has a very small value, and the adaptive maximum likelihood sequence estimator is configured using, for example, a fixed-point arithmetic DSP. When realized, in equation (4), e n ·
When cr n is calculated, the calculation accuracy may deteriorate,
It was difficult to solve it. The present invention solves the problem that the error signal of the transmission path used for phase error detection becomes a small value when the estimation operation of the transmission path and the phase is sufficiently performed as the problem that the above-mentioned conventional technology has. An object of the present invention is to provide an excellent adaptive maximum likelihood sequence estimator that does not deteriorate the calculation accuracy of phase error detection even if it is realized by a DSP of fixed point arithmetic.
【０００８】[0008]
【課題を解決するための手段】第１の発明は、前記課題
を解決するために、位相推定値に基づき受信信号の位相
を回転させて該受信信号の位相変動を補償する位相回転
部と、前記補償後の受信信号を入力し、伝送路のインパ
ルス応答推定値に基づきビタビ・アルゴリズムに従って
送信シンボルの推定を行い、推定送信シンボル系列を出
力するビタビ・アルゴリズム処理部と、伝送路のインパ
ルス応答を推定する伝送路推定部と、受信信号の位相誤
差を検出する位相誤差検出手段を有し、該位相誤差を位
相修正値として位相推定値に加えて新しい前記位相推定
値を前記位相回転部に与える位相推定部とを、備えた適
応最尤系列推定器において、前記位相誤差検出手段を次
のように構成している。ここで、伝送路推定部は、前記
推定送信シンボル系列と前記伝送路のインパルス応答推
定値とから受信信号の推定値を算出する受信信号再生手
段を有し、前記補償後の受信信号から該受信信号の推定
値を差し引いて推定誤差を算出し、該推定誤差及び前記
推定送信シンボル系列に基づき、適応アルゴリズムに従
い伝送路のインパルス応答を更新して新しい前記伝送路
のインパルス応答推定値を前記ビタビ・アルゴリズム処
理部及び受信信号再生手段に与える機能を有している。
そして、本発明の位相誤差検出手段は、前記補償後の受
信信号と前記受信信号の推定値とを用いて前記位相誤差
を検出する構成にしている。第２の発明によれば、第１
の発明の位相誤差検出手段を、前記受信信号の推定値か
らその複素共役を算出する複素共役算出手段と、前記補
償後の受信信号と前記複素共役とを乗算する乗算手段
と、前記乗算手段の乗算結果より虚数部を抽出して位相
誤差を出力する虚数部抽出手段とで、構成している。In order to solve the above-mentioned problems, a first aspect of the invention is to rotate a phase of a received signal based on a phase estimation value to compensate a phase fluctuation of the received signal, and The received signal after the compensation is input, the transmission symbol is estimated according to the Viterbi algorithm based on the impulse response estimation value of the transmission line, and the Viterbi algorithm processing unit that outputs the estimated transmission symbol sequence and the impulse response of the transmission line are output. It has a transmission path estimating unit for estimating and a phase error detecting unit for detecting a phase error of a received signal, and adds the phase error as a phase correction value to the phase estimated value to give the new phase estimated value to the phase rotation unit. In the adaptive maximum likelihood sequence estimator provided with the phase estimating section, the phase error detecting means is configured as follows. Here, the transmission channel estimation unit has a reception signal reproducing means for calculating an estimation value of a reception signal from the estimated transmission symbol sequence and an impulse response estimation value of the transmission channel, and the reception signal is regenerated from the reception signal after the compensation. The estimation value of the signal is subtracted to calculate the estimation error, and the impulse response of the transmission path is updated according to an adaptive algorithm based on the estimation error and the estimated transmission symbol sequence, and a new impulse response estimation value of the transmission path is set to the Viterbi It has a function of giving to the algorithm processing section and the received signal reproducing means.
Then, the phase error detecting means of the present invention is configured to detect the phase error using the received signal after the compensation and the estimated value of the received signal. According to the second invention, the first
The phase error detecting means of the invention comprises a complex conjugate calculating means for calculating a complex conjugate of the received signal from an estimated value, a multiplying means for multiplying the compensated received signal by the complex conjugate, and a multiplying means of the multiplying means. And an imaginary part extracting means for extracting an imaginary part from the multiplication result and outputting a phase error.
【０００９】[0009]
【作用】第１の発明によれば、以上のように適応最尤系
列推定器を構成したので、受信信号が入力されると、そ
の位相変動が位相回転部で補償され、ビタビ・アルゴリ
ズム処理部、伝送路推定部、及び位相推定部へ送られ
る。ビタビ・アルゴリズム処理部では、位相回転部で補
償された受信信号を入力し、伝送路のインパルス応答推
定値に基づき送信シンボルの推定を行って推定送信シン
ボル系列を出力する。伝送路推定部では、前記推定送信
シンボル系列と前記伝送路のインパルス応答推定値とか
ら受信信号の位相変動を推定し、その受信信号の推定値
を位相推定部内の位相誤差検出手段へ送る。位相誤差検
出手段では、位相回転部で補償された受信信号と、伝送
路推定部から与えられる受信信号の推定値とを用いて位
相誤差を検出する。位相推定部では、位相誤差検出手段
で検出された位相誤差を位相修正値として位相推定値に
加えて新しい位相推定値を求めることによって受信信号
の位相変動を推定し、その推定された新しい位相推定値
を位相回転部へ与える。すると、与えられた位相推定値
に基づき、位相回転部が受信信号の位相変動を補償す
る。第２の発明によれば、位相誤差検出手段は、伝送路
推定部から受信信号の推定値が与えられると、その複素
共役を複素共役算出手段で算出する。この複素共役と、
位相回転部で補償された受信信号とが乗算手段で乗算さ
れ、その乗算結果より、虚数部抽出手段で虚数部が抽出
されて位相誤差が出力される。従って、前記課題を解決
できるのである。According to the first aspect of the present invention, the adaptive maximum likelihood sequence estimator is configured as described above. Therefore, when a received signal is input, its phase fluctuation is compensated by the phase rotation unit, and the Viterbi algorithm processing unit is provided. , The transmission path estimation unit and the phase estimation unit. The Viterbi algorithm processing unit inputs the received signal compensated by the phase rotation unit, estimates transmission symbols based on the impulse response estimation value of the transmission path, and outputs an estimated transmission symbol sequence. The transmission path estimation unit estimates the phase fluctuation of the received signal from the estimated transmission symbol sequence and the impulse response estimated value of the transmission path, and sends the estimated value of the received signal to the phase error detection means in the phase estimation unit. The phase error detection means detects a phase error using the received signal compensated by the phase rotation unit and the estimated value of the received signal given from the transmission path estimation unit. The phase estimation unit estimates the phase fluctuation of the received signal by adding the phase error detected by the phase error detection means as a phase correction value to the phase estimation value to obtain a new phase estimation value, and the estimated new phase estimation. Give a value to the phase rotator. Then, the phase rotation unit compensates the phase fluctuation of the received signal based on the given phase estimation value. According to the second aspect of the invention, when the estimated value of the received signal is given from the transmission path estimation unit, the phase error detection unit calculates the complex conjugate thereof by the complex conjugate calculation unit. This complex conjugate and
The received signal compensated by the phase rotation unit is multiplied by the multiplication unit, and the imaginary number extraction unit extracts the imaginary number unit from the multiplication result and outputs the phase error. Therefore, the above problem can be solved.
【００１０】[0010]
【実施例】図１は、本発明の実施例を示す適応最尤系列
推定器の機能ブロック図であり、従来の図３中の要素と
共通の要素には共通の符号が付されている。この適応最
尤系列推定器は、従来と同様、図２に示すディジタル移
動通信における送受信機中の適応等化器３３に適応され
るもので、ＤＳＰ等で構成されている。本実施例の適応
最尤系列推定器では、従来の図３中の伝送路推定部７０
及び位相推定部８０に代えて、構成の異なる伝送路推定
部７０Ａ及び位相推定部８０Ａが設けられている。伝送
路推定部７０Ａは、従来と同様の受信信号再生手段７
１、インパルス応答適応更新手段７２、及び減算手段７
３で構成されているが、減算手段７３で求めた誤差信号
ｅn を位相推定部８０Ａに与えずに、受信信号再生手段
７１で求めた受信信号の推定値Ｅｒn を該位相推定部８
０Ａに与えるようにしている点が従来のものと異なって
いる。また、位相推定部８０Ａは、従来と異なる位相誤
差検出回路８１Ａと、従来と同様のループフィルタ８２
及びＶＣＯ８３とで、構成されている。位相誤差検出回
路８１Ａは、受信信号再生手段７１から与えられる受信
信号の推定値Ｅｒn から複素共役ｃｒ* n-Mを求める複素
共役算出手段８１ａと、該複素共役ｃｒ* n-Mと遅延手段
５０の出力ｃｒn-M とを乗算する乗算手段８１ｂと、該
乗算手段８１ｂの出力から虚数部を抽出して位相誤差△
φn を出力する虚数部抽出手段８１ｃとで、構成されて
いる。ループフィルタ８２は、従来と同様、位相誤差△
φn に対して乗数αを乗算して位相修正量△Ｅφn+1 を
出力する乗算手段で構成されている。ＶＣＯ８３は、従
来と同様、ループフィルタ８２から出力される位相修正
量△Ｅφn+1 に対して前の時刻の位相推定値Ｅφn-1 を
加算する加算手段８３ａと、該加算手段８３ａの出力を
遅延して位相回転部４０へ与える位相推定値Ｅφn を出
力するレジスタ等の遅延手段８３ｂとで、構成されてい
る。1 is a functional block diagram of an adaptive maximum likelihood sequence estimator showing an embodiment of the present invention, in which elements common to those in the conventional FIG. 3 are designated by common reference numerals. This adaptive maximum likelihood sequence estimator is adapted to the adaptive equalizer 33 in the transmitter / receiver in the digital mobile communication shown in FIG. 2 as in the conventional case, and is composed of a DSP or the like. In the adaptive maximum likelihood sequence estimator of the present embodiment, the conventional channel estimation unit 70 in FIG. 3 is used.
Instead of the phase estimation unit 80, a transmission path estimation unit 70A and a phase estimation unit 80A having different configurations are provided. The transmission path estimation unit 70A uses the received signal reproducing means 7 similar to the conventional one.
1, impulse response adaptive updating means 72, and subtracting means 7
Are constituted by 3, subtraction means an error signal e n obtained without giving a phase estimation unit 80A in 73, the received signal reproducing means 71 in said phase estimating section 8 estimates Er n of the received signal obtained
It is different from the conventional one in that it is given to 0A. Further, the phase estimation unit 80A includes a phase error detection circuit 81A different from the conventional one and a loop filter 82 similar to the conventional one.
And VCO 83. Phase error detection circuit 81A, the output of the complex conjugate calculation unit 81a and, complex-conjugated cr * nM and delay means 50 for obtaining the complex conjugate cr * nM from estimates Er n of the received signal supplied from the reception signal reproducing means 71 cr The multiplication means 81b for multiplying by nM and the phase error Δ by extracting the imaginary part from the output of the multiplication means 81b.
and an imaginary part extracting unit 81c that outputs φ n . The loop filter 82 has the same phase error Δ as the conventional one.
It is composed of multiplication means for multiplying φ n by a multiplier α and outputting a phase correction amount ΔEφ n + 1 . The VCO 83 adds the phase correction amount ΔEφ n + 1 output from the loop filter 82 to the phase estimation value Eφ n-1 at the previous time and the output of the addition means 83a, as in the conventional case. And a delay means 83b such as a register for outputting the phase estimation value Eφ n given to the phase rotator 40 after delaying.
【００１１】次に、動作を説明する。例えば、受信信号
のサンプル値ｙn を ｙn＝ｒn・ｅｘｐ［ｊφn］ ・・・（５） のように表す。ここで、φn は周波数オフセットや位相
ジッタによる位相変動量、ｒn はこれらの位相変動がな
い場合の受信信号のサンプル値で、インパルス応答ベク
トルＶｈn、及び送信シンボルベクトルＶＸnを用いて次
式（６）のように表される。 ｒn＝Ｖｈn T・Ｖｘn ・・・（６） 但し、Ｖｈn＝｛ｈ0 n，ｈ1 n，…，ｈL n｝T Ｖｘn＝｛ｘn，ｘn-1，…，ｘn-L｝T T；ベクトルの転置 図２の受信機３０において、シンボル間隔Ｔでサンプリ
ングされた受信信号のサンプル値Ｙn が位相回転部４０
に入力されると、該位相回転部４０では、位相推定部８
０Ａで推定された位相推定値Ｅφn から演算手段４１で
位相回転量ｅｘｐ［−ｊＥφn]を求め、これを乗算手段
４２で受信信号のサンプル値Ｙn に乗じて位相を補償し
た次式（７）のような受信信号のサンプル値ｃｒn を、
遅延手段５０及びビタビ・アルゴリズム処理部６０へ出
力する。 ｃｒn＝ｒn・ｅｘｐ［ｊ（φn−Ｅφn）］ ・・・（７） 遅延手段５０は受信信号のサンプル値ｃｒn を遅延し、
その遅延した値ｃｒn- M を位相誤差検出回路８１Ａ内の
乗算手段８１ｂ、及び伝送路推定部７０Ａ内の減算手段
７３へ与える。ビタビ・アルゴリズム処理部６０では、
受信信号のサンプル値ｃｒn を入力し、インパルス応答
適応更新手段７２で推定された伝送路２０のインパルス
応答推定値Ｅｈj に基づき、送信シンボル系列を推定
し、その推定送信シンボル系列｛Ｅｘn，Ｅｘn-1，…，
Ｅｘn-L}を出力する。伝送路推定部７０Ａ内の受信信号
再生手段７１は、推定送信シンボル系列｛Ｅｘn，Ｅｘ
n-1，…，Ｅｘn-L}と伝送路２０のインパルス応答推定
値Ｅｈj とに基づき、受信信号の推定値Ｅｒn-M を求
め、減算手段７３、及び位相誤差検出回路８１Ａ内の複
素共役算出手段８１ａへ与える。減算手段７３は、遅延
手段５０からの受信信号のサンプル値ｃｒn-M から推定
値Ｅｒn-M を減算して推定誤差ｅn- M を求め、それをイ
ンパルス応答適応更新手段７２に与える。位相誤差検出
回路８１Ａでは、受信信号再生手段７１から与えられる
受信信号の推定値Ｅｒn から複素共役算出手段８１ａで
複素共役ｃｒ* n-Mを算出し、その複素共役ｃｒ* n-Mと、
遅延手段５０で遅延された受信信号のサンプル値ｃｒ
n-Mとを、乗算手段８１ｂで乗算する。この乗算結果か
ら、虚数部抽出手段８１ｃで虚数部を抽出し、位相誤差
△φn を求め、ループフィルタ８２へ与える。伝送路推
定部７０Ａ及び位相推定部８０Ａの推定動作が十分行わ
れているとすると、受信信号の推定値Ｅｒnはほぼｒnに
等しいから、位相誤差検出回路８１Ａの出力は、次式
（８）のようになり、位相誤差に比例した量となる。Next, the operation will be described. For example, the sample value y n of the received signal is y n = r n · exp [jφ n ] ... is expressed as (5). Here, phi n is the phase deviation due to frequency offset and phase jitter, using the sample values of the received signal when r n is not have these phase fluctuations, the impulse response vector Vh n, and a transmission symbol vector VX n following It is expressed as in Expression (6). r n = Vh n T · Vx n ··· (6) where, Vh n = {h 0 n , h 1 n, ..., h L n} T Vx n = {x n, x n-1, ..., x nL } T T; Transposition of vector In the receiver 30 of FIG. 2, the sample value Y n of the reception signal sampled at the symbol interval T is the phase rotation unit 40.
Is input to the phase rotation unit 40, the phase estimation unit 8
The phase rotation amount exp [−jEφ n ] is calculated by the computing unit 41 from the phase estimated value Eφ n estimated at 0 A, and is multiplied by the sample value Y n of the received signal by the multiplication unit 42 to obtain the following equation ( The sampled value cr n of the received signal as in
It outputs to the delay means 50 and the Viterbi algorithm processing unit 60. cr n = r n · exp [j (φ n −Eφ n )] (7) The delay means 50 delays the sample value cr n of the received signal,
The delayed value cr n- M is given to the multiplication means 81b in the phase error detection circuit 81A and the subtraction means 73 in the transmission path estimation unit 70A. In the Viterbi algorithm processing unit 60,
The received signal sample value cr n is input, the transmission symbol sequence is estimated based on the impulse response estimation value Eh j of the transmission path 20 estimated by the impulse response adaptive updating means 72, and the estimated transmission symbol sequence {Ex n , Ex n-1 , ...,
Ex nL } is output. The reception signal reproducing means 71 in the transmission path estimation unit 70A uses the estimated transmission symbol sequence {Ex n , Ex.
n-1, ..., based on the Ex nL} impulse response estimate Eh j of the transmission path 20, it obtains an estimated value Er nM of the received signal, subtraction means 73, and the complex conjugate calculating means of the phase error detection circuit 81A 81a. The subtracting means 73 subtracts the estimated value Er nM from the sample value cr nM of the received signal from the delay means 50 to obtain an estimated error e n− M , and supplies it to the impulse response adaptive updating means 72. In the phase error detection circuit 81A, it calculates a complex conjugate cr * nM from estimates Er n of the received signal supplied from the reception signal reproducing means 71 by the complex conjugate calculation unit 81a, and its complex conjugate cr * nM,
Sample value cr of the received signal delayed by the delay means 50
nM is multiplied by the multiplication means 81b. From this multiplication result, the imaginary part extracting means 81c extracts the imaginary part, obtains the phase error Δφ n , and supplies it to the loop filter 82. Assuming that the estimation operations of the transmission path estimation unit 70A and the phase estimation unit 80A are sufficiently performed, the estimated value Er n of the received signal is substantially equal to r n , and therefore the output of the phase error detection circuit 81A is ), And the amount is proportional to the phase error.
【００１２】 Ｉｍ［Ｅｒn *・ｃｒn］＝Ｉｍ［｜ｒn｜2・ｅｘｐ［ｊ(φn−Ｅφn)]] ＝Ａ・Ｈ2・sin（△φn） ≒Ａ・Ｈ2・△φn ・・・（８） 但し、Ａ；送信シンボルベクトルＶＸnの２乗平均値 Ｈ；伝送路２０のインパルス応答ベクトルＶｈnの絶対
値 位相誤差検出回路８１Ａから出力された位相誤差△φn
は、ループフィルタ８２で乗数αが乗算されて位相修正
量△Ｅφn+1 となり、ＶＣＯ８３へ送られる。ＶＣＯ８
３では、加算手段８３ａで、位相推定値Ｅφnに位相修
正量△Ｅφn+1を加算し、遅延手段８３ｂで遅延し、新
たな位相推定値Ｅφn+1 として位相回転部４０へ送られ
る。[0012] Im [Er n * · cr n ] = Im [| r n | 2 · exp [j (φ n -Eφ n)]] = A · H 2 · sin (△ φ n) ≒ A · H 2 · △ φ n ··· (8) where, a; absolute value phase error output from the detection circuit 81A phase error of the impulse response vector Vh n of the transmission channel 20 △; 2 mean square value H of the transmitted symbol vector VX n φ n
Is multiplied by a multiplier α in the loop filter 82 to obtain a phase correction amount ΔEφ n + 1 , which is sent to the VCO 83. VCO8
In step 3, the addition means 83a adds the phase correction amount ΔEφ n + 1 to the phase estimation value Eφ n , the delay means 83b delays it, and the new phase estimation value Eφ n + 1 is sent to the phase rotation unit 40. .
【００１３】以上のように、本実施例では、次のような
利点を有している。As described above, this embodiment has the following advantages.
【００１４】位相推定部８０Ａ内の位相誤差検出回路８
１Ａでは、遅延手段５０から出力される位相を補償した
受信信号ｃｒn と、受信信号再生手段７１から出力され
る受信信号の推定値Ｅｒnとから、位相誤差△φnを検出
するので、例えば、固定小数点演算のＤＳＰ等で適応最
尤系列推定器を実現しても、位相誤差検出の計算精度が
劣化しない。なお、本発明は上記実施例に限定されず、
種々の変形が可能である。その変形例としては、例えば
次のようなものがある。 （ａ）適応最尤系列推定器の構成として、図１のビタビ
・アルゴリズム処理部６０の入力側に、信号対雑音比
（Ｓ／Ｎ比）を低減するための整合フィルタや白色化整
合フィルタを設け、そのフィルタの出力をビタビ・アル
ゴリズム処理部６０に入力する構成例がある。これらの
構成の適応最尤系列推定器は、ビタビ・アルゴリズム処
理部６０内の計算が異なるだけであり、これらの構成の
適応最尤系列推定器にも、上記実施例をまったく同様に
適用できる。 （ｂ）位相推定部８０Ａ内のループフィルタ８２は、従
来と同様に１次のＰＬＬで構成したが、これは２次、あ
るいはより高次のＰＬＬ等で構成してもよい。 （ｃ）上記実施例の適応最尤系列推定器は、ディジタル
移動通信の適応等化器３３に適用される場合について説
明したが、固定通信網におけるデータ通信の適応等化器
等としても、当然、適用可能である。Phase error detection circuit 8 in phase estimation section 80A
In 1A, the phase error Δφ n is detected from the received signal cr n output from the delay unit 50 and having the phase compensated, and the estimated value Er n of the received signal output from the received signal reproducing unit 71. Even if the adaptive maximum likelihood sequence estimator is realized by a fixed-point arithmetic DSP or the like, the calculation accuracy of phase error detection does not deteriorate. The present invention is not limited to the above embodiment,
Various modifications are possible. The following are examples of such modifications. (A) As a configuration of the adaptive maximum likelihood sequence estimator, a matched filter or a whitened matched filter for reducing the signal-to-noise ratio (S / N ratio) is provided on the input side of the Viterbi algorithm processing unit 60 of FIG. There is a configuration example in which the output of the filter is provided and the output of the filter is input to the Viterbi algorithm processing unit 60. The adaptive maximum likelihood sequence estimator having these configurations is different only in the calculation in the Viterbi algorithm processing unit 60, and the above embodiment can be applied to the adaptive maximum likelihood sequence estimator having these configurations in exactly the same manner. (B) The loop filter 82 in the phase estimation unit 80A is configured by a first-order PLL as in the conventional case, but it may be configured by a second-order or higher-order PLL or the like. (C) The adaptive maximum likelihood sequence estimator of the above embodiment has been described as applied to the adaptive equalizer 33 for digital mobile communication. However, it is natural that the adaptive maximum likelihood sequence estimator for data communication in a fixed communication network may be used. , Applicable.
【００１５】[0015]
【発明の効果】以上詳細に説明したように、第１及び第
２の発明によれば、位相推定部内の位相誤差検出手段
は、位相回転部で位相の補償された受信信号と、伝送路
推定部内の受信信号再生手段で求められた受信信号の推
定値とから、位相誤差を検出する構成にしたので、伝送
路推定部及び位相推定部の推定動作が十分行われている
時に伝送路の推定誤差が小さな値になっても、該位相誤
差検出手段で求める位相誤差には何等影響されない。即
ち、固定小数点演算のＤＳＰ等で適応最尤系列推定器を
実現しても、位相誤差検出の計算精度が劣化しないとい
う効果が得られる。As described in detail above, according to the first and second aspects of the present invention, the phase error detecting means in the phase estimating section includes the received signal whose phase is compensated by the phase rotating section and the transmission path estimation. Since the phase error is detected from the estimated value of the received signal obtained by the received signal reproducing means in the unit, the transmission line estimation is performed when the estimation operation of the transmission line estimation unit and the phase estimation unit is sufficiently performed. Even if the error has a small value, it is not affected by the phase error obtained by the phase error detecting means. That is, even if the adaptive maximum likelihood sequence estimator is realized by a DSP of fixed point arithmetic, the effect that the calculation accuracy of the phase error detection does not deteriorate can be obtained.
【図１】本発明の実施例を示す適応最尤系列推定器の機
能ブロック図である。FIG. 1 is a functional block diagram of an adaptive maximum likelihood sequence estimator showing an embodiment of the present invention.
【図２】一般的なディジタル移動通信における送受信機
の機能ブロック図である。FIG. 2 is a functional block diagram of a transceiver in general digital mobile communication.
【図３】従来の適応最尤系列推定器の機能ブロック図で
ある。FIG. 3 is a functional block diagram of a conventional adaptive maximum likelihood sequence estimator.
４０ 位相回転部 ５０ 遅延手段 ６０ ビタビ・アルゴリズム処理
部 ７０Ａ 伝送路推定部 ７１ 受信信号再生手段 ７２ インパルス応答適応更新手
段 ７３ 減算手段 ８０Ａ 位相推定部 ８１Ａ 位相誤差検出回路 ８１ａ 複素共役算出手段 ８１ｂ 乗算手段 ８１ｃ 虚数部抽出手段 ８２ ループフィルタ ８３ ＶＣＯ40 phase rotating unit 50 delaying unit 60 Viterbi algorithm processing unit 70A transmission line estimating unit 71 received signal reproducing unit 72 impulse response adaptive updating unit 73 subtracting unit 80A phase estimating unit 81A phase error detecting circuit 81a complex conjugate calculating unit 81b multiplying unit 81c Imaginary part extraction means 82 Loop filter 83 VCO
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０４Ｌ 27/01 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H04L 27/01
Claims (2)
転させて該受信信号の位相変動を補償する位相回転部
と、 前記補償後の受信信号を入力し、伝送路のインパルス応
答推定値に基づきビタビ・アルゴリズムに従って送信シ
ンボルの推定を行い、推定送信シンボル系列を出力する
ビタビ・アルゴリズム処理部と、 前記推定送信シンボル系列と前記伝送路のインパルス応
答推定値とから受信信号の推定値を算出する受信信号再
生手段を有し、前記補償後の受信信号から該受信信号の
推定値を差し引いて推定誤差を算出し、該推定誤差及び
前記推定送信シンボル系列に基づき、適応アルゴリズム
に従い伝送路のインパルス応答を更新して新しい前記伝
送路のインパルス応答推定値を前記ビタビ・アルゴリズ
ム処理部及び受信信号再生手段に与える伝送路推定部
と、 受信信号の位相誤差を検出する位相誤差検出手段を有
し、該位相誤差を位相修正値として位相推定値に加えて
新しい前記位相推定値を前記位相回転部に与える位相推
定部とを、 備えた適応最尤系列推定器において、 前記位相誤差検出手段は、前記補償後の受信信号と前記
受信信号の推定値とを用いて前記位相誤差を検出する構
成にしたことを特徴とする適応最尤系列推定器。1. A phase rotation unit for rotating the phase of a received signal based on the estimated phase value to compensate for a phase variation of the received signal, and inputting the compensated received signal to an impulse response estimated value of a transmission line. Based on the Viterbi algorithm, the transmission symbol is estimated, and the estimated value of the received signal is calculated from the Viterbi algorithm processing unit that outputs the estimated transmission symbol sequence and the estimated transmission symbol sequence and the impulse response estimation value of the transmission path. An impulse response of the transmission line according to an adaptive algorithm based on the estimated error and the estimated transmission symbol sequence, the estimated signal error is subtracted from the compensated received signal, and the estimated error is calculated from the compensated received signal. To provide a new impulse response estimation value of the transmission line to the Viterbi algorithm processing unit and the received signal reproducing means. A phase estimation unit that has a transmission line estimation unit and a phase error detection unit that detects a phase error of a received signal, and adds the phase error as a phase correction value to the phase estimation value to give the new phase estimation value to the phase rotation unit. And a phase error detecting means configured to detect the phase error using the compensated received signal and an estimated value of the received signal. Adaptive maximum likelihood sequence estimator.
共役算出手段と、 前記補償後の受信信号と前記複素共役とを乗算する乗算
手段と、 前記乗算手段の乗算結果より虚数部を抽出して位相誤差
を出力する虚数部抽出手段とで、 構成したことを特徴とする請求項１記載の適応最尤系列
推定器。2. The phase error detecting means, a complex conjugate calculating means for calculating a complex conjugate of an estimated value of the received signal, a multiplying means for multiplying the compensated received signal by the complex conjugate, The adaptive maximum likelihood sequence estimator according to claim 1, wherein the adaptive maximum likelihood sequence estimator comprises: an imaginary part extracting unit that extracts an imaginary part from the multiplication result of the multiplying unit and outputs a phase error.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05202294A JP3135425B2 (en) | 1993-08-16 | 1993-08-16 | Adaptive maximum likelihood sequence estimator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05202294A JP3135425B2 (en) | 1993-08-16 | 1993-08-16 | Adaptive maximum likelihood sequence estimator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0758676A true JPH0758676A (en) | 1995-03-03 |
| JP3135425B2 JP3135425B2 (en) | 2001-02-13 |
Family
ID=16455165
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05202294A Expired - Fee Related JP3135425B2 (en) | 1993-08-16 | 1993-08-16 | Adaptive maximum likelihood sequence estimator |
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| Country | Link |
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| JP (1) | JP3135425B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6473470B1 (en) | 1998-05-11 | 2002-10-29 | Nec Corp. | Phase-locked loop circuits for communication system |
| WO2007061174A1 (en) * | 2005-11-25 | 2007-05-31 | Electronics And Telecommunications Research Institute | Apparatus for estimating phase error and phase error correction system using the same |
-
1993
- 1993-08-16 JP JP05202294A patent/JP3135425B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6473470B1 (en) | 1998-05-11 | 2002-10-29 | Nec Corp. | Phase-locked loop circuits for communication system |
| WO2007061174A1 (en) * | 2005-11-25 | 2007-05-31 | Electronics And Telecommunications Research Institute | Apparatus for estimating phase error and phase error correction system using the same |
| US8045646B2 (en) | 2005-11-25 | 2011-10-25 | Electronics And Telecommunications Research Institute | Apparatus for estimating phase error and phase error correction system using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3135425B2 (en) | 2001-02-13 |
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