JPH0758239A - Chip carrier - Google Patents
Chip carrierInfo
- Publication number
- JPH0758239A JPH0758239A JP16217593A JP16217593A JPH0758239A JP H0758239 A JPH0758239 A JP H0758239A JP 16217593 A JP16217593 A JP 16217593A JP 16217593 A JP16217593 A JP 16217593A JP H0758239 A JPH0758239 A JP H0758239A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- conductive circuit
- pattern
- chip carrier
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子等の電子部
品を搭載するために用いられるチップキャリアに関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip carrier used for mounting electronic parts such as semiconductor elements.
【０００２】[0002]
【従来の技術】図３に示すごとく、プリント配線板
（１）に付設された放熱用の金属層（２）を備えたチッ
プキャリアにおいて、放熱用の金属層（２）は、プリン
ト配線板（１）の導電回路（１０）にワイヤボンディン
グされた半導体素子等の電子部品（７）の熱が蓄積する
のを防ぐため、放熱する役割を果たす。従って、一般的
には、放熱用の金属層（２）の材料としては、熱伝導性
の良好なアルミニウム、銅及びこれらの合金等の金属が
使用されている。2. Description of the Related Art As shown in FIG. 3, in a chip carrier provided with a metal layer (2) for heat dissipation attached to a printed wiring board (1), the metal layer (2) for heat dissipation is In order to prevent the heat of the electronic component (7) such as a semiconductor element wire-bonded to the conductive circuit (10) of 1) from being accumulated, it plays a role of radiating heat. Therefore, as a material for the metal layer (2) for heat dissipation, metals such as aluminum, copper and alloys thereof having good thermal conductivity are generally used.
【０００３】このチップキャリアは、絶縁基板（１ａ）
に導電回路（１０）を形成してなるプリント配線板
（１）の導電回路（１０）が形成された面に電子部品
（７）を搭載し、電子部品（７）とプリント配線板
（１）の導電回路（１０）をボンディングワイア（６）
で電気的に接続してあり、このプリント配線板（１）の
導電回路（１０）が形成された面と反対側の面には、放
熱用の金属層（２）が形成されている。この導電回路
（１０）と放熱用の金属層（２）との間に厚みあるい
は、使用している材料等に差があるため、熱膨張によ
り、厚みの厚い放熱用の金属層（２）の方が、厚みの薄
い導電回路（１０）より大きな応力が発生し、力の釣り
合いが崩れることにより、曲げ応力が発生し、チップキ
ャリアに、反りが発生するという欠点がある。This chip carrier is an insulating substrate (1a).
An electronic component (7) is mounted on the surface of the printed wiring board (1) formed with the conductive circuit (10) on which the conductive circuit (10) is formed, and the electronic component (7) and the printed wiring board (1). Bonding wire (6) for the conductive circuit (10)
And a metal layer (2) for heat dissipation is formed on the surface of the printed wiring board (1) opposite to the surface on which the conductive circuit (10) is formed. Since there is a difference in thickness or a material used between the conductive circuit (10) and the metal layer (2) for heat dissipation, thermal expansion causes a thick metal layer (2) for heat dissipation. However, there is a drawback in that a larger stress is generated than in the conductive circuit (10) having a small thickness, and the balance of forces is lost, so that bending stress is generated and the chip carrier is warped.
【０００４】特に絶縁基板（１ａ）の厚みを薄くすれば
するほど、反りの発生が顕著になる。In particular, the thinner the insulating substrate (1a), the more remarkable the warpage.
【０００５】[0005]
【発明が解決しようとする課題】本発明は上記の欠点を
除去するためになされたもので、その目的とするところ
は、放熱が良好で、反りのないチップキャリアを提供す
ることにある。SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a chip carrier which has good heat dissipation and does not warp.
【０００６】[0006]
【課題を解決するための手段】本発明に係るチップキャ
リアは、絶縁基板（１ａ）と、この絶縁基板（１ａ）に
搭載する半導体素子等の電子部品（７）の実装面に形成
された導電回路（１０）とからなるプリント配線板
（１）及びこの実装面と反対側に付設された放熱用の金
属層（２）を備えたチップキャリアにおいて、上記金属
層（２）が、電子部品（７）からの熱による、導電回路
（１０）の熱応力を相殺する応力を発生するパターン
（９）で構成したことを特徴とするものである。A chip carrier according to the present invention is a conductive material formed on a mounting surface of an insulating substrate (1a) and an electronic component (7) such as a semiconductor element mounted on the insulating substrate (1a). In a chip carrier provided with a printed wiring board (1) including a circuit (10) and a metal layer (2) for heat dissipation provided on the side opposite to the mounting surface, the metal layer (2) is an electronic component (2). It is characterized in that it is composed of a pattern (9) that generates a stress that cancels the thermal stress of the conductive circuit (10) by the heat from 7).
【０００７】また本発明にあって、サーマルビア（５）
を介して、電子部品（７）は、金属層（２）と熱的に接
続させる。According to the present invention, the thermal via (5)
The electronic component (7) is thermally connected to the metal layer (2) via the.
【０００８】[0008]
【作用】本発明によると、半導体素子等の電子部品
（７）の熱が、絶縁基板（１ａ）あるいは、サーマルビ
ア（５）を介して、放熱用の金属層（２）に伝えられ、
放熱されるが、放熱用の金属層（２）はスリット状また
は、放射状等のパターン（９）で形成されているため、
導電回路（１０）と放熱用の金属層（２）との間に厚み
あるいは、使用している材料に差があっても、熱に起因
して発生する導電回路（１０）の応力と放熱用の金属層
（２）の応力とが相殺される。According to the present invention, the heat of the electronic component (7) such as a semiconductor element is transferred to the heat radiating metal layer (2) through the insulating substrate (1a) or the thermal via (5),
Heat is dissipated, but since the metal layer (2) for heat dissipation is formed in a slit-shaped or radial pattern (9),
Even if there is a difference in the thickness or the material used between the conductive circuit (10) and the metal layer (2) for heat dissipation, the stress of the conductive circuit (10) caused by heat and the heat dissipation And the stress of the metal layer (2) are canceled out.
【０００９】[0009]
【実施例】以下、本発明を実施例によって詳述する。EXAMPLES The present invention will be described in detail below with reference to examples.
【００１０】図１は、本発明の実施例に係るチップキャ
リアを例示した断面図である。図１（ａ）に示すごと
く、このチップキャリアは、絶縁基板（１ａ）に導電回
路（１０）を形成してなるプリント配線板（１）の導電
回路（１０）が形成された面に半導体素子等の電子部品
（７）を搭載し、電子部品（７）とプリント配線板
（１）の導電回路（１０）をボンディングワイア（６）
で電気的に接続してあり、このプリント配線板（１）の
導電回路（１０）が形成された面と反対側の面には、放
熱用の金属層（２）が形成されている。FIG. 1 is a sectional view illustrating a chip carrier according to an embodiment of the present invention. As shown in FIG. 1A, this chip carrier has a semiconductor element on a surface of a printed wiring board (1) having a conductive circuit (10) formed on the insulating substrate (1a). An electronic component (7) such as the like is mounted, and the electronic component (7) and the conductive circuit (10) of the printed wiring board (1) are bonded to each other by a bonding wire (6).
And a metal layer (2) for heat dissipation is formed on the surface of the printed wiring board (1) opposite to the surface on which the conductive circuit (10) is formed.
【００１１】この金属層（２）の材料としては、熱伝導
性の良好な銅、アルミニウム及びこれらの合金等を使用
してもよく、金属箔であっても、メッキであってもよ
く、材料及び形成方法は問わない。As the material of the metal layer (2), copper, aluminum and alloys thereof having good thermal conductivity may be used, and may be metal foil or plating. The forming method does not matter.
【００１２】導電回路（１０）を形成する銅箔の厚み
は、９μｍ〜１８μｍが好ましく、放熱用の金属層
（２）の厚みは、５０μｍ〜７０μｍが好ましい。The thickness of the copper foil forming the conductive circuit (10) is preferably 9 μm to 18 μm, and the thickness of the metal layer (2) for heat dissipation is preferably 50 μm to 70 μm.
【００１３】この放熱用の金属層（２）は、図１（ｂ）
に示すごとく、放射状のパターン（９）で形成され、放
熱用の金属層（２）と導電回路（１０）との応力が相殺
し、互いの応力が打ち消し合い、反りが発生しないよう
にしている。The metal layer (2) for heat dissipation is shown in FIG.
As shown in FIG. 7, the pattern is formed in a radial pattern (9) so that the stress between the heat-dissipating metal layer (2) and the conductive circuit (10) cancels each other out, so that the stresses cancel each other out and no warpage occurs. .
【００１４】すなわち、放熱用の金属層（２）を形成す
るパターン（９）は、絶縁基板（１ａ）が露出する露出
面（３）及び絶縁基板（１ａ）が金属層（２）により被
覆される被覆面（４）とからなる。このパターン（９）
は、放射状に限定されるものではなく、格子状であって
も、スリット状であってもよい。That is, in the pattern (9) for forming the metal layer (2) for heat dissipation, the exposed surface (3) where the insulating substrate (1a) is exposed and the insulating substrate (1a) are covered with the metal layer (2). Coating surface (4). This pattern (9)
Is not limited to a radial shape, and may be a lattice shape or a slit shape.
【００１５】電子部品（７）から発生した熱は、絶縁基
板（１ａ）に伝熱し放熱用の金属層（２）に到達し放熱
される。The heat generated from the electronic component (7) is transferred to the insulating substrate (1a), reaches the metal layer (2) for heat radiation, and is radiated.
【００１６】また、図２に示すごとく、このチップキャ
リアは、絶縁基板（１ａ）を貫通したスルーホール（１
１）を熱的に導通する熱伝導性の良い銅等で被覆するこ
とにより形成されたサーマルビア（５）を備え、電子部
品（７）を前記スルーホール（１１）を閉塞するように
搭載すると、電子部品（７）から発生した熱は、絶縁基
板（１ａ）よりも熱伝導量の高いサーマルビア（５）を
伝導し放熱用の金属層（２）に伝わるので放熱量が増大
する。その結果、導電回路（１０）と金属層（２）の熱
応力の相殺効果が高まる。Further, as shown in FIG. 2, this chip carrier has a through hole (1) penetrating the insulating substrate (1a).
When the electronic component (7) is mounted so as to close the through hole (11), it is provided with a thermal via (5) formed by covering 1) with copper or the like having good thermal conductivity that conducts heat. The heat generated from the electronic component (7) is conducted through the thermal via (5) having a higher thermal conductivity than that of the insulating substrate (1a) and is transmitted to the heat dissipation metal layer (2), so that the heat dissipation is increased. As a result, the effect of canceling the thermal stress between the conductive circuit (10) and the metal layer (2) is enhanced.
【００１７】[0017]
【発明の効果】本発明のチップキャリアによると、半導
体素子等の電子部品（７）から発生した熱は、絶縁基板
（１ａ）に伝熱し放熱用の金属層（２）に到達し放熱さ
れる。この場合、放熱用の金属層（２）に形成されたパ
ターン（９）が、熱に起因する導電回路（１０）の応力
を相殺する応力を発生させるため、反りが発生しない。According to the chip carrier of the present invention, the heat generated from the electronic component (7) such as a semiconductor element is transferred to the insulating substrate (1a), reaches the metal layer (2) for heat radiation and is radiated. . In this case, the pattern (9) formed on the heat-dissipating metal layer (2) generates a stress that cancels the stress of the conductive circuit (10) caused by heat, so that no warp occurs.
【００１８】また、サーマルビア（５）を備えることに
より、前記より更に電子部品（７）から発生した熱の放
熱性が向上するので熱応力の相殺効果が高まる。Further, the provision of the thermal vias (5) further improves the heat radiation performance of the heat generated from the electronic component (7), so that the effect of canceling the thermal stress is enhanced.
【図１】本発明のチップキャリアの実施例を示し、
（ａ）は断面図であり、（ｂ）は平面図である。FIG. 1 shows an embodiment of a chip carrier of the present invention,
(A) is sectional drawing, (b) is a top view.
【図２】本発明の他の実施例に係るチップキャリアの断
面図である。FIG. 2 is a sectional view of a chip carrier according to another embodiment of the present invention.
【図３】従来例に係るチップキャリアに半導体素子等の
電子部品を搭載した状態を示す断面図である。FIG. 3 is a cross-sectional view showing a state where electronic components such as a semiconductor element are mounted on a chip carrier according to a conventional example.
１ プリント配線板 １ａ 絶縁基板 ２ 金属層 ５ サーマルビア ７ 電子部品 ９ パターン １０ 導電回路 1 Printed Wiring Board 1a Insulating Substrate 2 Metal Layer 5 Thermal Via 7 Electronic Component 9 Pattern 10 Conductive Circuit
Claims (2)
ａ）に搭載する電子部品（７）の実装面に形成された導
電回路（１０）とからなるプリント配線板（１）及びこ
の実装面と反対側に付設された放熱用の金属層（２）を
備えたチップキャリアにおいて、上記金属層（２）が、
電子部品（７）からの熱による、導電回路（１０）の熱
応力を相殺する応力を発生するパターン（９）で構成し
たことを特徴とするチップキャリア。1. An insulating substrate (1a) and the insulating substrate (1)
A printed wiring board (1) comprising a conductive circuit (10) formed on a mounting surface of an electronic component (7) mounted on a) and a metal layer (2) for heat dissipation provided on the opposite side of the mounting surface. In the chip carrier provided with, the metal layer (2) is
A chip carrier comprising a pattern (9) for generating a stress that cancels a thermal stress of a conductive circuit (10) by heat from an electronic component (7).
（７）と金属層（２）とが熱的に接続されていることを
特徴とする請求項１に記載のチップキャリア。2. Chip carrier according to claim 1, characterized in that the electronic component (7) and the metal layer (2) are thermally connected via a thermal via (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16217593A JPH0758239A (en) | 1993-06-30 | 1993-06-30 | Chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16217593A JPH0758239A (en) | 1993-06-30 | 1993-06-30 | Chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0758239A true JPH0758239A (en) | 1995-03-03 |
Family
ID=15749445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16217593A Pending JPH0758239A (en) | 1993-06-30 | 1993-06-30 | Chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758239A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006524904A (en) * | 2003-02-10 | 2006-11-02 | スカイワークス ソリューションズ，インコーポレイテッド | Semiconductor die package with reduced inductance and reduced die adhesive flow |
| US8102046B2 (en) * | 2007-10-26 | 2012-01-24 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| JP2016500485A (en) * | 2012-12-21 | 2016-01-12 | エプコス アクチエンゲゼルシャフトＥｐｃｏｓ Ａｇ | Component carrier and component carrier assembly |
| JP2016103546A (en) * | 2014-11-27 | 2016-06-02 | パナソニックＩｐマネジメント株式会社 | Board device and electronic equipment |
| JP2016162720A (en) * | 2015-03-05 | 2016-09-05 | コニカミノルタ株式会社 | Light-emitting device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01143242A (en) * | 1987-11-27 | 1989-06-05 | Ibiden Co Ltd | Semiconductor mounting heat dissipation substrate |
| JPH0451583A (en) * | 1990-06-20 | 1992-02-20 | Kawasaki Steel Corp | Metal-sheet bonded ceramic board |
| JPH04182367A (en) * | 1990-11-14 | 1992-06-29 | Kawasaki Steel Corp | Ceramic substrate joined to metallic plate |
-
1993
- 1993-06-30 JP JP16217593A patent/JPH0758239A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01143242A (en) * | 1987-11-27 | 1989-06-05 | Ibiden Co Ltd | Semiconductor mounting heat dissipation substrate |
| JPH0451583A (en) * | 1990-06-20 | 1992-02-20 | Kawasaki Steel Corp | Metal-sheet bonded ceramic board |
| JPH04182367A (en) * | 1990-11-14 | 1992-06-29 | Kawasaki Steel Corp | Ceramic substrate joined to metallic plate |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006524904A (en) * | 2003-02-10 | 2006-11-02 | スカイワークス ソリューションズ，インコーポレイテッド | Semiconductor die package with reduced inductance and reduced die adhesive flow |
| US8102046B2 (en) * | 2007-10-26 | 2012-01-24 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| JP2016500485A (en) * | 2012-12-21 | 2016-01-12 | エプコス アクチエンゲゼルシャフトＥｐｃｏｓ Ａｇ | Component carrier and component carrier assembly |
| US10021776B2 (en) | 2012-12-21 | 2018-07-10 | Epcos Ag | Component carrier and component carrier arrangement |
| JP2018139317A (en) * | 2012-12-21 | 2018-09-06 | エプコス アクチエンゲゼルシャフトＥｐｃｏｓ Ａｇ | Component carrier and component carrier assembly |
| JP2016103546A (en) * | 2014-11-27 | 2016-06-02 | パナソニックＩｐマネジメント株式会社 | Board device and electronic equipment |
| JP2016162720A (en) * | 2015-03-05 | 2016-09-05 | コニカミノルタ株式会社 | Light-emitting device |
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