JPH0755012Y2 - Address setting structure - Google Patents
Address setting structureInfo
- Publication number
- JPH0755012Y2 JPH0755012Y2 JP3119190U JP3119190U JPH0755012Y2 JP H0755012 Y2 JPH0755012 Y2 JP H0755012Y2 JP 3119190 U JP3119190 U JP 3119190U JP 3119190 U JP3119190 U JP 3119190U JP H0755012 Y2 JPH0755012 Y2 JP H0755012Y2
- Authority
- JP
- Japan
- Prior art keywords
- address
- board
- sub
- information
- main board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Combinations Of Printed Boards (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 本考案はアドレス設定構造に関し、特に１つの主基板と
２つの副基板を結合して一つの機能ユニットとして構成
され、実装される複数のプリント基板に対する実装上の
識別アドレスを設定するアドレス設定構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an address setting structure, and in particular, a plurality of prints which are configured and mounted as one functional unit by combining one main board and two sub boards. The present invention relates to an address setting structure for setting an identification address for mounting on a board.
従来、この種のアドレス設定は、アドレス板一枚一枚を
異なるものとして作るか、もしくは同一プリント板上に
アドレスを識別するための異る配線や部品実装をほどこ
すことにより行なっていた。Conventionally, this kind of address setting has been performed by making each address plate different, or by providing different wirings and component mounting for identifying addresses on the same printed board.
上述した従来のアドレス設定方法は、プリント板をその
基板の持つアドレス値に従って別別に作るか、もしく
は、同一基板を利用した場合にはあらかじめ異なるアド
レスを設定できるようなストラップ配線または部品を取
り付けられるように用意しなければならないという欠点
がある。In the conventional address setting method described above, the printed board is made separately according to the address value of the board, or if the same board is used, strap wiring or parts can be attached so that different addresses can be set in advance. It has the drawback of having to be prepared.
本考案のアドレス設定構造は、プリント基板に対して実
装上の識別アドレスを設定するためのアドレス設定構造
であって、１つの機能ユニットを形成する１つの主基板
ならびに第１および第２の２つの副基板と、前記第１お
よび第２の副基板を前記主基板の一面に平行に保持して
電気的かつ構造的に結合させ互いに配設位置を異にする
第１および第２の２つのコネクタと、前記主基板の接地
情報を前記第１のコネクタを介して受け前記接地情報を
前記第１の副基板のアドレス判別情報として判別し出力
する第１のアドレス判別回路と、前記接地情報を受けな
い状態を前記第２の副基板のアドレス判別情報として判
別し出力する第２のアドレス判別回路とを備えて構成さ
れる。The address setting structure of the present invention is an address setting structure for setting an identification address for mounting on a printed circuit board, and includes one main board forming one functional unit and two first and second boards. A sub-board and first and second connectors that hold the first and second sub-boards in parallel with one surface of the main board and electrically and structurally couple the sub-boards and dispose them at different positions. A first address discriminating circuit for receiving ground information of the main board via the first connector and discriminating and outputting the ground information as address discrimination information of the first sub-board; and receiving the ground information. A second address discriminating circuit for discriminating and outputting the absence state as the address discriminating information of the second sub-board.
次に、図面を参照して本考案を説明する。第１図は本考
案の一実施例の側面図である。第１図に示す実施例は、
架等に実装されて１つの機能を発揮する機能ユニットを
形成する複数のプリント基板の主基板１、第１の副基板
２、第２の副基板３と、互いに異る位置に配設されて各
プリント基板相互間を電気的に接続し、かつ平行に保持
する第１のコネクタ５、第２のコネクタ８と、主基板１
と接地情報を受けてこの接地情報を第１の副基板２のア
ドレス判別情報として利用する第１のアドレス判別回路
７と、主基板１を介して取得する接地情報から疎外され
た状態を第２の副基板３のアドレス判別情報として利用
する第２のアドレス判定回路10と、抵抗器６および９を
備えて構成される。The present invention will now be described with reference to the drawings. FIG. 1 is a side view of an embodiment of the present invention. The embodiment shown in FIG.
The main board 1, the first sub-board 2 and the second sub-board 3, which are a plurality of printed boards that are mounted on a rack or the like to form a functional unit that exhibits one function, are arranged at different positions. A first connector 5 and a second connector 8 for electrically connecting the printed circuit boards to each other and holding them in parallel, and a main board 1.
And the ground information and receives the ground information and uses this ground information as the address discrimination information of the first sub-board 2 and the ground information obtained via the main board 1 in the second state. A second address determination circuit 10 used as address determination information of the sub-board 3 and resistors 6 and 9 are provided.
次に、第１図の実施例の動作について説明する。Next, the operation of the embodiment shown in FIG. 1 will be described.
まず、第１の副基板２に着目すると、主基板１上の接地
部４による接地情報は、第１のコネクタ５の中の配線路
11を通して第１の副基板２上の抵抗器６の片端へ送られ
る。抵抗器６のもう一方の端は電源に接続される主基板
１から取得する接地情報により抵抗器６の片端は論理ロ
ウ（Low）となる。この論理Lowの情報は、第１のアドレ
ス判別回路７に供給され、アドレス判別情報として用い
られる。First, focusing on the first sub-board 2, the grounding information by the grounding section 4 on the main board 1 is determined by the wiring path in the first connector 5.
It is sent to one end of the resistor 6 on the first sub-board 2 through 11. The other end of the resistor 6 becomes a logic low (Low) according to the ground information acquired from the main board 1 connected to the power supply. This logic Low information is supplied to the first address discrimination circuit 7 and used as address discrimination information.
一方、第２の副基板３について考えると、抵抗器９の一
端は主基板１からの接地情報を受けるとことができない
ので、論理的にはハイ（High）の状態となる。この論理
Highの情報は、第２のアドレス判別回路10へ供給されて
アドレス解読のための情報として用いられる。On the other hand, considering the second sub-board 3, one end of the resistor 9 cannot receive the ground information from the main board 1 and therefore is logically in a high state. This logic
The High information is supplied to the second address discrimination circuit 10 and used as information for address decoding.
以上述べたように、第１の副基板２と第２の副基板３は
同じプリント基板であるにもかかわらず、コネクタを通
して主基板１から受けると接地情報の有無に対応して論
理High,Lowを作り出すことができ、異るアドレス設定が
可能なる。As described above, even though the first sub-board 2 and the second sub-board 3 are the same printed circuit board, when they are received from the main board 1 through the connector, they are logically High, Low corresponding to the presence or absence of ground information. Can be created and different address settings can be made.
以上説明したように本考案は、アドレス設定情報として
接地情報を利用し、接地情報を主基板から受けとるか、
受けとらないかによって２種の状態を作り出すことによ
り、第１の副基板と第２の副基板の２つの副基板を同一
の基板として用いることができる効果がある。As described above, the present invention uses the ground information as the address setting information and receives the ground information from the main board.
By creating two kinds of states depending on whether or not they are received, there is an effect that the two sub-boards of the first sub-board and the second sub-board can be used as the same board.
第１図は本考案の一実施例の側面図である。 １……主基板、２……第１の副基板、３……第２の副基
板、４……接地部、５……第１のコネクタ、６……抵抗
器、７……第１のアドレス判別回路、８……第２のコネ
クタ、９……抵抗器、10……第２のアドレス判別回路、
11……接続路。FIG. 1 is a side view of an embodiment of the present invention. 1 ... Main board, 2 ... First sub board, 3 ... Second sub board, 4 ... Grounding section, 5 ... First connector, 6 ... Resistor, 7 ... First Address discrimination circuit, 8 ... second connector, 9 ... resistor, 10 ... second address discrimination circuit,
11 ... Connection path.
Claims (1)
スを設定するためのアドレス設定構造であって、１つの
機能ユニットを形成する１つの主基板ならびに第１およ
び第２の２つの副基板と、前記第１および第２の副基板
を前記主基板の一面に平行に保持して電気的かつ構造的
に結合させ互いに配設位置を異にする第１および第２の
２つのコネクタと、前記主基板の接地情報を前記第１の
コネクタを介して受け前記接地情報を前記第１の副基板
のアドレス判別情報として判別し出力する第１のアドレ
ス判別回路と、前記接地情報を受けない状態を前記第２
の副基板のアドレス判別情報として判別し出力する第２
のアドレス判別回路とを備えて成ることを特徴とするア
ドレス設定構造。1. An address setting structure for setting an identification address for mounting on a printed circuit board, comprising one main board forming one functional unit and two first and second sub boards. A first connector and a second connector that hold the first and second sub-boards in parallel with one surface of the main board and electrically and structurally couple them to each other and dispose them at different positions. A first address discriminating circuit that receives ground information of the main board via the first connector and discriminates and outputs the ground information as address discrimination information of the first sub-board, and a state of not receiving the ground information. The second
Second, which is determined and output as the address determination information of the sub-board of
An address setting structure comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3119190U JPH0755012Y2 (en) | 1990-03-27 | 1990-03-27 | Address setting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3119190U JPH0755012Y2 (en) | 1990-03-27 | 1990-03-27 | Address setting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03122573U JPH03122573U (en) | 1991-12-13 |
| JPH0755012Y2 true JPH0755012Y2 (en) | 1995-12-18 |
Family
ID=31533928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3119190U Expired - Lifetime JPH0755012Y2 (en) | 1990-03-27 | 1990-03-27 | Address setting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0755012Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9619000B2 (en) * | 2013-05-17 | 2017-04-11 | Nec Corporation | Board, board apparatus and method for interconnection of boards |
-
1990
- 1990-03-27 JP JP3119190U patent/JPH0755012Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03122573U (en) | 1991-12-13 |
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