JPH0750702B2 - Method of forming an insulator on a patterned conductive layer - Google Patents
Method of forming an insulator on a patterned conductive layerInfo
- Publication number
- JPH0750702B2 JPH0750702B2 JP60128392A JP12839285A JPH0750702B2 JP H0750702 B2 JPH0750702 B2 JP H0750702B2 JP 60128392 A JP60128392 A JP 60128392A JP 12839285 A JP12839285 A JP 12839285A JP H0750702 B2 JPH0750702 B2 JP H0750702B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating layer
- conductive layer
- insulating
- adjacent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 28
- 239000012212 insulator Substances 0.000 title claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- 150000008282 halocarbons Chemical class 0.000 claims 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 21
- 239000002184 metal Substances 0.000 description 21
- 239000004020 conductor Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 3
- 238000010292 electrical insulation Methods 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- OYLRFHLPEAGKJU-UHFFFAOYSA-N phosphane silicic acid Chemical compound P.[Si](O)(O)(O)O OYLRFHLPEAGKJU-UHFFFAOYSA-N 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- DLYUQMMRRRQYAE-UHFFFAOYSA-N tetraphosphorus decaoxide Chemical compound O1P(O2)(=O)OP3(=O)OP1(=O)OP2(=O)O3 DLYUQMMRRRQYAE-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 本発明はパターン化した第１導電層を具え、前記導電層
はこの導電層の隣接部分より上に上向きに突出する部分
を有し、さらに電気絶縁層を具え、前記電気絶縁層は、
前記導電層および本体の隣接部分上に、前記絶縁層の一
部分が前記絶縁層の隣接部分より上に特に前記導電層の
突出部分の位置において上向きに突出するように形成さ
れている本体上に絶縁層を形成する方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention comprises a patterned first conductive layer, said conductive layer having an upwardly projecting portion above an adjacent portion of said conductive layer, and further comprising an electrically insulating layer, The electrical insulation layer is
Insulation on a body formed on the conductive layer and the adjacent portion of the body such that a portion of the insulating layer projects above the adjacent portion of the insulating layer, particularly at the location of the protruding portion of the conductive layer. It relates to a method of forming a layer.
能動半導体領域をケイ素ウエハーの表面に沿って分離す
る従来技術は酸化物による分離であって、この技術では
二酸化ケイ素の厚い絶縁フィールド領域を能動領域の回
りの側面に成長させる。かかるデバイスにおける能動領
域の端縁に沿った区域において、フィールド酸化物は酸
化物の隣接部分およびケイ素領域より上に上向きに突出
する鳥の頭の形状をしていることが多い。A conventional technique for isolating active semiconductor regions along the surface of a silicon wafer is oxide isolation, in which a thick insulating field region of silicon dioxide is grown laterally around the active region. In the area along the edges of the active area in such devices, the field oxide is often in the shape of a bird's head that projects above the adjacent portion of the oxide and the silicon area.
能動領域の所定の部分に対する電気接点は、酸化物およ
びケイ素領域の上に横たわるパターン化した導電層によ
って作られる。普通導電層は金属層を構体の頂面上に堆
積させ、次いで金属の望ましくない部分を除去すること
により生成する。この結果、生成する上側表面に沿って
少くとも２種の高さの差が生ずる。一方の高さの差は鳥
の頭の上の金属部分の頂面から隣接金属の頂面までの間
で生ずる。他方の高さの差は残りの金属の端縁において
生ずる。Electrical contacts to selected portions of the active area are made by the patterned conductive layer overlying the oxide and silicon areas. The conductive layer is usually produced by depositing a metal layer on the top surface of the structure and then removing the undesired portions of the metal. This results in at least two height differences along the generated upper surface. One height difference occurs between the top of the metal on the bird's head and the top of the adjacent metal. The other height difference occurs at the remaining metal edges.
他のパターン化した金属層の使用しようとする場合に
は、先ず構体の上側表面に上に絶縁層を堆積させる。一
般的にこの絶縁層の頂面の形状は第１金属層の形状を反
映したものとなる。米国特許第3.962.779号（アール・
エドワード等）は、例えば、絶縁層の頂面が鳥の頭の上
で最大高さに達し、第１金属層の端縁を越えた区域で最
小高さに低下することを示している。かかる表面のでこ
ぼこは第２金属層による良好な被覆を設ける際に困難を
生ずる。If another patterned metal layer is to be used, an insulating layer is first deposited on the upper surface of the structure. Generally, the shape of the top surface of the insulating layer reflects the shape of the first metal layer. U.S. Patent No. 3.962.779 (Earl
(Edward et al.), For example, show that the top surface of the insulating layer reaches a maximum height above the bird's head and falls to a minimum height above the edge of the first metal layer. Such surface irregularities cause difficulties in providing good coverage with the second metal layer.
この種類の構体におけるかかる非平坦性は、例えば米国
特許第4,025,411号（ワイ・ホムーマ等）に記載されて
いるように、鳥の頭をいくらかまたは全部除去すること
により軽減することができる。この米国特許によれば、
フォトレジスト層を鳥の頭の上および構体の隣接部分の
上に、ホトレジスト層の上側表面がほぼ平坦になるよう
に形成する。次いでこの構体をスパッタエッチングす
る。この際フォトレジストおよび二酸化ケイ素はほぼ同
じ速度で侵される。従って、鳥の頭は除去されるが、酸
化物分離領域の隣接部分は除去されない。表面の非平坦
性を減少する際には、エッチングを全く注意深く制御し
て能動領域中への貫入を回避する必要がある。Such non-flatness in this type of structure can be mitigated by removing some or all of the bird's head, as described, for example, in US Pat. No. 4,025,411 (Wai Homma et al.). According to this US patent,
A photoresist layer is formed over the bird's head and adjacent portions of the structure such that the upper surface of the photoresist layer is substantially planar. Then, this structure is sputter-etched. At this time, the photoresist and silicon dioxide are attacked at almost the same rate. Thus, the bird's head is removed, but not adjacent to the oxide isolation region. When reducing surface non-planarity, the etching needs to be quite carefully controlled to avoid penetration into the active area.
前記米国特許によれば、平坦面上に位置するパターン化
した金属層上に形成された絶縁層を平坦化する際に類似
の技術を使用する。取の頭は存在しない。ほぼ平坦な上
側表面を有する重合体層を金属の上および絶縁層の隣接
部分の上に形成する。次いでこの構体をイオンビームに
よって処理して金属が露出するまで平坦面を下げる。こ
の技術はある限定された用途では有用であるが、この技
術は第１金属が鳥の頭の上に横たわりかつこれを上に横
たわる第２金属層の部分から電気的に分離する必要があ
る場合にまでは及ばない。According to said US patent, similar techniques are used in planarizing an insulating layer formed on a patterned metal layer located on a flat surface. There is no head of Tori. A polymer layer having a substantially flat upper surface is formed on the metal and on an adjacent portion of the insulating layer. The structure is then treated with an ion beam to lower the flat surface until the metal is exposed. While this technique is useful in certain limited applications, it is used when the first metal overlies the bird's head and needs to be electrically isolated from the portion of the second metal layer overlying it. It does not reach to.
本発明の目的は電気絶縁性を犠牲にせずに表面の非平坦
性を減少する方法によって構体を製造することにある。
本発明方法は特に鳥の頭が表面の非平坦性の原因となっ
ている酸化物で分離された半導体デバイスに適用できる
が、また類似の表面の不規則性が存在する他のデバイス
にも適用される。It is an object of the present invention to fabricate a structure by a method that reduces surface non-planarity without sacrificing electrical insulation.
The method of the invention is particularly applicable to oxide-isolated semiconductor devices in which the bird's head is responsible for surface non-planarity, but also to other devices in which similar surface irregularities are present. To be done.
本発明方法は、実質的に平坦な表面を有する追加層を前
記絶縁層上に形成し、前記絶縁層の材料より著しく前記
追加層の材料を侵す第１エッチング剤により前記追加層
をエッチングすることによって、前記絶縁層の突出部分
の少くとも一部分を露出させ、次いで前記追加層の残部
および露出された前記絶縁層を、前記絶縁層および前記
追加層の材料を実質的に同じ速度で侵す第２エッチング
剤によりエッチングすることを特徴とする。The method of the present invention comprises forming an additional layer having a substantially flat surface on said insulating layer and etching said additional layer with a first etchant which attacks the material of said additional layer significantly more than the material of said insulating layer. Exposing at least a portion of the protruding portion of the insulating layer and then attacking the remainder of the additional layer and the exposed insulating layer at substantially the same rate as the insulating layer and the material of the additional layer. It is characterized by etching with an etching agent.
導電層の突出部分は、例えば、酸化物分離領域の鳥の頭
の結果として生じる。電気絶縁層が導電層の上および本
体の隣接部分の上に形成された際に、導電層の突出部分
の位置における絶縁層の部分が同様に上向きに突出す
る。The protruding portion of the conductive layer results, for example, from a bird's head in the oxide isolation region. When the electrically insulating layer is formed on the conductive layer and on the adjacent part of the body, the part of the insulating layer at the position of the protruding part of the conductive layer likewise projects upwards.
平坦な上側表面を有する追加層は普通、ホトレジスト層
を堆積させ、次いでこれを表面がほぼ平坦になるまで加
熱することによって、絶縁層上に形成される。絶縁層
の、例えば、エッチングによる露出は、その突出部分に
隣接する絶縁層の部分が露出しないうちに終らせるのが
普通である。An additional layer having a flat upper surface is usually formed on the insulating layer by depositing a photoresist layer and then heating it until the surface is substantially flat. The exposure of the insulating layer, for example by etching, is usually terminated before the portion of the insulating layer adjacent to the protruding portion is exposed.
第２エッチング剤によるエッチングは導電層のどの部分
も露出しないうちに終らせるのが普通である。従って、
絶縁性上側表面は、この絶縁性上側表面が導電層の上側
表面にほぼ合致している導電層の突出部分の上を除き、
ほぼ平坦である。Etching with the second etchant is typically completed before any portion of the conductive layer is exposed. Therefore,
The insulative upper surface, except on the protruding portion of the conductive layer, where the insulative upper surface substantially conforms to the upper surface of the conductive layer,
It is almost flat.
そこで介在部分を形成するための１個以上の開口を、導
電層に達するまで絶縁層の残部中にエツチングすること
ができる。絶縁層の残部は導電層の側方端縁を越えた部
分では前記導電層の上の部分より厚さが厚いので介在部
分は大きすぎる大きさにする−−すなわち、下にある導
電層部分より幅を広くする−−ことができ、しかも介在
部分は導電層に隣接する絶縁材料を貫通することはな
い。これにより絶縁材料の下の材料中への望ましくない
侵入が回避される。次いで第２のパターン化した導電層
を絶縁層の残部の上に形成する。導電層は介在部分を介
して選択的に互に接触する。第１導電層の突出部分にお
いて導電層のある部分間の接触が望ましくない場合に
は、絶縁層の残部の合致する部分が所要の分離を提供す
る。There, one or more openings for forming intervening portions can be etched into the rest of the insulating layer until reaching the conductive layer. The remaining portion of the insulating layer is thicker than the portion above the conductive layer in the portion beyond the lateral edge of the conductive layer, so the intervening portion is made too large--that is, the portion below the conductive layer. The width can be increased, and the intervening portion does not penetrate the insulating material adjacent to the conductive layer. This avoids undesired penetration into the material below the insulating material. A second patterned conductive layer is then formed over the rest of the insulating layer. The conductive layers selectively contact each other via the intervening portion. If contact between certain portions of the conductive layer at the protruding portion of the first conductive layer is not desired, the matching portion of the rest of the insulating layer provides the required isolation.
本発明を図面を参照して例について説明する。The invention will be described by way of example with reference to the drawings.
第1a〜1g図は酸化物で分離された半導体構体の製造工程
を示す正面図であって、この半導体構体は高度の平坦特
性を有し、これにより多重導電層の使用が容易になる。
第2e〜2g図はそれぞれ第1e〜1g図に示す工程の側面図で
ある。特記しない限り、次の操作を大気圧および常温
（約25℃）で行う。1a to 1g are front views showing a process of manufacturing a semiconductor structure separated by an oxide, which semiconductor structure has a high degree of flatness characteristics, which facilitates the use of multiple conductive layers.
2e-2g are side views of the steps shown in FIGS. 1e-1g, respectively. Unless otherwise specified, perform the following operations at atmospheric pressure and room temperature (about 25 ° C).
出発材料は半導体本体10で、本体10は適当なＰ形および
／またはＮ形半導体不純物をドーブした単結晶ケイ素基
板を有する。本体10は基板の頂面に沿ってエピタキシヤ
ル層（図面には明示されていない）を有することができ
る。The starting material is a semiconductor body 10, which has a single crystal silicon substrate doped with suitable P-type and / or N-type semiconductor impurities. The body 10 can have an epitaxial layer (not explicitly shown in the drawing) along the top surface of the substrate.
厚さ約1.4ミクロンの厚い二酸化ケイ素の電気絶縁領域1
2を従来技術によって本体10の上側表面に沿って成長さ
せて能動半導体領域14の側面を取囲み、これによりこの
領域を他のかかる能動半導体領域から分離する。これは
代表的な例では、本体10の上側表面に沿ってオキシ窒化
ケイ素層を形成し、このオキシ窒化ケイ素層を通ってそ
の下にあるケイ素中に、酸化物分離領域12に予定されて
いる位置において溝を形成し次いでこの構体を加熱して
領域12を成長させることにより行われる。次の工程で
は、オキシ窒化物層を除去し、次いで種々のＮ形および
／またはＰ形の領域（図示せず）を領域14に形成する。
単結晶ケイ素以外の物質を領域14の頂面から除去する。
かくして第1a図に示す構体が得られる。Electrically insulating region of thick silicon dioxide about 1.4 microns thick 1
2 is grown by conventional techniques along the upper surface of the body 10 to surround the sides of the active semiconductor region 14, thereby isolating this region from other such active semiconductor regions. This typically forms a layer of silicon oxynitride along the upper surface of body 10 and is intended for oxide isolation region 12 through the silicon oxynitride layer and into the underlying silicon. This is done by forming trenches in position and then heating the structure to grow region 12. The next step is to remove the oxynitride layer and then form various N-type and / or P-type regions (not shown) in region 14.
Materials other than single crystal silicon are removed from the top surface of region 14.
Thus, the structure shown in FIG. 1a is obtained.
酸化物による分離処理の結果として、フィールド酸化物
領域12は領域14の端縁に沿って鳥の頭の形状をした上向
き突出部分16を有する。鳥の頭16はこれに隣接する絶縁
体12の主要部分18より上に約0.4ミクロン突出し、能動
領域14より上に先の場合より数十ナノメータ小さく突出
する。As a result of the oxide isolation treatment, the field oxide region 12 has an upwardly projecting portion 16 in the shape of a bird's head along the edge of the region 14. The bird's head 16 projects about 0.4 microns above the adjacent major portion 18 of the insulator 12 and tens of nanometers above the active region 14 than before.
厚さ約0.5ミクロンのパターン化した導電層20を第1b図
に示すように鳥の頭16並びにこれに隣接する領域14およ
び18の部分上に形成する。導電層20は、0.5％の銅を含
有するアルミニウム合金のような金属の層を構体の上側
表面全体の上に堆積させ、層20に予定されている位置の
上にフォトレジストマスクを形成し、次いで金属層の望
ましくない部分を三塩化ホウ素と塩素とからなるプラズ
マのようなエッチング剤によって除去することにより形
成する。第1b図において、層20はこの図の平面に平行に
延在する導体トラックである。鳥の頭16に起因して、層
20の部分22はこれに隣接する層20の部分より上に上向き
に突出する。A patterned conductive layer 20 about 0.5 microns thick is formed on the bird's head 16 and adjacent portions of regions 14 and 18 as shown in FIG. 1b. The conductive layer 20 comprises depositing a layer of metal, such as an aluminum alloy containing 0.5% copper, over the entire upper surface of the structure, forming a photoresist mask over the locations intended for layer 20, The undesired portion of the metal layer is then formed by removing it with an etchant, such as a plasma of boron trichloride and chlorine. In FIG. 1b, the layer 20 is a conductor track extending parallel to the plane of this figure. Layers due to bird head 16
Portion 22 of 20 projects upwardly above the portion of layer 20 adjacent thereto.
約12％の五酸化リンを含有する二酸化ケイ素の電気絶縁
層24を第1c図に示すように構体の頂面の全体の上に化学
的に蒸着させる。リン−ケイ酸塩ガラス（PSG）層24は
平均1.4ミクロンの厚さを有する。この堆積は大気圧で
行われるので、金属突出部22の上には僅かに多量のPSG
が堆積する。この結果、誘電層24は金属突出部22の上に
厚さ約1.55ミクロンの上向き突出部分26を有する。これ
により約0.55ミクロンの高さの差tuが、酸化物突出部分
26の頂面と、主要フィールド酸化物部分18の上の導体20
の上に横たわる絶縁体24の隣接部分の頂面との間に存在
する。導体20の端縁における段差が絶縁層24に大きな影
響を与える。従って、約0.5ミクロクの高さの差tLが、
主要絶縁部分18と接触する層24の部分の頂面と、層20の
上の層24の隣接部分の頂面との間に存在する。An electrically insulating layer 24 of silicon dioxide containing about 12% phosphorus pentoxide is chemically deposited over the entire top surface of the structure as shown in Figure 1c. The phosphorus-silicate glass (PSG) layer 24 has an average thickness of 1.4 microns. Since this deposition is carried out at atmospheric pressure, a slightly large amount of PSG is present on the metal protrusion 22.
Is deposited. As a result, the dielectric layer 24 has an upwardly protruding portion 26 above the metal protrusion 22 that is approximately 1.55 microns thick. This results in a height difference t u of about 0.55 microns,
Conductor 20 on top of 26 and above main field oxide portion 18
Between the top surface of the adjacent portion of the overlying insulator 24. The step at the edge of the conductor 20 greatly affects the insulating layer 24. Therefore, the height difference t L of about 0.5 microc is
It exists between the top surface of the portion of layer 24 in contact with main insulating portion 18 and the top surface of the adjacent portion of layer 24 above layer 20.
約1.2ミクロンのハントのポジティブ・フォトレジスト
（Hunt′s Positive Photoresist）204を誘電体24の上
側表面全体の上に堆積させる。このフォトレジストを10
3℃で30分間熱処理し、次いで平行な方向を有する放射
に曝す。次いでこのフォトレジストを200℃で30分間加
熱する。かかる処理によりフォトレジストは第1d図に示
すように極めて平坦な上側表面を有する層28になるまで
流れる。A Hunt's Positive Photoresist 204 of about 1.2 microns is deposited over the entire top surface of the dielectric 24. This photoresist 10
Heat treated at 3 ° C. for 30 minutes, then exposed to radiation with parallel directions. The photoresist is then heated at 200 ° C for 30 minutes. Such treatment causes the photoresist to flow to a layer 28 having a very flat upper surface as shown in Figure 1d.
この構体は、例えば、AME8110ヘキソイダル（hexoida
l）プラズマ反応器（アプライド・マテリアルス社製）
内に置く。この反応器を80ミリトル（milli−torr）の
圧力まで排気する。この構体に流量80標準cm3/分（SCC
M）の酸素からなるプラズマを5.5分間作用させる。反応
器に対するRF出力は1350ワットである。酸素プラズマは
層24のPSGより著しく（有効に無限に）層28のフォトレ
ジストを侵す。かくして、第1eおよび2e図に示すよう
に、フォトレジスト層28がエッチング除去された際に突
出部分26の一部分が露出する。突出部分26の露出部分は
生成する層28の残部の上側表面より上に約0.35ミクロン
突出する。This structure is, for example, the AME8110 hexoidal
l) Plasma reactor (manufactured by Applied Materials)
Put it inside. The reactor is evacuated to a pressure of 80 milli-torr. Flow rate of 80 standard cm 3 / min (SCC
The plasma consisting of M) oxygen is applied for 5.5 minutes. The RF power to the reactor is 1350 watts. The oxygen plasma attacks the photoresist in layer 28 significantly (effectively infinitely) than the PSG in layer 24. Thus, as shown in FIGS. 1e and 2e, a portion of the protruding portion 26 is exposed when the photoresist layer 28 is etched away. The exposed portion of the raised portion 26 projects about 0.35 microns above the upper surface of the remainder of the resulting layer 28.
この構体がプラズマ反応器内に置かれている間に、この
構体に流量33SCCMの酸素と47SCCMの四フッ化炭素とから
なるプラズマを14分間作用させる。RF出力は1350ワット
に維持する。酸素／四フッ化炭素プラズマはフォトレジ
ストおよびPSGを同じ速度に極めて近い速度で侵す。フ
ォトレジスト層28および絶縁層24の上側表面の材料は露
出するにつれて漸次除去される。上側表面は第1fおよび
2f図の構体が達成されるまで、すべての点においてほぼ
同程度下方に移動する。While the structure is placed in the plasma reactor, a plasma consisting of oxygen at a flow rate of 33 SCCM and carbon tetrafluoride at 47 SCCM is applied to the structure for 14 minutes. RF power is maintained at 1350 watts. The oxygen / carbon tetrafluoride plasma attacks the photoresist and PSG very close to the same rate. The material on the upper surfaces of photoresist layer 28 and insulating layer 24 is gradually removed as it is exposed. The upper surface is 1f and
All the points move approximately the same downward until the structure shown in Figure 2f is achieved.
導体20の端縁における段差は誘電体24の残部30には影響
は及ぼさない。絶縁性突出部分26の残部32は導電性突出
部分22の上側表面にほぼ合致している。絶縁性上側表面
の最低部と最高部との高さの差tFは約0.35ミクロンにす
ぎない。従って絶縁体30は、部分32における最小値約0.
9ミクロンから、誘電体30が主要フィールド酸化物部分1
8と隣接する箇所における最大値約1.4ミクロンまで変化
する厚さを有する。酸化物の厚さも誘電体30が能動領域
14と隣接する箇所において約1.4ミクロンである。The step at the edge of the conductor 20 does not affect the rest 30 of the dielectric 24. The remainder 32 of the insulative protrusion 26 substantially conforms to the upper surface of the electrically conductive protrusion 22. The height difference t F between the bottom and top of the insulating upper surface is only about 0.35 micron. Therefore, the insulator 30 has a minimum value of about 0.
From 9 microns, dielectric 30 is the main field oxide part 1
It has a thickness that varies up to a maximum of about 1.4 microns in the area adjacent to 8. The thickness of the oxide is also the active area of the dielectric 30.
It is about 1.4 microns at the point adjacent to 14.
第1g図に示すような介在部分（即ち、通路）34のための
開口を構体の上側表面に沿った選定された位置において
導体20に達するまで絶縁体30中に形成する。かかる介在
部分は、代表的な例ではフォトレジストマスクを形成
し、このホトレジストに開けた孔から従来のフッ化水素
酸溶液による2.5分間の処理とCHF3/CO2/Heプラズマによ
る３分間の処理との組合せによってエッチングし、次い
でこのフォトレジストマスクを除去することにより形成
する。介在部分34が僅か整合していないように示されて
いる第2g図から分るように、介在部分34は大きすぎる大
きさに作りしかも導体20に隣接する絶縁体30の全体を貫
通しないように作ることができる。層30の厚さは層20の
端縁を越えた部分で一層厚くなっているのでエッチング
に対して安全な所要の縁部が提供される。Openings for intervening portions (ie passages) 34 as shown in Figure 1g are formed in the insulator 30 at selected locations along the upper surface of the structure until the conductor 20 is reached. A typical example of this intervening portion is to form a photoresist mask, and a conventional hydrofluoric acid solution is used for 2.5 minutes through a hole formed in the photoresist and a CHF 3 / CO 2 / He plasma treatment is performed for 3 minutes. Etching is performed by the combination with and then the photoresist mask is removed. As can be seen from FIG. 2g, where the interposer 34 is shown to be slightly misaligned, the interposer 34 should be oversized and should not penetrate the entire insulator 30 adjacent to the conductor 20. Can be made. The thickness of layer 30 is thicker beyond the edges of layer 20 to provide the required edges that are safe to etch.
厚さ1.0ミクロンのパターン化した導電層36を構体の上
側表面上に形成する。導電層36は、0.5％の銅を含有す
るアルミニウム合金のような金属の層を上側表面全体の
上に堆積させ、層36に予定されている位置の上にフォト
レジストマスクを形成し、次いで金属層の望ましくない
部分を上述のアルミニウム・エッチング剤によって除去
することにより生成する。第1g図は層36の２個の部分を
示し、これらの各部分はその一部が鳥の頭16の上に位置
しかつ図面の平面に垂直に延在する導電体トラックであ
る。これらのトラックの一方は介在部分34を介して突出
導電部分22と接触し、これらのトラックの他方は突出す
る絶縁性部分32によって突出部分22から絶縁されてい
る。そこで構体を従来方法で仕上げることができる。A 1.0 micron thick patterned conductive layer 36 is formed on the upper surface of the structure. The conductive layer 36 is formed by depositing a layer of metal, such as an aluminum alloy containing 0.5% copper, over the entire upper surface, forming a photoresist mask over the locations intended for layer 36, and then depositing the metal. Produced by removing unwanted portions of the layer with the aluminum etchant described above. FIG. 1g shows two portions of layer 36, each of which is a conductor track, a portion of which lies above the bird's head 16 and extends perpendicular to the plane of the drawing. One of these tracks contacts the protruding conductive portion 22 via an intervening portion 34, and the other of these tracks is insulated from the protruding portion 22 by a protruding insulating portion 32. The structure can then be finished by conventional methods.
本発明を特定の例について説明したが、かかる説明は例
示のためのものであるにすぎず、本発明の範囲を限定す
るものと解すべきでない。例えば、絶縁体24はどの部分
においてもほぼ一定の厚さを有するように形成すること
ができる。層28のためのほぼ平坦な上側表面は上述の堆
積／加熱技術以外の技術で生成することができる。層28
の形成にフォトレジスト以外の材料を使用することがで
きる。金属合金の代りにドープした多結晶ケイ素を導体
20および36のそれぞれのために使用することができる。
従って、当業者は種々の修正、変更および適用を本発明
の真の範囲および精神から逸脱することなく行うことが
できる。Although the present invention has been described in terms of particular examples, such description is for the purpose of illustration only and should not be construed as limiting the scope of the invention. For example, the insulator 24 can be formed to have a substantially constant thickness in any part. The substantially planar upper surface for layer 28 can be produced by techniques other than the deposition / heating techniques described above. Layer 28
Materials other than photoresist can be used to form the. Conductor made of polycrystalline silicon doped instead of metal alloy
Can be used for each of 20 and 36.
Therefore, various modifications, changes and applications can be made by those skilled in the art without departing from the true scope and spirit of the present invention.
第1a,1b,1c,1d,1e,1fおよび1g図は本発明方法の各段階
における半導体構造の断面図、 第2e,2fおよび2g図はそれぞれ第1e,1fおよび1g図におけ
る2e−2e,2f−2fおよび2g−2g面で切断した半導体構造
の断面図である。 10……半導体本体 12……電気絶縁領域 （分離領域、フィールド酸化物領域、絶縁体） 14……能動半導体領域（能動領域） 16……上向き突出部分（鳥の頭） 18……絶縁体12の主要部分 （主要フィールド酸化物部分，主要絶縁部分） 20……導電層（導体） 22……上向きに突出する導電層20の部分 （金属突出部分，突出導電部分） 24……電気絶縁層 （リン・ケイ酸塩ガラス（PSG）層，絶縁体，誘電体，
誘電層） 26……上向き突出部分（酸化物突出部分） 28……フォトレジスト層（追加層） 30……誘電体24の残部（絶縁体，誘電体） 32……突出部分26の残部（絶縁性部分） 34……介在部分、36……誘電層（導体）1a, 1b, 1c, 1d, 1e, 1f and 1g are cross-sectional views of the semiconductor structure at each stage of the method of the present invention, 2e, 2f and 2g are 1e, 1f and 2e-2e in 1g, respectively. 2f is a cross-sectional view of the semiconductor structure cut along the 2f-2f and 2g-2g planes. 10 …… Semiconductor body 12 …… Electrical insulation area (separation area, field oxide area, insulator) 14 …… Active semiconductor area (active area) 16 …… Upward protruding part (bird's head) 18 …… Insulator 12 Main part (main field oxide part, main insulating part) 20 …… conductive layer (conductor) 22 …… part of conductive layer 20 protruding upward (metal protruding part, protruding conductive part) 24 …… electrical insulating layer ( Phosphorus-silicate glass (PSG) layer, insulator, dielectric,
Dielectric layer) 26 …… Upward protruding part (oxide protruding part) 28 …… Photoresist layer (additional layer) 30 …… Remainder of dielectric 24 (insulator, dielectric) 32 …… Remaining protruding part 26 (insulation) 34 …… Interposed portion, 36 …… Dielectric layer (conductor)
Claims (16)
電層はこの導電層の隣接部分より上に上向きに突出する
部分を有し、さらに電気絶縁層を具え、前記電気絶縁層
は、前記導電層および本体の隣接部分上に、前記絶縁層
の一部分が前記絶縁層の隣接部分より上に特に前記導電
層の突出部分の位置において上向きに突出するように形
成されている本体上に絶縁層を形成するに当り、 実質的に平坦な表面を有する追加層を前記絶縁層上に形
成し、 前記絶縁層の材料より著しく前記追加層の材料を侵す第
１エッチング剤により前記追加層をエッチングすること
によって、前記絶縁層の突出部分の少なくとも一部を露
出させ、 次いで前記追加層の残部および露出された前記絶縁層
を、前記絶縁層および前記追加層の材料を実質的に同じ
速度で侵す第２エッチング剤によりエッチングすること
を特徴とするパターン化した導電層上に絶縁体を形成す
る方法。1. A patterned first conductive layer, said conductive layer having an upwardly projecting portion above an adjacent portion of said conductive layer, further comprising an electrically insulating layer, said electrically insulating layer comprising: Insulation on a body formed on the conductive layer and the adjacent portion of the body such that a portion of the insulating layer projects above the adjacent portion of the insulating layer, particularly at the location of the protruding portion of the conductive layer. In forming the layer, an additional layer having a substantially flat surface is formed on the insulating layer, and the additional layer is etched by a first etchant that attacks the material of the additional layer significantly more than the material of the insulating layer. Exposing at least a portion of the protruding portion of the insulating layer, and then attacking the remainder of the additional layer and the exposed insulating layer at substantially the same rate as the insulating layer and the material of the additional layer. A method of forming an insulator patterned conductive layer, characterized by etching by the second etchant.
が露出しないうちに前記絶縁層の露出を終らせる特許請
求の範囲第１項記載の方法。2. The method according to claim 1, wherein the exposure of the insulating layer is terminated before the portion of the insulating layer adjacent to the protruding portion is exposed.
エッチング工程を終らせる特許請求の範囲第２項記載の
方法。3. The method of claim 2 wherein the etching step is terminated before any portion of the conductive layer is exposed.
記導電層に達する開口を作り、前記絶縁層の残部および
前記導電層の露出部分に第２のパターン化した導電層を
設ける特許請求の範囲第３項記載の方法。4. A patent for forming an opening through the insulating layer to the conductive layer for an intervening portion, and providing a second patterned conductive layer on the remainder of the insulating layer and the exposed portion of the conductive layer. The method according to claim 3.
きさに作り、前記開口が前記第１導電層の端縁に隣接す
る前記絶縁層の残部の全体を貫通する前に開口工程を終
らせる特許請求の範囲第４項記載の方法。5. An opening for the intervening portion is oversized, and the opening step is completed before the opening penetrates the entire remaining portion of the insulating layer adjacent to the edge of the first conductive layer. The method according to claim 4, wherein:
れている特許請求の範囲第１項記載の方法。6. The method of claim 1 wherein said additional layer comprises photoresist.
び 前記ホトレジスト層をその上側表面が極めて平坦になる
まで加熱する工程 を含む特許請求の範囲第６項記載の方法。7. The method of claim 6, wherein the step of forming the additional layer includes the steps of depositing a photoresist layer on the insulating layer, and heating the photoresist layer until its upper surface is very flat. Method described in section.
成されている特許請求の範囲第７項記載の方法。8. The method of claim 7, wherein the insulating layer is predominantly composed of a semiconductor oxide.
マである特許請求の範囲第８項記載の方法。9. The method of claim 8 wherein the first etchant is a plasma containing oxygen.
カーボンを含むプラズマである特許請求の範囲第９項記
載の方法。10. The method of claim 9 wherein the second etchant is a plasma containing oxygen and halocarbons.
み、前記ハロカーボンが四フッ化炭素を含む特許請求の
範囲第10項記載の方法。11. The method of claim 10 wherein the semiconductor oxide comprises silicon dioxide and the halocarbon comprises carbon tetrafluoride.
た電気絶縁領域を有す単結晶半導体構体を有し、前記絶
縁領域は特に前記導電層の突出部分の位置において、前
記絶縁領域の隣接部分より上に上向きに突出する端縁部
分を有し、前記導電層の厚さはほぼ一定である特許請求
の範囲第１項記載の方法。12. The body comprises a single crystal semiconductor structure having a patterned electrically insulating region on one surface, the insulating region being adjacent to the insulating region, particularly at the location of the protruding portion of the conductive layer. The method of claim 1 having an edge portion projecting upward above the portion, wherein the thickness of the conductive layer is substantially constant.
許請求の範囲第12項記載の方法。13. The method according to claim 12, wherein the insulating layer is formed by chemical vapor deposition.
許請求の範囲第13項記載の方法。14. The method according to claim 13, wherein the insulating layer is formed at atmospheric pressure.
接部分より厚さが厚い特許請求の範囲第14項記載の方
法。15. The method according to claim 14, wherein the protruding portion of the insulating layer is thicker than the adjacent portion of the insulating layer.
ている特許請求の範囲第15項記載の方法。16. The method according to claim 15, wherein the insulating layer is formed to have a substantially constant thickness.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US621001 | 1984-06-15 | ||
| US06/621,001 US4594769A (en) | 1984-06-15 | 1984-06-15 | Method of forming insulator of selectively varying thickness on patterned conductive layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6110257A JPS6110257A (en) | 1986-01-17 |
| JPH0750702B2 true JPH0750702B2 (en) | 1995-05-31 |
Family
ID=24488323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60128392A Expired - Fee Related JPH0750702B2 (en) | 1984-06-15 | 1985-06-14 | Method of forming an insulator on a patterned conductive layer |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US4594769A (en) |
| JP (1) | JPH0750702B2 (en) |
| CA (1) | CA1229180A (en) |
| DE (1) | DE3520083C2 (en) |
| FR (1) | FR2566180B1 (en) |
| GB (1) | GB2160359B (en) |
| IT (1) | IT1190363B (en) |
| NL (1) | NL8501688A (en) |
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|---|---|---|---|---|
| US4708767A (en) * | 1984-10-05 | 1987-11-24 | Signetics Corporation | Method for providing a semiconductor device with planarized contacts |
| JPS62282446A (en) * | 1986-05-31 | 1987-12-08 | Toshiba Corp | Manufacture of semiconductor device |
| NL8701717A (en) * | 1987-07-21 | 1989-02-16 | Philips Nv | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH A PLANARIZED STRUCTURE |
| US6074569A (en) * | 1997-12-09 | 2000-06-13 | Hughes Electronics Corporation | Stripping method for photoresist used as mask in Ch4 /H2 based reactive ion etching (RIE) of compound semiconductors |
| US6319796B1 (en) | 1999-08-18 | 2001-11-20 | Vlsi Technology, Inc. | Manufacture of an integrated circuit isolation structure |
| CN107665829B (en) * | 2017-08-24 | 2019-12-17 | 长江存储科技有限责任公司 | method for improving metal lead process safety in wafer hybrid bonding |
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| US3962779A (en) * | 1974-01-14 | 1976-06-15 | Bell Telephone Laboratories, Incorporated | Method for fabricating oxide isolated integrated circuits |
| DE2547792C3 (en) * | 1974-10-25 | 1978-08-31 | Hitachi, Ltd., Tokio | Method for manufacturing a semiconductor component |
| US4044454A (en) * | 1975-04-16 | 1977-08-30 | Ibm Corporation | Method for forming integrated circuit regions defined by recessed dielectric isolation |
| JPS5383467A (en) * | 1976-11-30 | 1978-07-22 | Nec Corp | Production of semiconductor device |
| JPS53129970A (en) * | 1977-04-20 | 1978-11-13 | Hitachi Ltd | Production of semiconductor device |
| US4222816A (en) * | 1978-12-26 | 1980-09-16 | International Business Machines Corporation | Method for reducing parasitic capacitance in integrated circuit structures |
| IE52971B1 (en) * | 1979-07-23 | 1988-04-27 | Fujitsu Ltd | Method of manufacturing a semiconductor device wherein first and second layers are formed |
| JPS5648140A (en) * | 1979-09-27 | 1981-05-01 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPS56108264A (en) * | 1980-01-31 | 1981-08-27 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| JPS5750436A (en) * | 1980-09-12 | 1982-03-24 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58135645A (en) * | 1982-02-08 | 1983-08-12 | Fujitsu Ltd | Manufacture of semiconductor device |
| US4481070A (en) * | 1984-04-04 | 1984-11-06 | Advanced Micro Devices, Inc. | Double planarization process for multilayer metallization of integrated circuit structures |
-
1984
- 1984-06-15 US US06/621,001 patent/US4594769A/en not_active Expired - Lifetime
-
1985
- 1985-06-05 DE DE3520083A patent/DE3520083C2/en not_active Expired - Fee Related
- 1985-06-12 GB GB08514823A patent/GB2160359B/en not_active Expired
- 1985-06-12 IT IT21117/85A patent/IT1190363B/en active
- 1985-06-12 NL NL8501688A patent/NL8501688A/en not_active Application Discontinuation
- 1985-06-12 CA CA000483809A patent/CA1229180A/en not_active Expired
- 1985-06-14 FR FR8509070A patent/FR2566180B1/en not_active Expired
- 1985-06-14 JP JP60128392A patent/JPH0750702B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| GB2160359A (en) | 1985-12-18 |
| FR2566180B1 (en) | 1989-07-28 |
| JPS6110257A (en) | 1986-01-17 |
| FR2566180A1 (en) | 1985-12-20 |
| NL8501688A (en) | 1986-01-02 |
| GB2160359B (en) | 1988-02-24 |
| US4594769A (en) | 1986-06-17 |
| CA1229180A (en) | 1987-11-10 |
| DE3520083C2 (en) | 1994-05-26 |
| IT1190363B (en) | 1988-02-16 |
| IT8521117A0 (en) | 1985-06-12 |
| GB8514823D0 (en) | 1985-07-17 |
| DE3520083A1 (en) | 1985-12-19 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |