JPH0741161Y2 - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH0741161Y2 JPH0741161Y2 JP1988096005U JP9600588U JPH0741161Y2 JP H0741161 Y2 JPH0741161 Y2 JP H0741161Y2 JP 1988096005 U JP1988096005 U JP 1988096005U JP 9600588 U JP9600588 U JP 9600588U JP H0741161 Y2 JPH0741161 Y2 JP H0741161Y2
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- ground
- metal substrate
- pattern
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Wire Bonding (AREA)
- Waveguides (AREA)
- Structure Of Printed Boards (AREA)
Description
【考案の詳細な説明】 （イ）産業上の利用分野 本考案は混成集積回路に関し、特に高周波回路が形成さ
れた混成集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit in which a high frequency circuit is formed.
（ロ）従来の技術 金属基板表面を絶縁薄層で絶縁して、その上に回路を組
み込むことは特公昭46−13234号公報で出願人が既に提
案しており、周知技術として知られている。(B) Conventional technology It has been proposed by the applicant in Japanese Examined Patent Publication No. 46-13234 that the surface of a metal substrate is insulated with an insulating thin layer and a circuit is incorporated thereon, and it is known as a well-known technique. .
斯る金属基板上に高周波回路（例えば数10MHz以上）を
形成した場合、小信号回路、パワー回路と独立した機能
をもつ回路間でグランドラインが引廻しにより共通イン
ピーダンスをもつと周波数特性の悪化、異常発振、独立
回路間のクロストーク等の問題が発生するため、通常第
６図に示す如く、金属基板（10）上にグランドパターン
（11）を形成し、そのグランドパターン（11）を任意一
点でA1線（12）等で金属基板（10）に落とすことで上述
した問題を解消していた。When a high-frequency circuit (for example, several tens of MHz or higher) is formed on such a metal substrate, the frequency characteristics deteriorate if the ground line has a common impedance between the small signal circuit and the circuit having a function independent of the power circuit, Since problems such as abnormal oscillation and crosstalk between independent circuits occur, normally, as shown in FIG. 6, a ground pattern (11) is formed on a metal substrate (10) and the ground pattern (11) is set at an arbitrary point. The above problem was solved by dropping it on the metal substrate (10) with the A1 wire (12).
（ハ）考案が解決しようとする課題 しかしながら、上述の如く、構成でグランドラインの共
通インピーダンスを極力小さくする場合、グランドパタ
ーン中にランドを作り回路を組み込むか、あるいはグラ
ンドパターンを極力太く、短くし、共通インピーダンス
を考慮したグランド廻りの設計が必要となり、性能面で
の限界がある問題点があった。(C) Problems to be solved by the invention However, as described above, when the common impedance of the ground line is made as small as possible in the configuration, a land is formed in the ground pattern to incorporate a circuit, or the ground pattern is made as thick and short as possible. However, there is a problem in that there is a limit in terms of performance because it is necessary to design the ground around considering the common impedance.
また、グランドパターンを太く形成しなければならず、
スペース的にロスが大きくなり小型の混成集積回路を提
供することが困難であるという大きな問題点があった。Also, the ground pattern must be formed thick,
There is a big problem that it is difficult to provide a small hybrid integrated circuit due to a large loss in space.
（ニ）課題を解決するための手段 本考案は上述した課題に鑑みて為されたものであり、絶
縁性金属基板と、前記基板上に形成された所望形状の導
体パターンと、前記導体パターン上に固着され複数の半
導体素子から形成された高周波回路と、前記半導体素子
が固着される前記導体パターンの一端と前記絶縁性金属
基板とを少なくとも一カ所で接続せしめる接続体とを備
えて解決する。(D) Means for Solving the Problems The present invention has been made in view of the above problems, and includes an insulating metal substrate, a conductor pattern of a desired shape formed on the substrate, and a conductor pattern on the conductor pattern. A high-frequency circuit formed by fixing a plurality of semiconductor elements to each other and a connection body for connecting one end of the conductor pattern to which the semiconductor elements are fixed and the insulating metal substrate at at least one place.
（ホ）作用 この様に本考案に依れば、半導体素子が固着される導体
パターンの一端と絶縁性金属基板とを少なくとも一カ所
で接続せしめる接続体を設けることにより、絶縁性金属
基板を接地ラインとして用いることができ、接地ライン
層をもつ多層基板と同等性能を単層絶縁性金属基板で実
現することができる。(E) Function As described above, according to the present invention, the insulating metal substrate is grounded by providing the connecting body for connecting one end of the conductor pattern to which the semiconductor element is fixed and the insulating metal substrate at at least one place. It can be used as a line, and a single-layer insulating metal substrate can achieve the same performance as a multilayer substrate having a ground line layer.
（ヘ）実施例 以下に図面に示した実施例に基づいて本考案を詳細に説
明する。(F) Embodiments The present invention will be described in detail below based on the embodiments shown in the drawings.
第１図は、本考案の混成集積回路を示す平面図であり、
（１）は絶縁性金属基板、（２）は導体パターン、
（２′）は導体より形成され、図のようにグランドパッ
ドより延在さたれアース接地用ライン、（３）は半導体
素子、（４）は導体パターン（２）と基板（１）とを接
地する接続部、（５）はザグリ部である。FIG. 1 is a plan view showing a hybrid integrated circuit of the present invention,
(1) is an insulating metal substrate, (2) is a conductor pattern,
(2 ') is formed of a conductor and extends from the ground pad as shown in the figure, and is a grounding line, (3) is a semiconductor element, and (4) is a conductor pattern (2) and the substrate (1) are grounded. A connecting portion, and (5) is a counterbore portion.
絶縁性金属基板（１）（以下基板という）はアルミニウ
ム基板等が用いられ、そのアルミニウム基板表面は周知
の陽極酸化技術によって酸化アルミニウム膜（６）が形
成され絶縁基板となされる。An aluminum substrate or the like is used as the insulating metal substrate (1) (hereinafter referred to as a substrate), and an aluminum oxide film (6) is formed on the surface of the aluminum substrate by a well-known anodic oxidation technique to form an insulating substrate.
その基板（１）上には第１図及び第２図から明らかな様
に絶縁樹脂薄層（７）を介して銅箔よりなる所望形状の
導体パターン（２）及びアース接地ライン（２′）が形
成される。導体パターン（２）上にトランジスタ、IC、
チップ抵抗、チップコンデンサ等の複数の半導体素子
（３）が固着される。As is apparent from FIGS. 1 and 2, a conductor pattern (2) of a desired shape made of copper foil and an earth ground line (2 ') are formed on the substrate (1) via an insulating resin thin layer (7). Is formed. Transistor, IC, on the conductor pattern (2)
A plurality of semiconductor elements (3) such as chip resistors and chip capacitors are fixed.
本考案の特徴とするところは、半導体素子（３）が固着
される導体パターン（２）の一端及びアース接地ライン
（２′）と基板（１）とを少なくとも一カ所以上で接続
させるところにある。即ち、本願は導体パターン（２）
及びアース接地ライン（２′）と基板（１）とを積極的
に複数カ所で接続させ基板（１）を接地ラインとして用
いるところにある。本来第１図において、基板（１）と
接続されている４つの導体パターン（２）は、これらを
１本（一体）につなぐと従来構造第６図のグランドパタ
ーン（11）に相当することになる。ここでグランドパッ
ドから延在された一番左側の導体パターン（２）をアー
ス接地ライン（２′）として区別して説明すると、この
ライン（２′）は、接続手段（４）で基板（１）を確実
にアース電位に固定する。従って従来のようにアースラ
インを基板の一端から他端まで張り巡らす必要はなく、
本来グランドパッドと一体で成るべき導体パターン
（２）（基板と接続されている残り３つのライン）を必
要最小限の長さに設け、接続手段を介して基板と接続す
れば、このパターン（２）を安定したOVに固定でき、更
には従来構造と比べて不要となった領域は、別の配線等
を設けることができる。従って安定したアース電圧に固
定でき、且つ高密度実装または小型化が可能となる。The present invention is characterized in that one end of the conductor pattern (2) to which the semiconductor element (3) is fixed and the earth ground line (2 ') are connected to the substrate (1) at least at one place or more. . That is, the present application is a conductor pattern (2)
Also, the grounding line (2 ') and the substrate (1) are positively connected at a plurality of points to use the substrate (1) as a grounding line. The four conductor patterns (2) originally connected to the substrate (1) in FIG. 1 correspond to the ground pattern (11) in FIG. 6 of the conventional structure when they are connected (integrated) to each other. Become. The leftmost conductor pattern (2) extending from the ground pad will be described as an earth ground line (2 '). This line (2') is connected to the substrate (1) by the connecting means (4). Is securely fixed to the ground potential. Therefore, it is not necessary to stretch the ground line from one end to the other end of the board as in the past.
If the conductor pattern (2) (the remaining three lines connected to the substrate) which should originally be formed integrally with the ground pad is provided in the minimum necessary length and connected to the substrate through the connecting means, this pattern (2 ) Can be fixed to a stable OV, and further wiring can be provided in a region which is unnecessary compared with the conventional structure. Therefore, a stable ground voltage can be fixed, and high-density mounting or miniaturization is possible.
導体パターン（２）及びアース接地ライン（２′）と基
板（１）との接続は第１図及び第２図に示す如く、基板
（１）にザグリ部（５）を設けて基板（１）を露出させ
接続体（４）によって接続される。ザグリ部（５）は導
体パターン（２）及びアース接地ライン（２′）上から
ドリルによって削る様に形成される。この結果ザグリ部
（５）は導体パターン（２）、アース接地ライン
（２′）下に形成されることになる。As shown in FIGS. 1 and 2, the conductor pattern (2) and the earth ground line (2 ') are connected to the substrate (1) by providing a counterbore (5) on the substrate (1). Exposed and connected by a connector (4). The counterbore (5) is formed by drilling from above the conductor pattern (2) and the earth ground line (2 '). As a result, the counterbore portion (5) is formed below the conductor pattern (2) and the earth ground line (2 ').
ザグリ部（５）を形成することによって基板（１）は露
出され、その露出された部分にA1線、Au線等の接続体
（４）を用いてボンディング接続が行われる。このと
き、導体パターン（２）及びアース接地ライン（２′）
上にはニッケルメッキ膜（８）が形成されてる。The substrate (1) is exposed by forming the countersunk portion (5), and bonding connection is performed on the exposed portion by using a connecting body (4) such as an A1 wire or an Au wire. At this time, the conductor pattern (2) and the earth ground line (2 ')
A nickel plating film (8) is formed on the top.
斯る本考案に依れば、基板（１）と導体パターン（２）
とを積極的且つ強制的に接続体（４）によって接続する
ことにより、基板（１）自体を接地ラインとして利用す
ることができ、従来の様にアース接地ラインのパターン
設計を不要とすることができる。According to the present invention, the substrate (1) and the conductor pattern (2)
By positively and forcibly connecting and with the connection body (4), the substrate (1) itself can be used as a ground line, and the pattern design of the ground / ground line as in the conventional case is unnecessary. it can.
また、接続体（４）は第３図及び第４図に示す如く、導
電性ペースト（４）を用いて行うことも可能である。こ
のとき、導電ペースト（４′）露出面を保護膜（９）で
被覆する。Further, the connecting body (4) can also be formed by using a conductive paste (4) as shown in FIGS. 3 and 4. At this time, the exposed surface of the conductive paste (4 ') is covered with the protective film (9).
また、第５図に示す如く、ザグリ部（５）をレーザによ
って形成した後、無電解メッキによって基板（１）と導
体パターン（２）とを接地することも可能である。Further, as shown in FIG. 5, it is also possible to ground the substrate (1) and the conductor pattern (2) by electroless plating after forming the countersunk portion (5) by laser.
（ト）考案の効果 以上に詳述した如く、本考案に依れば、基板自体を接地
ラインとして利用することができることにより、回路パ
ターンにおけるグランドパターンの面積を著しく削減す
ることができ、コンパクトな設計が可能となり、混成集
積回路の小型に大きく寄与できるものである。(G) Effect of the Invention As described in detail above, according to the present invention, the substrate itself can be used as a ground line, so that the area of the ground pattern in the circuit pattern can be remarkably reduced and a compact size can be achieved. The design becomes possible and it can greatly contribute to the miniaturization of the hybrid integrated circuit.
また、従来の様にグランドパターンの形状に電気的特性
上の考慮が不必要となり、回路パターン設計の簡略化が
計れるものである。Further, unlike the conventional case, the shape of the ground pattern does not need to be considered in terms of electrical characteristics, and the circuit pattern design can be simplified.
第１図及び第２図は本考案の混成集積回路を示す平面図
及び断面図、第３図乃至第５図は他の実施例を示す平面
図及び断面図、第６図は従来例を示す平面図である。 （１）…絶縁性金属基板、（２）…導体パターン、
（２′）…アース接地ライン、（３）…半導体素子、
（４）…接続体、（５）…ザグリ部。1 and 2 are plan and sectional views showing a hybrid integrated circuit of the present invention, FIGS. 3 to 5 are plan and sectional views showing another embodiment, and FIG. 6 is a conventional example. It is a top view. (1) ... Insulating metal substrate, (2) ... Conductor pattern,
(2 ') ... earth ground line, (3) ... semiconductor element,
(4) ... Connection body, (5) ... Counterbore part.
Claims (2)
基板上に形成された所望形状の導体パターンと、この導
体パターンに固着された複数の半導体素子とを備え、前
記導体パターンおよび前記半導体素子とを少なくとも要
素として所望の回路を達成する混成集積回路において、 前記絶縁性金属基板上には、グランドパッドが１つ設け
られ、このグランドパッドから延在されるグランドライ
ンとなる導体パターンは、この導体パターンと前記絶縁
性金属基板を電気的に接続する複数個の接続体を介し
て、前記絶縁性金属基板をグランドに固定し、前記グラ
ンドパッドから延在されるグランドラインとなる導体パ
ターンの配置領域以外に設けられるグランドラインとな
るべき導体パターンは、この導体パターンに設けられる
接続体を介して前記絶縁性金属基板と電気的に接続され
ることを特徴とした混成集積回路。1. An insulating metal substrate, a conductor pattern having a desired shape formed on the insulative metal substrate, and a plurality of semiconductor elements fixed to the conductor pattern. A hybrid integrated circuit that achieves a desired circuit by using the semiconductor element as at least an element, wherein one ground pad is provided on the insulating metal substrate, and a conductor pattern serving as a ground line extending from the ground pad Is a conductor that serves as a ground line extending from the ground pad by fixing the insulating metal substrate to the ground through a plurality of connecting bodies that electrically connect the conductor pattern and the insulating metal substrate. The conductor pattern to be the ground line provided in a region other than the pattern arrangement region is described above through the connection body provided in the conductor pattern. A hybrid integrated circuit characterized by being electrically connected to an insulating metal substrate.
ドラインとなる導体パターンおよび前記グランドライン
となるべき導体パターンには、このパターンの下層の金
属表面が露出されるザグリ部が設けられ、このザグリ部
に前記接続体が電気的に接続されることで、前記絶縁性
金属基板およびグランドとなるべき導体パターンをグラ
ンドに固定する請求項１記載の混成集積回路。2. A conductor pattern extending from the ground pad to be a ground line and a conductor pattern to be the ground line are provided with a counterbore portion exposing a metal surface of a lower layer of the pattern. The hybrid integrated circuit according to claim 1, wherein the insulating metal substrate and the conductor pattern to be the ground are fixed to the ground by electrically connecting the connection body to the portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988096005U JPH0741161Y2 (en) | 1988-07-20 | 1988-07-20 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988096005U JPH0741161Y2 (en) | 1988-07-20 | 1988-07-20 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0217847U JPH0217847U (en) | 1990-02-06 |
| JPH0741161Y2 true JPH0741161Y2 (en) | 1995-09-20 |
Family
ID=31320794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988096005U Expired - Lifetime JPH0741161Y2 (en) | 1988-07-20 | 1988-07-20 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0741161Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2646988B2 (en) * | 1993-12-24 | 1997-08-27 | 日本電気株式会社 | Resin-sealed semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6372180A (en) * | 1986-09-12 | 1988-04-01 | ティーディーケイ株式会社 | Electronic component and manufacture of the same |
| JPS6359370U (en) * | 1986-10-06 | 1988-04-20 |
-
1988
- 1988-07-20 JP JP1988096005U patent/JPH0741161Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0217847U (en) | 1990-02-06 |
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