JPH07307308A - Film forming method and manufacture of semiconductor integrated circuit device using the same - Google Patents
Film forming method and manufacture of semiconductor integrated circuit device using the sameInfo
- Publication number
- JPH07307308A JPH07307308A JP9826894A JP9826894A JPH07307308A JP H07307308 A JPH07307308 A JP H07307308A JP 9826894 A JP9826894 A JP 9826894A JP 9826894 A JP9826894 A JP 9826894A JP H07307308 A JPH07307308 A JP H07307308A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- deposited
- silicon film
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体製造工程で行わ
れる成膜技術に関し、特に、半導体基板上に堆積する薄
膜のストレス低減に適用して有効な技術に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a film forming technique used in a semiconductor manufacturing process, and more particularly to a technique effectively applied to reduce stress of a thin film deposited on a semiconductor substrate.
【０００２】[0002]
【従来の技術】半導体集積回路装置の製造工程では、シ
リコン基板上の電極配線材料として多結晶シリコン膜が
広く使用されている。2. Description of the Related Art In a manufacturing process of a semiconductor integrated circuit device, a polycrystalline silicon film is widely used as an electrode wiring material on a silicon substrate.
【０００３】多結晶シリコン膜を半導体基板上に堆積す
るには、モノシラン（ＳｉＨ4)やジシラン（Ｓｉ2 Ｈ6)
などの反応ガスを用いたＣＶＤ法が利用されている。こ
のＣＶＤ法によって半導体基板上に堆積された直後の多
結晶シリコン膜は、通常、アモルファス状態になってお
り、その後、熱処理を施すことによって多結晶化され
る。To deposit a polycrystalline silicon film on a semiconductor substrate, monosilane (SiH 4 ) or disilane (Si 2 H 6 ) is used.
A CVD method using a reaction gas such as is used. The polycrystalline silicon film immediately after being deposited on the semiconductor substrate by this CVD method is usually in an amorphous state, and then heat-treated to be polycrystallized.
【０００４】[0004]
【発明が解決しようとする課題】上記多結晶シリコン膜
のように、成膜後の熱処理によって結晶化する薄膜は、
堆積時の膜厚が厚い程、結晶化時のグレインサイズが大
きくなる。A thin film that is crystallized by heat treatment after film formation, such as the above-mentioned polycrystalline silicon film, is
The thicker the deposited film, the larger the grain size during crystallization.
【０００５】ところが、膜のグレインサイズが大きくな
ると、それに比例して結晶化時の膜ストレスが大きくな
るため、膜ハガレが生じたり、膜中にヒロックやクラッ
クなどが発生したりする。また、膜ストレスが大きくな
ると下地へのダメージも大きくなり、例えばＭＩＳＦＥ
Ｔのゲート電極の膜ストレスが大きくなると、下地のゲ
ート酸化膜の欠陥密度が増大してしまう。However, as the grain size of the film increases, the film stress during crystallization increases in proportion to the increase in film size, resulting in film peeling and hillocks and cracks in the film. Further, when the film stress increases, the damage to the base also increases, and for example, MISFE
When the film stress of the T gate electrode increases, the defect density of the underlying gate oxide film increases.
【０００６】このような問題は、多結晶シリコン膜のみ
に生じるものではなく、成膜後の熱処理によって結晶化
する各種の薄膜、例えば高融点金属シリサイド膜などに
おいても同様に生じる。Such a problem does not occur only in the polycrystalline silicon film, but also in various thin films which are crystallized by heat treatment after the film formation, such as a refractory metal silicide film.
【０００７】本発明の目的は、基板上に堆積した薄膜が
結晶化する際のストレスを低減することのできる技術を
提供することにある。An object of the present invention is to provide a technique capable of reducing stress when a thin film deposited on a substrate is crystallized.
【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００９】[0009]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
次のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.
【００１０】本発明の成膜方法は、多結晶シリコン膜や
シリサイド膜のように成膜後の熱処理によって結晶化す
る膜を堆積する際、所望の膜厚を一度に堆積するのでは
なく、膜の堆積と熱処理とを交互に複数回繰り返しなが
ら所望の膜厚を得るようにするものである。According to the film forming method of the present invention, when a film such as a polycrystalline silicon film or a silicide film which is crystallized by heat treatment after film formation is deposited, a desired film thickness is not deposited all at once but The desired film thickness is obtained by alternately repeating the deposition and the heat treatment a plurality of times.
【００１１】[0011]
【作用】上記した手段によれば、所望の膜厚を一度に堆
積する場合に比べて結晶のグレインサイズが小さくなる
ので、結晶化時の膜ストレスを低減することができる。According to the above-mentioned means, the grain size of the crystal is smaller than in the case where a desired film thickness is deposited at one time, so that the film stress during crystallization can be reduced.
【００１２】[0012]
【実施例】以下、本発明の実施例を図面に基づいて詳細
に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【００１３】（実施例１）本実施例は、半導体基板上に
多結晶シリコン膜を堆積し、これをパターニングしてＭ
ＩＳＦＥＴのゲート電極を形成する工程に適用したもの
である。(Embodiment 1) In this embodiment, a polycrystalline silicon film is deposited on a semiconductor substrate and patterned to form M
This is applied to the step of forming the gate electrode of the ISFET.
【００１４】まず、図１に示すように、例えばｐ型の単
結晶シリコンからなる半導体基板１の主面にフィールド
絶縁膜２およびゲート絶縁膜３を形成した後、モノシラ
ンまたはジシランを反応ガスに用いたＣＶＤ法により、
全面にゲート電極材料である多結晶シリコン膜４を堆積
する。First, as shown in FIG. 1, a field insulating film 2 and a gate insulating film 3 are formed on the main surface of a semiconductor substrate 1 made of, for example, p-type single crystal silicon, and then monosilane or disilane is used as a reaction gas. The CVD method
A polycrystalline silicon film 4 as a gate electrode material is deposited on the entire surface.
【００１５】このとき、本実施例では、所望する膜厚を
一度に堆積し、その後熱処理を行うのではなく、まず、
多結晶シリコン膜（４ａ）を薄く堆積した後、熱処理を
行い、さらに多結晶シリコン膜（４ｂ）を薄く堆積した
後、熱処理を行うというように、多結晶シリコン膜４の
堆積を複数回に分け、薄い多結晶シリコン膜（４ａ〜４
ｄ）を堆積するごとに熱処理を行う。すなわち、所望す
る多結晶シリコン膜４の膜厚が例えば１５０〜１６０nm
である場合は、膜の堆積を４０〜５０nmずつ３〜４回に
分けて行い、各回ごとに熱処理を行うようにする。At this time, in this embodiment, instead of depositing a desired film thickness at once and then performing heat treatment, first,
The polycrystalline silicon film (4a) is thinly deposited, then heat-treated, and then the polycrystalline silicon film (4b) is thinly deposited and then heat-treated. , Thin polycrystalline silicon film (4a-4
A heat treatment is performed each time d) is deposited. That is, the desired thickness of the polycrystalline silicon film 4 is, for example, 150 to 160 nm.
In such a case, the film is deposited every 40 to 50 nm in 3 to 4 times, and the heat treatment is performed each time.
【００１６】その後、図２に示すように、フォトレジス
ト５をマスクにして上記多結晶シリコン膜４をエッチン
グすることにより、ゲート電極６を形成する。After that, as shown in FIG. 2, the polycrystalline silicon film 4 is etched by using the photoresist 5 as a mask to form a gate electrode 6.
【００１７】図３は、不純物をドープした多結晶シリコ
ン膜（ドープトポリシリコン）の膜厚と膜ストレス変化
量との関係を示すグラフである。FIG. 3 is a graph showing the relationship between the film thickness of a polycrystalline silicon film doped with impurities (doped polysilicon) and the amount of change in film stress.
【００１８】図示のように、多結晶シリコン膜の膜スト
レスは、その膜厚が約５０nm以下になると著しく低下す
ることが判る。このことから、多結晶シリコン膜を堆積
する場合は、１回の堆積工程の膜厚を４０〜５０nm以下
にすることが望ましい。As shown in the figure, the film stress of the polycrystalline silicon film is remarkably reduced when the film thickness becomes about 50 nm or less. From this, when depositing a polycrystalline silicon film, it is desirable that the film thickness in one deposition step be 40 to 50 nm or less.
【００１９】（実施例２）本実施例は、ＭＩＳＦＥＴの
ゲート電極を多結晶シリコン膜とタングステンシリサイ
ド膜の積層膜（ポリサイド膜）で構成する場合である。(Embodiment 2) In this embodiment, the gate electrode of the MISFET is composed of a laminated film (polycide film) of a polycrystalline silicon film and a tungsten silicide film.
【００２０】まず、図４に示すように、フィールド絶縁
膜２およびゲート絶縁膜３を形成し、ＣＶＤ法により多
結晶シリコン膜４を堆積し、次いでこの多結晶シリコン
膜４の上にタングステンシリサイド膜７を堆積する。そ
の後、図５に示すように、フォトレジスト８をマスクに
してタングステンシリサイド膜７および多結晶シリコン
膜４を順次エッチングすることにより、ポリサイド構造
のゲート電極９を形成する。First, as shown in FIG. 4, a field insulating film 2 and a gate insulating film 3 are formed, a polycrystalline silicon film 4 is deposited by a CVD method, and then a tungsten silicide film is formed on the polycrystalline silicon film 4. 7 is deposited. After that, as shown in FIG. 5, the tungsten silicide film 7 and the polycrystalline silicon film 4 are sequentially etched using the photoresist 8 as a mask to form a gate electrode 9 having a polycide structure.
【００２１】この場合も、多結晶シリコン膜４およびタ
ングステンシリサイド膜７の堆積をそれぞれ複数回に分
けて行い、各回ごとに熱処理を行うようにすることで多
結晶シリコン膜４およびタングステンシリサイド膜７の
膜ストレスを低減することができる。Also in this case, the polycrystalline silicon film 4 and the tungsten silicide film 7 are deposited in a plurality of times, and the heat treatment is performed each time, so that the polycrystalline silicon film 4 and the tungsten silicide film 7 are deposited. Membrane stress can be reduced.
【００２２】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることはいうまでもない。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.
【００２３】本発明は、多結晶シリコン膜やシリサイド
膜に限らず、成膜後の熱処理によって結晶化する各種の
膜を堆積する場合に広く適用することができる。The present invention is not limited to the polycrystalline silicon film and the silicide film, but can be widely applied to the case of depositing various films which are crystallized by the heat treatment after the film formation.
【００２４】[0024]
【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下の通りである。The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.
【００２５】本発明の成膜方法およびそれを用いた半導
体集積回路装置の製造方法によれば、基板上に堆積した
薄膜が結晶化する際のストレスを低減することができる
ので、膜ハガレ、ヒロック、クラックなどの発生を防止
し、かつ下地へのダメージを低減することができ、これ
により、半導体集積回路装置の製造歩留り、信頼性を向
上させることができる。According to the film forming method of the present invention and the method of manufacturing a semiconductor integrated circuit device using the film forming method, it is possible to reduce the stress when the thin film deposited on the substrate is crystallized. It is possible to prevent the occurrence of cracks, etc., and reduce damage to the underlying layer, thereby improving the manufacturing yield and reliability of the semiconductor integrated circuit device.
【図１】本発明の一実施例である半導体集積回路装置の
製造方法を示す半導体基板の要部断面図である。FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
【図２】本発明の一実施例である半導体集積回路装置の
製造方法を示す半導体基板の要部断面図である。FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
【図３】多結晶シリコン膜の膜厚と膜ストレス変化量と
の関係を示すグラフである。FIG. 3 is a graph showing a relationship between a film thickness of a polycrystalline silicon film and a film stress change amount.
【図４】本発明の他の実施例である半導体集積回路装置
の製造方法を示す半導体基板の要部断面図である。FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.
【図５】本発明の他の実施例である半導体集積回路装置
の製造方法を示す半導体基板の要部断面図である。FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.
１ 半導体基板 ２ フィールド絶縁膜 ３ ゲート絶縁膜 ４ 多結晶シリコン膜 ４ａ〜４ｄ 多結晶シリコン膜 ５ フォトレジスト ６ ゲート電極 ７ タングステンシリサイド膜 ８ フォトレジスト ９ ゲート電極 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Field insulating film 3 Gate insulating film 4 Polycrystalline silicon film 4a-4d Polycrystalline silicon film 5 Photoresist 6 Gate electrode 7 Tungsten silicide film 8 Photoresist 9 Gate electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/3205 29/78 Ｈ０１Ｌ 29/78 ３０１ Ｇ (72)発明者 鈴木 範夫 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所半導体事業部内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Reference number within the agency FI Technical indication part H01L 21/3205 29/78 H01L 29/78 301 G (72) Inventor Norio Suzuki Suzuki, Kodaira, Tokyo 5-20-1, Mizumotocho Incorporated company Hitachi Ltd. Semiconductor Division
Claims (4)
を基板上に堆積する際、膜の堆積と熱処理とを交互に複
数回繰り返しながら所望の膜厚を得ることを特徴とする
成膜方法。1. A method for forming a film, wherein when a thin film which is crystallized by heat treatment after deposition is deposited on a substrate, a desired film thickness is obtained by alternately repeating film deposition and heat treatment a plurality of times.
点金属シリサイド膜であることを特徴とする請求項１記
載の成膜方法。2. The film forming method according to claim 1, wherein the thin film is a polycrystalline silicon film or a refractory metal silicide film.
高融点金属シリサイド膜もしくはそれらの積層膜からな
る薄膜を堆積する際、膜の堆積と熱処理とを交互に複数
回繰り返しながら所望の膜厚を得、次いで、前記薄膜を
パターニングして電極または配線を形成することを特徴
とする請求項１または２記載の成膜方法を用いた半導体
集積回路装置の製造方法。3. When depositing a thin film of a polycrystalline silicon film or a refractory metal silicide film or a laminated film thereof on a semiconductor substrate, a desired film thickness is obtained by alternately repeating film deposition and heat treatment a plurality of times. 3. A method for manufacturing a semiconductor integrated circuit device using the film forming method according to claim 1, wherein the thin film is then patterned to form electrodes or wiring.
下とすることを特徴とする請求項３記載の半導体集積回
路装置の製造方法。4. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein the film thickness in one deposition step is set to 40 to 50 nm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09826894A JP3357456B2 (en) | 1994-05-12 | 1994-05-12 | Method of manufacturing semiconductor integrated circuit device and semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09826894A JP3357456B2 (en) | 1994-05-12 | 1994-05-12 | Method of manufacturing semiconductor integrated circuit device and semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07307308A true JPH07307308A (en) | 1995-11-21 |
| JP3357456B2 JP3357456B2 (en) | 2002-12-16 |
Family
ID=14215201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP09826894A Expired - Fee Related JP3357456B2 (en) | 1994-05-12 | 1994-05-12 | Method of manufacturing semiconductor integrated circuit device and semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3357456B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006524439A (en) * | 2003-04-24 | 2006-10-26 | エーエスエム アメリカ インコーポレイテッド | Method for depositing polycrystalline film having highly functional particle structure |
| CN109987568A (en) * | 2017-12-29 | 2019-07-09 | 中芯国际集成电路制造(上海)有限公司 | The forming method of membrane structure, acoustic-electrical transducer part and forming method thereof |
-
1994
- 1994-05-12 JP JP09826894A patent/JP3357456B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006524439A (en) * | 2003-04-24 | 2006-10-26 | エーエスエム アメリカ インコーポレイテッド | Method for depositing polycrystalline film having highly functional particle structure |
| CN109987568A (en) * | 2017-12-29 | 2019-07-09 | 中芯国际集成电路制造(上海)有限公司 | The forming method of membrane structure, acoustic-electrical transducer part and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3357456B2 (en) | 2002-12-16 |
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