JPH0730258A - Multilayer wiring board with built-in capacitor, and its manufacture - Google Patents
Multilayer wiring board with built-in capacitor, and its manufactureInfo
- Publication number
- JPH0730258A JPH0730258A JP5196788A JP19678893A JPH0730258A JP H0730258 A JPH0730258 A JP H0730258A JP 5196788 A JP5196788 A JP 5196788A JP 19678893 A JP19678893 A JP 19678893A JP H0730258 A JPH0730258 A JP H0730258A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- electrodes
- built
- wiring board
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、キャパシタ内蔵配線基
板とその製造方法に関し、特に複数のＩＣを搭載するマ
ルチチップモジュール基板に好適に利用され得る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board with a built-in capacitor and a method for manufacturing the wiring board, and particularly, it can be suitably used for a multi-chip module board on which a plurality of ICs are mounted.
【０００２】[0002]
【従来の技術】複数のＩＣを搭載するいわゆるマルチチ
ップモジュールにおいては、クロック周波数の上昇、消
費電力の増加傾向が著しい。これにともない電源ノイズ
も上昇する。従って、これを抑制するには、まず電源イ
ンピーダンスを下げることが必須であり、デカップリン
グキャパシタを装着する必要がある。2. Description of the Related Art In a so-called multi-chip module having a plurality of ICs mounted thereon, there is a marked increase in clock frequency and power consumption. Along with this, power supply noise also rises. Therefore, in order to suppress this, it is essential to first lower the power source impedance, and it is necessary to mount a decoupling capacitor.
【０００３】従来、絶縁基板の部品（通常ＩＣ）搭載面
に、デカップリングキャパシタとしてのチップコンデン
サを実装する手法がとられている。また、絶縁基板をセ
ラミックグリーンシートから作製し、そのグリーンシー
トの一部を誘電体層として、絶縁基板にコンデンサーを
内蔵することも提案されている。すなわち、絶縁基板表
面にチップコンデンサーを搭載するものに比べて、ＩＣ
を搭載する絶縁基板にあっては、ＩＣとコンデンサー間
の配線長が短くて済むので、低インダクタンスとなり、
電源ノイズ、グランドノイズなどの低減効果が大きくな
るからである。そして、その場合の、チップコンデンサ
用セラミック誘電体材料としてはチタン酸バリウムが、
絶縁基板用セラミック絶縁材料としてはアルミナがそれ
ぞれよく知られている。Conventionally, a method of mounting a chip capacitor as a decoupling capacitor on a component (usually IC) mounting surface of an insulating substrate has been adopted. It has also been proposed that the insulating substrate is made of a ceramic green sheet, and a capacitor is built in the insulating substrate by using a part of the green sheet as a dielectric layer. In other words, compared to the one that mounts the chip capacitor on the surface of the insulating substrate, the IC
In the case of the insulating board that mounts the, because the wiring length between the IC and the capacitor is short, the inductance is low,
This is because the effect of reducing power supply noise, ground noise, etc. becomes greater. And, in that case, barium titanate is used as the ceramic dielectric material for the chip capacitor.
Alumina is well known as a ceramic insulating material for insulating substrates.
【０００４】[0004]
【発明が解決しようとする課題】しかし、絶縁基板表面
にチップコンデンサーを搭載するものは、チップの大き
さが１〜２ｍｍ四方もあることから、装置全体の占める
面積が大きくなり、装置の高密度化、小型化を達成する
ことができない。However, in the case where the chip capacitor is mounted on the surface of the insulating substrate, since the size of the chip is 1 to 2 mm square, the area occupied by the entire device is large, and the device has a high density. Downsizing and downsizing cannot be achieved.
【０００５】また、絶縁基板にコンデンサーを内蔵する
場合、一般的なセラミック誘電体材料、例えばチタン酸
バリウムなどは、高誘電率でありコンデンサーとしての
機能はよいが、熱膨張係数が８×１０-6／℃以上と半導
体シリコン（ＩＣ）よりかなり大きく、強度も６５０ｋ
ｇ／ｃｍ2程度で決して高くないため、ＩＣを搭載する
絶縁基板との兼用には適さない。When a capacitor is built in an insulating substrate, a general ceramic dielectric material such as barium titanate has a high dielectric constant and functions well as a capacitor, but has a thermal expansion coefficient of 8 × 10 −. Greater than 6 / ° C, much larger than semiconductor silicon (IC), and has strength of 650k
Since it is not so high as g / cm 2 , it is not suitable as an insulating substrate on which an IC is mounted.
【０００６】アルミナは、高強度であるが、熱膨張係数
が６〜８×１０-6／℃と大きいうえ、誘電率が８．５〜
１０と低いため、誘電体層厚が５０μｍのとき単位面積
あたりの静電容量が０．２ｎＦ／ｃｍ2程度と小さい。
従って、これを誘電体層として用いても通常の面積であ
れば小さい容量のコンデンサーしか得られず、結局電源
インピーダンスＺ＝（インダクタンスＬ／静電容量Ｃ）
1/2の関係でインピーダンスが高くなる。かといって、
現在要求されているＩＣ１個当たりの静電容量はおよそ
１００ｎＦであるが、これを充足するには、５００ｃｍ
2もの大面積が必要となる。Alumina has high strength, but has a large coefficient of thermal expansion of 6 to 8 × 10 -6 / ° C. and a dielectric constant of 8.5 to 8.5.
Since it is as low as 10, the capacitance per unit area is as small as about 0.2 nF / cm 2 when the dielectric layer thickness is 50 μm.
Therefore, even if this is used as a dielectric layer, only a capacitor having a small capacitance can be obtained in a normal area, and eventually the power source impedance Z = (inductance L / electrostatic capacitance C)
The impedance becomes high due to the 1/2 relationship. However,
The current required capacitance per IC is about 100 nF, but to satisfy this, 500 cm
Two large areas are required.
【０００７】一方、印刷及び焼成の工程を経て得られた
厚膜やスパッタリング工程を経て得られた薄膜などのよ
うな膜状のものを誘電体層とすることにより、静電容量
を高め、その結果、電源インピーダンスを下げることも
考えられるが、グリーンシートから得られた誘電体層に
比べてその厚さが薄いので、誘電体層中のわずかのピン
ホールによって電極間ショートが発生する。従って、大
きな静電容量を確保しようとするほどに製品の歩留まり
が低下する。On the other hand, by using a film-like material such as a thick film obtained through the printing and firing steps or a thin film obtained through the sputtering step as a dielectric layer, the capacitance is increased, As a result, it is possible to reduce the power source impedance, but since the thickness is smaller than the dielectric layer obtained from the green sheet, a short pinhole in the dielectric layer causes a short circuit between electrodes. Therefore, the yield of products decreases as the larger electrostatic capacity is required.
【０００８】よって、高密度化、熱膨張係数、強度及び
誘電率のすべてを満足し、しかも生産性に優れた構造は
従来知られていなかった。本発明の目的は、誘電率に依
存することなく、電源ノイズの抑制及び高密度化を達成
することができ、生産性に優れたキャパシタ内蔵配線基
板を提供することにある。Therefore, a structure satisfying all of high densification, thermal expansion coefficient, strength and permittivity and excellent in productivity has not been heretofore known. An object of the present invention is to provide a wiring board with a built-in capacitor that can suppress power supply noise and achieve high density without depending on the dielectric constant and has excellent productivity.
【０００９】[0009]
【課題を解決するための手段】その手段は、基板と、こ
の基板上に設けられた多層配線層と、多層配線層に内蔵
された薄膜、厚膜などによる膜状の誘電体層及びこれを
挟む電極からなるキャパシタとを備え、前記電極のうち
少なくとも一方の電極が、複数の小電極からなることを
特徴とするキャパシタ内蔵多層配線基板にある。このキ
ャパシタ内蔵多層配線基板において望ましいのは、膜状
の誘電体層が、薄膜又は高誘電率厚膜よりなるものであ
る。[Means for Solving the Problems] The means is a substrate, a multilayer wiring layer provided on the substrate, a film-like dielectric layer made of a thin film or a thick film built in the multilayer wiring layer, and A multilayer wiring board with a built-in capacitor, comprising a capacitor composed of electrodes sandwiched between the electrodes, and at least one of the electrodes being composed of a plurality of small electrodes. In this capacitor-embedded multilayer wiring board, it is desirable that the film-shaped dielectric layer be a thin film or a high dielectric constant thick film.
【００１０】薄膜の材質としては、例えばＳｉＯ2，Ｔ
ｉＯ2，Ｔａ2Ｏ5、Ｓｉ3Ｎ4等が挙げられる。そして、
これらを薄膜で形成するには、最初から酸化物の形態で
スパッタリングする方法、金属塩化物をＣＶＤ法にて蒸
着した後、酸化する方法、Ｓｉ，Ｔｉ，Ｔａ等の金属を
スパッタリングした後、陽極酸化又は窒化する方法など
が挙げられる。また、高誘電率厚膜とは、例えばチタン
酸バリウム粉末やＰＺＴ系粉末を主成分とするペースト
をスクリーン印刷し焼成して得られるようなものがあげ
られる。As the material of the thin film, for example, SiO 2 , T
Examples thereof include iO 2 , Ta 2 O 5 , and Si 3 N 4 . And
To form these in a thin film, a method of sputtering in the form of an oxide from the beginning, a method of depositing a metal chloride by a CVD method and then oxidizing, a method of sputtering a metal such as Si, Ti, Ta, and the like Examples thereof include a method of oxidizing or nitriding. Examples of the high dielectric constant thick film include those obtained by screen-printing and firing a paste containing barium titanate powder or PZT-based powder as a main component.
【００１１】同じく望ましいのは、複数の小電極のう
ち、対向する電極と短絡していないもの同士が相互に結
線されてキャパシタが形成されていることを特徴とす
る。本発明は、相互に結線された小電極群により形成さ
れるキャパシタを、同一誘電体層内に複数設ける（以
下、個々のキャパシタを分割キャパシタと称する。）場
合も適用可能である。すなわち、１平面内の分割キャパ
シタを、１電源（例えば＋５Ｖ）のみで使用する場合ば
かりでなく、２電源以上（＋５Ｖ，−５Ｖ・・・・）で領域
を分けて使用する場合も適用可能である。It is also desirable that among the plurality of small electrodes, those which are not short-circuited with the opposing electrodes are connected to each other to form a capacitor. The present invention is also applicable to a case where a plurality of capacitors formed by small electrode groups connected to each other are provided in the same dielectric layer (hereinafter, each capacitor is referred to as a divided capacitor). That is, it is applicable not only when the divided capacitors in one plane are used by only one power source (for example, + 5V), but also when divided by two power sources or more (+ 5V, -5V ...). is there.
【００１２】小電極の相互結線は、電極と同一面に設け
られてもよいし、小電極の上に絶縁膜が積層され、その
絶縁膜の上に設けられてもよい。後者の場合は、同一絶
縁膜の表面を相互結線と信号配線とで共有することがで
き、相互結線だけを目的として層数を増す必要がない点
で都合がよい。The mutual connection of the small electrodes may be provided on the same surface as the electrodes, or an insulating film may be laminated on the small electrodes and provided on the insulating film. The latter case is convenient in that the surface of the same insulating film can be shared by the mutual connection and the signal wiring, and it is not necessary to increase the number of layers only for the purpose of mutual connection.
【００１３】同じく上記目的達成の手段は、基板の上
に、直接又は絶縁膜を介して誘電体層及びこの誘電体層
を挟む電極を形成する方法において、少なくとも一方の
電極を複数の小電極にて形成し、各小電極と他方の電極
との間の短絡を検査した後、短絡していない小電極の２
つ以上を互いに結線することによってキャパシタを設け
ることを特徴とするキャパシタ内蔵多層配線基板の製造
方法にある。The means for achieving the above-mentioned object is also a method of forming a dielectric layer and electrodes sandwiching the dielectric layer directly or through an insulating film on a substrate, wherein at least one electrode is formed into a plurality of small electrodes. After checking the short circuit between each small electrode and the other electrode,
A method of manufacturing a multilayer wiring board with a built-in capacitor is characterized in that a capacitor is provided by connecting three or more wires to each other.
【００１４】[0014]
【作用】キャパシタが多層配線層に内蔵されているの
で、電子部品搭載面をキャパシタが占有することはな
い。そして、誘電体層が膜状のものであるから、グリー
ンシートから形成されるアルミナの誘電体層に比べて薄
いので、静電容量が高く、しかも多層配線基板全体の体
積にさほど影響を及ぼすことがない。Since the capacitor is built in the multilayer wiring layer, the capacitor does not occupy the electronic component mounting surface. Since the dielectric layer is a film, it is thinner than the alumina dielectric layer formed from the green sheet, so that the capacitance is high and the volume of the entire multilayer wiring board is significantly affected. There is no.
【００１５】膜状の誘電体層が薄膜よりなるとき、その
材質が高誘電率のものでなくても、薄膜すなわち０．１
μ〜数μ程度の膜厚のものであるから、静電容量が高く
なり、その結果、電源インピーダンスが低くなる。一
方、膜状の誘電体層が高誘電率厚膜よりなるときには、
膜厚は薄膜に比べて厚くなるものの、誘電率が大きいの
で、同様に静電容量が高く、電源インピーダンスが低く
なる。When the film-like dielectric layer is made of a thin film, the thin film, that is, 0.1
Since the film thickness is about μ to several μ, the electrostatic capacity becomes high, and as a result, the power source impedance becomes low. On the other hand, when the film-shaped dielectric layer is a high dielectric constant thick film,
Although the film thickness is thicker than that of the thin film, since the dielectric constant is large, similarly, the electrostatic capacity is high and the power source impedance is low.
【００１６】また、各小電極と対向電極との間の短絡を
検査した後、短絡していない小電極のみを互いに結線す
ることによって上下電極及び誘電体層よりなるキャパシ
タを設けるので、キャパシタ内蔵多層配線基板として完
成した後に、キャパシタの短絡が原因で不良品となるこ
とがない。従って、キャパシタを形成する前の工程が無
駄にならない。Further, after inspecting a short circuit between each small electrode and the counter electrode, only the small electrodes which are not short-circuited are connected to each other to provide a capacitor composed of upper and lower electrodes and a dielectric layer. After it is completed as a wiring board, it does not become a defective product due to a short circuit of the capacitor. Therefore, the process before forming the capacitor is not wasted.
【００１７】すなわち、マルチチップモジュール等のよ
うに大きな静電容量を必要とする多層配線基板では、そ
の基板の面積にほぼ等しい電極面積の大きなキャパシタ
を設けなければならない。従って、電極間短絡の発生率
は極めて高く、通常の製造方法では製造歩留まりが著し
く低い。これに対して、本発明では、短絡した小電極を
除いて正常な小電極のみを相互に接続したものを一つの
電極として用いるので、キャパシタ部の電極間短絡によ
る不良発生率をほぼ皆無とすることができるのである。That is, in a multi-layer wiring board which requires a large capacitance such as a multi-chip module, it is necessary to provide a capacitor having a large electrode area which is almost equal to the area of the board. Therefore, the occurrence rate of the short circuit between the electrodes is extremely high, and the manufacturing yield is extremely low in the ordinary manufacturing method. On the other hand, in the present invention, since only normal small electrodes are connected to each other excluding short-circuited small electrodes as one electrode, there is almost no defect occurrence rate due to inter-electrode short circuit of the capacitor part. It is possible.
【００１８】尚、上記手段において、誘電体層は基板に
比べて薄いためＩＣ等の電子部品を搭載する支持体とし
ての機能は、基板が果たす。従って、誘電体層となる薄
膜や高誘電率厚膜に、ＩＣとの熱膨張係数の整合性及び
機械的強度はあまり必要とされない。In the above means, since the dielectric layer is thinner than the substrate, the substrate functions as a support for mounting electronic parts such as ICs. Therefore, the thin film or the high-dielectric-constant thick film that becomes the dielectric layer is not required to have much matching coefficient of thermal expansion with the IC and mechanical strength.
【００１９】[0019]
【実施例】−好適な実施例− ［キャパシタ内蔵多層配線基板の構造］本発明キャパシ
タ内蔵多層配線基板の実施例を図面を用いて説明する。
図１は、キャパシタ内蔵多層配線基板１の厚み方向断面
図である。Examples-Preferred Examples- [Structure of Multilayer Wiring Board with Built-in Capacitor] An example of the multilayer wiring board with built-in capacitor of the present invention will be described with reference to the drawings.
FIG. 1 is a sectional view in the thickness direction of a multilayer wiring substrate 1 with a built-in capacitor.
【００２０】キャパシタ内蔵多層配線基板１は、アルミ
ナセラミック基板２上に複数の配線層が積層されて多層
配線層３を構成している多層配線基板であり、セラミッ
ク基板２は、本例ではそれ自体が内部配線を有する多層
配線基板であるが、内部配線を有しない単板であっても
よい。The multi-layer wiring board 1 with a built-in capacitor is a multi-layer wiring board in which a plurality of wiring layers are laminated on an alumina ceramic substrate 2 to form a multi-layer wiring layer 3, and the ceramic substrate 2 itself in this example. Is a multilayer wiring board having internal wiring, but it may be a single plate having no internal wiring.
【００２１】多層配線層３は、セラミック基板２のすぐ
上に存在するキャパシタ部４及びさらにその上の信号配
線部５に分けられる。キャパシタ部４は、セラミック基
板２に近い側より、Ｃｒ及びＣｕの２層よりなる面積８
１ｃｍ2の下側電極４１、厚さ１μｍ，面積１００ｃｍ2
のＴａ2Ｏ5薄膜よりなる誘電体層４２及び下側電極４１
と同質で１個当たりの面積１０ｃｍ2の８個の小電極４
３ａ・・・４３ｈよりなる上側電極４３にて構成されて
いる。信号配線部５は、ポリイミド等の有機高分子の絶
縁膜５１とＣｒ及びＣｕの２層よりなる導体膜５２とが
交互に積層されてなる。導体膜５２は、その大部分が信
号配線であり、絶縁膜５１の所々に設けられた導電ビア
５３にて三次元的に層間接続している。但し、キャパシ
タ部４のすぐ上の絶縁膜５１には、各々の小電極につな
がる導電ビア４４が設けられ、その絶縁膜５１上の導体
膜４５にて結線されている。従って、信号配線部５のう
ち、キャパシタ部４に最も近い絶縁膜５１上には、信号
配線の他に小電極を結線するための接続配線（導体膜４
５）を有する。The multi-layered wiring layer 3 is divided into a capacitor portion 4 existing immediately above the ceramic substrate 2 and a signal wiring portion 5 thereon. The capacitor portion 4 has an area 8 composed of two layers of Cr and Cu from the side closer to the ceramic substrate 2.
1 cm 2 lower electrode 41, thickness 1 μm, area 100 cm 2
Dielectric layer 42 and lower electrode 41 of Ta 2 O 5 thin film
Eight small electrodes 4 of the same quality as each and having an area of 10 cm 2
It is comprised by the upper electrode 43 which consists of 3a ... 43h. The signal wiring portion 5 is formed by alternately stacking an insulating film 51 of an organic polymer such as polyimide and a conductor film 52 composed of two layers of Cr and Cu. Most of the conductor film 52 is a signal wiring, and three-dimensional interlayer connection is made by conductive vias 53 provided in various places of the insulating film 51. However, a conductive via 44 connected to each small electrode is provided in the insulating film 51 immediately above the capacitor unit 4, and is connected by a conductor film 45 on the insulating film 51. Therefore, in the signal wiring portion 5, on the insulating film 51 closest to the capacitor portion 4, a connection wiring (conductor film 4) for connecting small electrodes in addition to the signal wiring.
5).
【００２２】［キャパシタ内蔵多層配線基板の製造方
法］このようなキャパシタ内蔵多層配線基板の製造方法
を説明する。先ず、アルミナ等のセラミックスを主成分
とする複数枚のグリーンシートに各配線等を層間接続す
る導電ビアを打ち抜き加工し、このビアに金属ペースト
を充填する。導電ビアが形成されたグリーンシートの表
面に、タングステンＷもしくはモリブデンＭｏ等の金属
ペーストを所定パターンにスクリーン印刷して、信号配
線、電源配線、接地配線等の各種配線パターン及び端子
（図示省略）を形成する。そして、これらグリーンシー
トを積層し、熱圧着した後、１５００度前後の高温で焼
成することによって、セラミック基板２を形成した。[Manufacturing Method of Multilayer Wiring Board with Built-in Capacitor] A manufacturing method of such a multilayer wiring board with built-in capacitor will be described. First, a plurality of green sheets containing ceramics such as alumina as a main component are punched to form conductive vias for interconnecting wirings, and the vias are filled with metal paste. A metal paste such as tungsten W or molybdenum Mo is screen-printed in a predetermined pattern on the surface of the green sheet on which the conductive vias are formed, and various wiring patterns such as signal wiring, power wiring, and ground wiring and terminals (not shown) are formed. Form. Then, these green sheets were laminated, thermocompression-bonded, and then fired at a high temperature of around 1500 ° C. to form the ceramic substrate 2.
【００２３】次に、セラミック基板２の主面を表面粗度
Ｒａ０．０５μｍ以下となるまで研磨し、その面にＣｒ
０．０５μｍ及びＣｕ０．５μｍを順にスパッタリング
した後、フォトレジストを塗布する。次いで、下側電極
パターンが形成されたフォトマスクをその上方に設置
し、露光し、下側電極パターンとなる部分のフォトレジ
ストを現像液にて除去する。更に、フォトレジストが除
去された部分に５μｍ程度のＣｕ鍍金を施した後、フォ
トレジストを溶剤にて除去し、不要部分（Ｃｕ鍍金され
ていない部分）のＣｕ及びＣｒをエッチング液にて除去
することにより下側電極４１を形成する。その上に、Ｔ
ａ2Ｏ5薄膜の誘電体層をスパッタリングにて形成する。
そして、セラミック基板２中の内部配線と多層配線層３
中の信号配線とを接続する導電ビアをフォトリソグラフ
ィー工程にて設ける。続いてＣｒを厚さ０．０５μｍ、
続いてＣｕを厚さ０．５μｍとなるようにスパッタリン
グした後、下側電極パターンに代えて上側電極パターン
とする以外は下側電極の場合と同様のフォトリソグラフ
ィー工程にて小電極４３ａ・・・４３ｈを形成する。こ
れにてキャパシタ部４を設けた。Next, the main surface of the ceramic substrate 2 is polished until the surface roughness Ra becomes 0.05 μm or less, and the surface thereof is Cr.
After sputtering 0.05 μm and Cu 0.5 μm in this order, a photoresist is applied. Next, a photomask on which the lower electrode pattern is formed is placed above it, exposed to light, and the photoresist in the portion to be the lower electrode pattern is removed with a developing solution. Further, after Cu plating of about 5 μm is applied to the portion where the photoresist is removed, the photoresist is removed with a solvent, and Cu and Cr in an unnecessary portion (a portion not Cu plated) are removed with an etching solution. Thus, the lower electrode 41 is formed. On top of that, T
a dielectric layer of a 2 O 5 thin film is formed by sputtering.
Then, the internal wiring in the ceramic substrate 2 and the multilayer wiring layer 3
Conductive vias that connect to the signal wirings therein are provided by a photolithography process. Then, Cr is 0.05 μm thick,
Subsequently, Cu is sputtered to have a thickness of 0.5 μm, and then the small electrode 43a is subjected to the same photolithography process as that of the lower electrode except that the upper electrode pattern is used instead of the lower electrode pattern. 43h is formed. Thus, the capacitor section 4 is provided.
【００２４】ここで次工程に移る前に、下側電極４１に
接続する端子に抵抗計のプローブの一つを固定し、他の
プローブを各々の小電極４３ａ・・・４３ｈに順に接触
させていき、電極間短絡の有無を検査した。短絡してい
た小電極は、１個（符号４３ｇで示す）であった。Before proceeding to the next step, one of the probes of the resistance meter is fixed to the terminal connected to the lower electrode 41, and the other probes are brought into contact with the respective small electrodes 43a ... 43h in order. Then, the presence or absence of a short circuit between the electrodes was inspected. The number of small electrodes that were short-circuited was one (indicated by 43g).
【００２５】次にポリイミドを主成分とし感光性乳剤を
も含有する感光性絶縁ペーストを塗布する。所定パター
ンを有するフォトマスクを通じて露光し、導電ビア４
４，５３となる部分の感光性絶縁ペーストを現像液にて
除去する。そして、３５０℃程度の温度で硬化し、絶縁
膜５１を形成した。絶縁膜５１の上に上側電極パターン
に代えて信号配線パターンとする以外は、上側電極４３
と同様の操作を行うことによって、信号配線を形成し
た。これにて配線層を設けた。このように絶縁膜５１の
形成工程と信号配線のための導体膜の形成工程を繰り返
すことで、信号配線部５を完成した。Next, a photosensitive insulating paste containing polyimide as a main component and also containing a photosensitive emulsion is applied. The conductive via 4 is exposed through a photomask having a predetermined pattern.
The photosensitive insulating paste in the portions to be 4, 53 is removed with a developing solution. Then, it was cured at a temperature of about 350 ° C. to form the insulating film 51. The upper electrode 43 is formed on the insulating film 51 except that a signal wiring pattern is used instead of the upper electrode pattern.
Signal wiring was formed by performing the same operation as. This provided the wiring layer. In this way, the signal wiring portion 5 is completed by repeating the step of forming the insulating film 51 and the step of forming the conductor film for the signal wiring.
【００２６】尚、キャパシタ部４に最も近い絶縁膜５１
上には、信号配線のほかに小電極を相互に接続する導体
膜４５も形成した。この導体膜４５形成にあたっては、
全ての小電極を接続するフォトマスクを用いて形成した
後、図２に示すように、上記検査工程において、下側電
極４１と短絡していた小電極４３ｇにつながる接続配線
４５を全て削り取るようにした。但し、短絡した小電極
４３ｇを他から切り離す手段は、これに限らず、レーザ
ーで切除しても良いし、Ｃｕ鍍金前に小電極４３ｇの周
囲を樹脂レジストで覆っておき、Ｃｕ鍍金後にその樹脂
レジストを除去する方法でも良い。これにてキャパシタ
内蔵多層配線基板１が完成した。The insulating film 51 closest to the capacitor section 4 is provided.
In addition to the signal wiring, the conductor film 45 for connecting the small electrodes to each other was also formed on the upper surface. When forming the conductor film 45,
After forming by using a photomask for connecting all the small electrodes, as shown in FIG. 2, in the inspection step, all the connection wirings 45 connected to the small electrodes 43g short-circuited with the lower electrode 41 are scraped off. did. However, the means for separating the short-circuited small electrode 43g from the other is not limited to this, and may be cut by laser, or the periphery of the small electrode 43g may be covered with a resin resist before the Cu plating and the resin after the Cu plating. A method of removing the resist may be used. Thus, the multilayer wiring board 1 with a built-in capacitor was completed.
【００２７】［評価］上記キャパシタ内蔵多層配線基板
１につき、静電容量を測定したところ、１．４μＦであ
った。[Evaluation] The capacitance of the multilayer wiring substrate 1 with a built-in capacitor was measured and found to be 1.4 μF.
【００２８】−その他の実施例− 上記の実施例では、基板材質としてアルミナを用いた
が、これに限らず窒化アルミニウム、ガラスセラミッ
ク、ムライト等のセラミックのほか、シリコンのような
半導体あるいはアルミニウムのような金属であっても良
い。絶縁膜は、ポリイミドに代えてベンゾシクロブテ
ン、ＳｉＯ2等の薄膜でも良い。-Other Examples-In the above-mentioned examples, alumina was used as the substrate material. However, the substrate material is not limited to this, and aluminum nitride, glass ceramics, mullite and other ceramics, as well as semiconductors such as silicon or aluminum may be used. It may be any metal. The insulating film may be a thin film of benzocyclobutene, SiO 2 or the like instead of polyimide.
【００２９】そして、誘電体層を薄膜に代えて高誘電率
厚膜で形成する場合は、電極材質としてはＡｇ／Ｐｄ合
金、Ｃｕ、Ａｕ等の低抵抗金属が適合する。高誘電率厚
膜は、印刷後に電極とともに焼成されるが、高誘電率厚
膜の焼成温度と低抵抗金属のそれとがほぼ一致している
からである。また、上記実施例では、キャパシタを１層
しか設けていないが、複数層設けても良い。When the dielectric layer is formed of a high dielectric constant thick film instead of a thin film, a low resistance metal such as Ag / Pd alloy, Cu or Au is suitable as the electrode material. This is because the high dielectric constant thick film is baked together with the electrode after printing, and the baking temperature of the high dielectric constant thick film and that of the low resistance metal are substantially the same. Further, although the capacitor is provided in only one layer in the above embodiment, a plurality of layers may be provided.
【００３０】−比較例− 図３に比較のためのキャパシタ内蔵配線基板の断面図を
示す。本例の構造は、上側電極が、面積８１ｃｍ2の一
つの電極よりなり、そのためキャパシタ部４に最も近い
絶縁膜５１上に接続配線４５が設けられていない点で、
図１のキャパシタ内蔵配線基板と異なる。Comparative Example FIG. 3 shows a sectional view of a wiring board with a built-in capacitor for comparison. In the structure of this example, the upper electrode is composed of one electrode having an area of 81 cm 2 , and therefore, the connection wiring 45 is not provided on the insulating film 51 closest to the capacitor section 4.
This is different from the wiring board with a built-in capacitor shown in FIG.
【００３１】従って、これを製造する際、キャパシタ部
４の電極間短絡の検査工程で、短絡していることが判明
すれば、不良品として製造ラインから除かれるものであ
り、その結果、検査工程に至るまでの作業や部品が無駄
になる。Therefore, when manufacturing this, if it is found in the inspection process of the short circuit between the electrodes of the capacitor section 4 that it is short-circuited, it is removed from the production line as a defective product, and as a result, the inspection process. The work and parts leading up to are wasted.
【００３２】[0032]
【効果】キャパシタ部を多層配線基板の内部に一体的に
含めているので、電子部品搭載面を有効に利用すること
ができる。また、キャパシタ部を多層配線基板の内部に
一体的に含めているので、装置の小型化及び高密度化を
図ることができるほか、シリコンチップを搭載した場合
のチップとキャパシタ間の配線長が短くなり、インダク
タンスを低減することができる。しかもキャパシタの電
極間の短絡発生率にかかわらず、最終歩留まりを向上さ
せることができる。[Effect] Since the capacitor portion is integrally included inside the multilayer wiring board, the electronic component mounting surface can be effectively used. Further, since the capacitor part is integrally included in the multilayer wiring board, the device can be downsized and the density can be increased, and the wiring length between the chip and the capacitor when the silicon chip is mounted is short. Therefore, the inductance can be reduced. Moreover, the final yield can be improved regardless of the occurrence rate of the short circuit between the electrodes of the capacitor.
【図１】実施例のキャパシタ内蔵多層配線基板を示す断
面図である。FIG. 1 is a cross-sectional view showing a capacitor-embedded multilayer wiring board according to an embodiment.
【図２】小電極の結線の状況を説明するために図１の上
方から接続配線及び上側電極を透視した図である。FIG. 2 is a diagram in which a connection wiring and an upper electrode are seen through from above in FIG. 1 in order to explain a connection state of small electrodes.
【図３】比較例のキャパシタ内蔵多層配線基板を示す断
面図である。FIG. 3 is a cross-sectional view showing a multilayer wiring board with a built-in capacitor of a comparative example.
１ キャパシタ内蔵多層配線基板 ２ セラミッ
ク基板 ３ 多層配線層 ４ キャパシタ部 ４１
下側電極 ４２ 誘電体層 ４３ 上側電極 ４４，
５３ 導電ビア ４５ 導体膜（接続配線） ５ 信号配線部
５１ 絶縁膜 ５２ 導体膜（信号配線）1 Multilayer Wiring Board with Built-in Capacitor 2 Ceramic Substrate 3 Multilayer Wiring Layer 4 Capacitor Section 41
Lower electrode 42 dielectric layer 43 upper electrode 44,
53 conductive via 45 conductor film (connection wiring) 5 signal wiring section
51 insulating film 52 conductor film (signal wiring)
Claims (7)
線層と、多層配線層に内蔵された膜状の誘電体層及びこ
れを挟む電極からなるキャパシタとを備え、前記電極の
うち少なくとも一方の電極が、複数の小電極からなるこ
とを特徴とするキャパシタ内蔵多層配線基板。1. A substrate, a multilayer wiring layer provided on the substrate, and a capacitor including a film-shaped dielectric layer embedded in the multilayer wiring layer and electrodes sandwiching the dielectric layer, and at least one of the electrodes. A multilayer wiring board with a built-in capacitor, wherein one electrode is composed of a plurality of small electrodes.
膜よりなる請求項１に記載のキャパシタ内蔵多層配線基
板。2. The multilayer wiring board with a built-in capacitor according to claim 1, wherein the film-shaped dielectric layer is a thin film or a high dielectric constant thick film.
絡していないもの同士が相互に結線されてキャパシタが
形成されていることを特徴とする請求項１〜２に記載の
キャパシタ内蔵多層配線基板。3. The capacitor-embedded multilayer according to claim 1, wherein among the plurality of small electrodes, those which are not short-circuited with the opposing electrodes are connected to each other to form a capacitor. Wiring board.
れるキャパシタを、同一誘電体層内に複数設けることを
特徴とする請求項３に記載のキャパシタ内蔵多層配線基
板。4. The multilayer wiring board with a built-in capacitor according to claim 3, wherein a plurality of capacitors formed by a group of small electrodes connected to each other are provided in the same dielectric layer.
けてなることを特徴とする請求項３〜４に記載のキャパ
シタ内蔵多層配線基板。5. The multilayer wiring board with a built-in capacitor according to claim 3, wherein mutual connection of the small electrodes is provided on the same surface as the electrodes.
縁膜の上に小電極の相互結線及び信号配線を設けてなる
ことを特徴とする請求項３〜４に記載のキャパシタ内蔵
多層配線基板。6. The multilayer structure with a built-in capacitor according to claim 3, wherein an insulating film is laminated on the small electrode, and the interconnection of the small electrodes and the signal wiring are provided on the insulating film. Wiring board.
電体層及びこの誘電体層を挟む電極を形成する方法にお
いて、少なくとも一方の電極を複数の小電極にて形成
し、各小電極と他方の電極との間の短絡を検査した後、
短絡していない小電極の２つ以上を互いに結線すること
によってキャパシタを設けることを特徴とするキャパシ
タ内蔵多層配線基板の製造方法。7. A method of forming a dielectric layer and electrodes sandwiching the dielectric layer directly or via an insulating film on a substrate, wherein at least one electrode is formed by a plurality of small electrodes, and each small electrode is formed. After inspecting for a short circuit between the electrode and the other electrode,
A method of manufacturing a multilayer wiring board with a built-in capacitor, comprising: connecting two or more small electrodes that are not short-circuited to each other to provide a capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19678893A JP3154594B2 (en) | 1993-07-13 | 1993-07-13 | Multilayer wiring board with built-in capacitor and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19678893A JP3154594B2 (en) | 1993-07-13 | 1993-07-13 | Multilayer wiring board with built-in capacitor and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0730258A true JPH0730258A (en) | 1995-01-31 |
| JP3154594B2 JP3154594B2 (en) | 2001-04-09 |
Family
ID=16363659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19678893A Expired - Fee Related JP3154594B2 (en) | 1993-07-13 | 1993-07-13 | Multilayer wiring board with built-in capacitor and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3154594B2 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6274224B1 (en) | 1999-02-01 | 2001-08-14 | 3M Innovative Properties Company | Passive electrical article, circuit articles thereof, and circuit articles comprising a passive electrical article |
| JP2002174667A (en) * | 2000-09-11 | 2002-06-21 | Hoya Corp | Multilayerd wiring board, and method of manufacturing the same |
| US6577492B2 (en) | 2001-07-10 | 2003-06-10 | 3M Innovative Properties Company | Capacitor having epoxy dielectric layer cured with aminophenylfluorenes |
| JP2005012107A (en) * | 2003-06-20 | 2005-01-13 | Ngk Spark Plug Co Ltd | Intermediate substrate with built-in capacitor |
| JP2007214437A (en) * | 2006-02-10 | 2007-08-23 | Dainippon Printing Co Ltd | Wiring board incorporated with passive element, and manufacturing method thereof |
| JP2010512667A (en) * | 2006-12-13 | 2010-04-22 | インテル コーポレイション | Small electronic device with bridge interconnection to upper conductive layer of passive buried structure and method of making the same |
| JP2010530644A (en) * | 2007-06-19 | 2010-09-09 | イー・アイ・デュポン・ドウ・ヌムール・アンド・カンパニー | Method for integrating thin film capacitors into the build-up layer of printed wiring boards |
| US7875808B2 (en) | 2005-09-19 | 2011-01-25 | Industrial Technology Research Institute | Embedded capacitor device having a common coupling area |
| WO2011086795A1 (en) * | 2010-01-15 | 2011-07-21 | 三洋電機株式会社 | Capacitor element and substrate with built-in capacitor |
| EP3346809A4 (en) * | 2016-03-04 | 2018-11-21 | Alps Electric Co., Ltd. | Electronic circuit module and method for testing electronic circuit module |
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1993
- 1993-07-13 JP JP19678893A patent/JP3154594B2/en not_active Expired - Fee Related
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6638378B2 (en) | 1999-02-01 | 2003-10-28 | 3M Innovative Properties Company | Passive electrical article, circuit articles thereof, and circuit articles comprising a passive electrical article |
| US6274224B1 (en) | 1999-02-01 | 2001-08-14 | 3M Innovative Properties Company | Passive electrical article, circuit articles thereof, and circuit articles comprising a passive electrical article |
| JP4509437B2 (en) * | 2000-09-11 | 2010-07-21 | Ｈｏｙａ株式会社 | Manufacturing method of multilayer wiring board |
| JP2002174667A (en) * | 2000-09-11 | 2002-06-21 | Hoya Corp | Multilayerd wiring board, and method of manufacturing the same |
| US6577492B2 (en) | 2001-07-10 | 2003-06-10 | 3M Innovative Properties Company | Capacitor having epoxy dielectric layer cured with aminophenylfluorenes |
| JP4570338B2 (en) * | 2003-06-20 | 2010-10-27 | 日本特殊陶業株式会社 | Intermediate board with built-in capacitor |
| JP2005012107A (en) * | 2003-06-20 | 2005-01-13 | Ngk Spark Plug Co Ltd | Intermediate substrate with built-in capacitor |
| US7875808B2 (en) | 2005-09-19 | 2011-01-25 | Industrial Technology Research Institute | Embedded capacitor device having a common coupling area |
| JP2007214437A (en) * | 2006-02-10 | 2007-08-23 | Dainippon Printing Co Ltd | Wiring board incorporated with passive element, and manufacturing method thereof |
| JP2010512667A (en) * | 2006-12-13 | 2010-04-22 | インテル コーポレイション | Small electronic device with bridge interconnection to upper conductive layer of passive buried structure and method of making the same |
| JP4932912B2 (en) * | 2006-12-13 | 2012-05-16 | インテル コーポレイション | Small electronic device with bridge interconnection to upper conductive layer of passive buried structure and method of making the same |
| JP2010530644A (en) * | 2007-06-19 | 2010-09-09 | イー・アイ・デュポン・ドウ・ヌムール・アンド・カンパニー | Method for integrating thin film capacitors into the build-up layer of printed wiring boards |
| WO2011086795A1 (en) * | 2010-01-15 | 2011-07-21 | 三洋電機株式会社 | Capacitor element and substrate with built-in capacitor |
| EP3346809A4 (en) * | 2016-03-04 | 2018-11-21 | Alps Electric Co., Ltd. | Electronic circuit module and method for testing electronic circuit module |
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