JPH07297313A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH07297313A JPH07297313A JP8193494A JP8193494A JPH07297313A JP H07297313 A JPH07297313 A JP H07297313A JP 8193494 A JP8193494 A JP 8193494A JP 8193494 A JP8193494 A JP 8193494A JP H07297313 A JPH07297313 A JP H07297313A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- substrate body
- solder resist
- resist film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、下面にバンプを有する
半導体装置およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bump on its lower surface and a method for manufacturing the same.
【０００２】近年、半導体装置には、その外形寸法が小
さく、かつ、実装が容易であることが望ましい。In recent years, it is desirable that a semiconductor device has a small outer dimension and is easy to mount.
【０００３】リード端子が半導体装置本体の周側面から
突き出した構造のＱＦＰ（Quad Flat Package）型の半
導体装置では、リード端子が３００程度にまで増加する
と、リードのピッチが０．３ｍｍ程度にまで狭くなっ
て、ＱＦＰ型の半導体装置の実装が非常に困難となって
いる。ＱＦＰ型の半導体装置の実装を考慮し、そのリー
ドピッチを広くすると、その外形寸法が大きくなってし
まう。In a QFP (Quad Flat Package) type semiconductor device having lead terminals protruding from the peripheral side surface of the semiconductor device body, when the lead terminals are increased to about 300, the lead pitch is narrowed to about 0.3 mm. As a result, it becomes very difficult to mount a QFP type semiconductor device. If the lead pitch is widened in consideration of the mounting of the QFP type semiconductor device, the outer dimension becomes large.
【０００４】そこで、端子を設ける場所を、半導体装置
本体の下面とし、この下面にバンプ状の端子を格子状に
配した、ＢＧＡ（Ball Grid Array ）型の半導体装置が
提案されている。このＢＧＡ型の半導体装置は、その外
形寸法を大きくすることなく、端子のピッチを大きくす
ることができ、実装が簡単である。Therefore, there has been proposed a BGA (Ball Grid Array) type semiconductor device in which terminals are provided on the lower surface of the semiconductor device main body, and bump-shaped terminals are arranged on the lower surface in a grid pattern. In this BGA type semiconductor device, the pitch of the terminals can be increased without increasing the external dimensions, and the mounting is easy.
【０００５】また、近年、ＢＧＡ型の半導体装置の信頼
性を向上させるため、耐水性の向上したものが必要とさ
れている。Further, in recent years, in order to improve the reliability of the BGA type semiconductor device, one having improved water resistance is required.
【０００６】[0006]
【従来の技術】従来のＢＧＡ型の半導体装置の断面図を
図９に示す。このＢＧＡ型の半導体装置は、下面にバン
プ１を格子状に有する基板２と、この基板２の上面にダ
イボンディングされた半導体素子３と、この半導体素子
３のパッドと基板２のパッドとにボンディングされたワ
イヤー４と、半導体素子３の上面および側面を覆う樹脂
パッケージ部５とで構成される。2. Description of the Related Art A sectional view of a conventional BGA type semiconductor device is shown in FIG. In this BGA type semiconductor device, a substrate 2 having bumps 1 in a grid pattern on the lower surface thereof, a semiconductor element 3 die-bonded to the upper surface of the substrate 2, a pad of the semiconductor element 3 and a pad of the substrate 2 are bonded. The formed wire 4 and the resin package portion 5 that covers the upper surface and the side surface of the semiconductor element 3.
【０００７】上記基板２は、基板本体６と、この基板本
体６の表裏面に被着されたソルダレジスト膜７などで構
成される。The substrate 2 is composed of a substrate body 6 and a solder resist film 7 deposited on the front and back surfaces of the substrate body 6.
【０００８】この基板本体６は多層構造のものであり、
内層に銅配線を有している。また、この基板本体６に
は、高い機械的強度および良好な耐熱性が求められてい
る。このため、基板本体６には、エポキシ樹脂にガラス
繊維を混入した材料が使用されている。The substrate body 6 has a multi-layer structure,
It has copper wiring in the inner layer. Further, the substrate body 6 is required to have high mechanical strength and good heat resistance. Therefore, the substrate body 6 is made of a material in which glass fiber is mixed with epoxy resin.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、従来の
ＢＧＡ型の半導体装置は、基板２の周側面において、基
板本体６が露出する構造である。すなわち、基板本体６
の周側面６ａはソルダレジスト膜７で被覆されていな
い。However, the conventional BGA type semiconductor device has a structure in which the substrate body 6 is exposed on the peripheral side surface of the substrate 2. That is, the substrate body 6
The peripheral side surface 6a of is not covered with the solder resist film 7.
【００１０】これは、基板本体６の全体をソルダレジス
ト膜７で覆ったものが型で抜かれたり、または、ダイシ
ングで切断されたりして、正方形に成形された基板２が
製造されるからである。This is because the substrate body 6 which is entirely covered with the solder resist film 7 is die-cut or cut by dicing to manufacture the square-shaped substrate 2. .
【００１１】そして、基板本体６はガラス繊維を含んで
いる。このガラス繊維は吸水し易い物質である。The substrate body 6 contains glass fiber. This glass fiber is a substance that easily absorbs water.
【００１２】したがって、従来のＢＧＡ型の半導体装置
は、基板本体６の周側面６ａが露出し、基板本体６にガ
ラス繊維が含まれるので、この周側面６ａから水分が基
板本体６内に侵入し易い構造となる。Therefore, in the conventional BGA type semiconductor device, the peripheral side surface 6a of the substrate main body 6 is exposed and the glass fiber is contained in the substrate main body 6, so that moisture penetrates into the substrate main body 6 from the peripheral side surface 6a. The structure is easy.
【００１３】この基板本体６内に水分が侵入すると、基
板本体６の内層の配線が腐食し始める。さらに、内層の
配線に接続された電極パッドが腐食する。この結果、Ｂ
ＧＡ型の半導体装置の特性不良が引き起こされることと
なる。When water enters the board body 6, the wiring in the inner layer of the board body 6 begins to corrode. Furthermore, the electrode pads connected to the inner layer wiring are corroded. As a result, B
This will cause defective characteristics of the GA type semiconductor device.
【００１４】さらに、基板本体６の内層の配線の腐食が
進むと、遂には、内層の配線が断線し、ＢＧＡ型の半導
体装置の寿命が短くなっていた。Further, when the inner layer wiring of the substrate body 6 is corroded, the inner layer wiring is finally broken, and the life of the BGA type semiconductor device is shortened.
【００１５】[0015]
【発明の目的】そこで、本発明は上記課題に鑑みなされ
たもので、基板本体内への水分の侵入を防止した半導体
装置およびその製造方法を提供することを目的とする。SUMMARY OF THE INVENTION Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same in which moisture is prevented from entering the substrate body.
【００１６】[0016]
【課題を解決するための手段】上記課題は、以下の発明
の構成で解決される。The above problems can be solved by the following constitutions of the invention.
【００１７】請求項１の発明は、下面にバンプを有する
基板と、この基板上に搭載され、該バンプと電気的に接
続された半導体素子と、上記基板上に形成され、上記半
導体素子を封止する樹脂パッケージ部と、上記基板の基
板本体の上面および下面を被覆するソルダレジスト膜
と、を備えた半導体装置において、上記基板本体の周側
面を上記バンプより高い融点を有する耐水部材で被覆し
て構成した半導体装置である。例えば、この耐水部材の
材質は、フッ素樹脂、ＳｉＮ、Ａｌである。According to a first aspect of the present invention, a substrate having a bump on its lower surface, a semiconductor element mounted on the substrate and electrically connected to the bump, and a semiconductor element formed on the substrate and sealing the semiconductor element are provided. In a semiconductor device including a resin package portion that stops and a solder resist film that covers the upper surface and the lower surface of the substrate body of the substrate, the peripheral side surface of the substrate body is covered with a water resistant member having a melting point higher than that of the bumps. The semiconductor device is configured as follows. For example, the material of the water resistant member is fluororesin, SiN, Al.
【００１８】また、請求項２の発明は、請求項１の基板
本体が多層構造であり、この内層に配線が形成されて構
成した半導体装置である。According to a second aspect of the present invention, there is provided a semiconductor device in which the substrate body according to the first aspect has a multi-layer structure and wiring is formed in the inner layer.
【００１９】また、請求項３の発明は、請求項１の耐水
部材がソルダレジスト膜であるように構成した半導体装
置である。According to a third aspect of the invention, there is provided a semiconductor device in which the water resistant member according to the first aspect is a solder resist film.
【００２０】また、請求項４の発明は、請求項１の耐水
部材が接合部材を介して基板本体の周側面に被覆されて
構成した半導体装置である。According to a fourth aspect of the present invention, there is provided a semiconductor device in which the water resistant member according to the first aspect is coated on the peripheral side surface of the substrate body via a joining member.
【００２１】また、請求項５の発明は、請求項１の耐水
部材がソルダレジスト膜に第２の耐水部材を被覆したも
ので構成した半導体装置である。According to a fifth aspect of the present invention, there is provided a semiconductor device in which the water resistant member of the first aspect comprises a solder resist film coated with a second water resistant member.
【００２２】また、請求項６の発明は、基板の基板本体
の上面および下面にソルダレジスト膜を形成する第１工
程と、この基板本体の周側面をバンプより高い融点を有
する耐水部材で被覆する第２工程と、基板上に半導体素
子を搭載する第３工程と、この半導体素子を封止する樹
脂パッケージ部を基板上に形成する第４工程と、基板の
下面に半導体素子と電気的に接続されるバンプを形成す
る第５工程と、で構成した半導体装置の製造方法であ
る。According to a sixth aspect of the invention, the first step of forming a solder resist film on the upper surface and the lower surface of the substrate body of the substrate, and the peripheral side surface of the substrate body are covered with a water resistant member having a melting point higher than that of the bumps. A second step, a third step of mounting the semiconductor element on the substrate, a fourth step of forming a resin package portion for sealing the semiconductor element on the substrate, and an electrical connection to the semiconductor element on the lower surface of the substrate And a fifth step of forming bumps to be formed.
【００２３】また、請求項７の発明は、請求項６の第２
工程に代えて、基板の基板本体の周側面にソルダレジス
ト膜を形成する工程を有して構成した半導体装置の製造
方法である。The invention of claim 7 is the second aspect of claim 6.
It is a method of manufacturing a semiconductor device having a step of forming a solder resist film on the peripheral side surface of the substrate body of the substrate instead of the step.
【００２４】また、請求項８の発明は、請求項６の第２
工程に代えて、接合部材に耐水部材を形成し、基板の基
板本体の周側面にこの接合部材を形成する工程を有して
構成した半導体装置の製造方法である。The invention of claim 8 is the second aspect of claim 6.
It is a method of manufacturing a semiconductor device, which includes a step of forming a water resistant member on the bonding member and forming the bonding member on the peripheral side surface of the substrate main body of the substrate instead of the step.
【００２５】また、請求項９の発明は、請求項６の第２
工程に代えて、基板の基板本体の周側面にソルダレジス
ト膜を形成し、このソルダレジスト膜に第２の耐水部材
を形成する工程を有して構成した半導体装置の製造方法
である。The invention of claim 9 is the second aspect of claim 6.
It is a method of manufacturing a semiconductor device including a step of forming a solder resist film on the peripheral side surface of the substrate body of the substrate instead of the step, and forming a second water resistant member on the solder resist film.
【００２６】[0026]
【作用】上述のように、請求項１の発明の半導体装置
は、基板本体の周側面をバンプより高い融点を有する耐
水部材で被覆している。このため、耐水部材は、基板本
体内への水分の侵入を防止するように作用する。As described above, in the semiconductor device according to the first aspect of the invention, the peripheral side surface of the substrate body is covered with the water resistant member having a melting point higher than that of the bump. Therefore, the water resistant member acts so as to prevent water from entering the substrate body.
【００２７】また、請求項２の発明の半導体装置は、請
求項１の基板本体が多層構造であり、この内層に配線が
形成されている。このため、耐水部材は、基板本体の内
層の配線を腐食させないように作用する。According to a second aspect of the semiconductor device of the present invention, the substrate body of the first aspect has a multi-layer structure, and the wiring is formed in the inner layer. Therefore, the water resistant member acts so as not to corrode the wiring in the inner layer of the substrate body.
【００２８】また、請求項３の発明の半導体装置は、請
求項１の耐水部材がソルダレジスト膜であるので、この
ソルダレジスト膜は基板本体の周側面を被覆するように
作用する。Further, in the semiconductor device of the invention of claim 3, since the water resistant member of claim 1 is the solder resist film, the solder resist film acts so as to cover the peripheral side surface of the substrate body.
【００２９】また、請求項４の発明の半導体装置は、請
求項１の耐水部材が接合部材を介して基板本体の周側面
に被覆されているので、接合部材が基板本体の周側面と
耐水部材との接合を介在するように作用する。Further, in the semiconductor device of the invention of claim 4, since the water resistant member of claim 1 is coated on the peripheral side surface of the substrate main body through the bonding member, the bonding member is the peripheral side surface of the substrate main body and the water resistant member. It acts so as to intervene in joining with.
【００３０】また、請求項５の発明の半導体装置は、請
求項１の耐水部材がソルダレジスト膜に第２の耐水部材
を被覆したものであるので、第２の耐水部材が該ソルダ
レジスト膜への水分の侵入を防止するように作用する。Further, in the semiconductor device of the present invention of claim 5, the water resistant member of claim 1 is a solder resist film coated with a second water resistant member, so that the second water resistant member is applied to the solder resist film. It acts to prevent the ingress of water.
【００３１】また、請求項６の発明の半導体装置の製造
方法は、基板本体の周側面をバンプより高い融点を有す
る耐水部材で被覆するので、耐水部材がバンプ形成の際
に溶けないように作用する。Further, in the method of manufacturing a semiconductor device according to the present invention, since the peripheral side surface of the substrate body is covered with the water resistant member having a melting point higher than that of the bump, the water resistant member does not melt during the formation of the bump. To do.
【００３２】また、請求項７の発明の半導体装置の製造
方法は、請求項６の第２工程に代えて、基板の基板本体
の周側面にソルダレジスト膜を形成する工程を有するの
で、このソルダレジスト膜と上記第１工程のソルダレジ
スト膜とを一体化するように作用する。Further, since the semiconductor device manufacturing method of the invention of claim 7 has a step of forming a solder resist film on the peripheral side surface of the substrate main body of the substrate, instead of the second step of claim 6, this solder is used. It works so as to integrate the resist film and the solder resist film in the first step.
【００３３】また、請求項８の発明の半導体装置の製造
方法は、請求項６の第２工程に代えて、接合部材に耐水
部材を形成し、基板の基板本体の周側面にこの接合部材
を形成する工程を有するので、耐水部材と基板本体の周
側面との接合強度を強化するように作用する。Further, in the method for manufacturing a semiconductor device according to the invention of claim 8, instead of the second step of claim 6, a water resistant member is formed on the bonding member, and the bonding member is formed on the peripheral side surface of the substrate body of the substrate. Since it has a forming step, it acts to enhance the bonding strength between the water resistant member and the peripheral side surface of the substrate body.
【００３４】また、請求項９の発明の半導体装置の製造
方法は、請求項６の第２工程に代えて、基板の基板本体
の周側面にソルダレジスト膜を形成し、このソルダレジ
スト膜に第２の耐水部材を形成する工程を有するので、
第２の耐水部材が該ソルダレジスト膜への水分の侵入を
防止するように作用する。In the method for manufacturing a semiconductor device according to a ninth aspect of the invention, instead of the second step of the sixth aspect, a solder resist film is formed on the peripheral side surface of the substrate body of the substrate, and the solder resist film is formed on the peripheral side surface of the substrate. Since it has a step of forming the water resistant member of 2,
The second water resistant member acts so as to prevent water from entering the solder resist film.
【００３５】[0035]
【実施例】図１を用いて本発明の第１実施例に係るＢＧ
Ａ型の半導体装置を説明する。図１（Ａ）は、このＢＧ
Ａ型の半導体装置の断面図を示し、図１（Ｂ）は、この
ＢＧＡ型の半導体装置の平面図を示す。図１において図
９と同一部分には同一符号を付している。EXAMPLE A BG according to a first example of the present invention with reference to FIG.
An A type semiconductor device will be described. This BG is shown in FIG.
A cross-sectional view of an A-type semiconductor device is shown, and FIG. 1B is a plan view of this BGA-type semiconductor device. In FIG. 1, the same parts as those in FIG. 9 are designated by the same reference numerals.
【００３６】このＢＧＡ型の半導体装置は、バンプ１と
基板１０と半導体素子３とワイヤー４と樹脂パッケージ
５とで構成される。This BGA type semiconductor device comprises a bump 1, a substrate 10, a semiconductor element 3, a wire 4 and a resin package 5.
【００３７】基板１０は、基板本体１１とソルダレジス
ト膜１２と電極パッド１３などで構成される。The substrate 10 is composed of a substrate body 11, a solder resist film 12, an electrode pad 13, and the like.
【００３８】この基板本体１１は多層構造であり、内層
に銅配線を有し、基板本体１１の厚さは０．４ｍｍであ
る。また、この基板本体１１には、高い機械的強度およ
び良好な耐熱性のため、エポキシ樹脂にガラス繊維を混
入した材料が使用されている。The substrate body 11 has a multi-layer structure, has copper wiring in the inner layer, and the thickness of the substrate body 11 is 0.4 mm. Further, for the substrate body 11, a material in which glass fiber is mixed with epoxy resin is used because of its high mechanical strength and good heat resistance.
【００３９】基板本体１１の周側面１１ａには、ソルダ
レジスト膜１２が１ｍｍの厚さで被覆されている。ま
た、基板本体１１の上面１１ｃの所定箇所および下面１
１ｄの所定箇所には、ソルダレジスト膜１２が７μｍの
厚さで被覆されている。このソルダレジスト膜１２は、
バンプ１より融点が高く、耐水性および撥水性が良好な
ものである。The peripheral side surface 11a of the substrate body 11 is covered with a solder resist film 12 with a thickness of 1 mm. In addition, a predetermined portion of the upper surface 11c of the substrate body 11 and the lower surface 1
A predetermined portion of 1d is covered with a solder resist film 12 with a thickness of 7 μm. This solder resist film 12 is
It has a melting point higher than that of the bump 1 and has good water resistance and water repellency.
【００４０】電極パッド１３はＡｕまたはＮｉ製であ
り、基板本体１１の内層の配線またはスルーホールを介
して基板本体１１上の半導体素子用パッドに電気的に接
続されている。The electrode pad 13 is made of Au or Ni, and is electrically connected to the semiconductor element pad on the substrate body 11 via the wiring or through hole in the inner layer of the substrate body 11.
【００４１】バンプ１は、ハンダ製の半球状であり、基
板１０の下面１０ａに格子状に形成される。The bumps 1 are solder-made hemispheres and are formed in a grid pattern on the lower surface 10a of the substrate 10.
【００４２】半導体素子３は、エポキシ系のペースト状
接着剤で、基板１０の半導体搭載部１０ｂに接着固定さ
れている。The semiconductor element 3 is adhered and fixed to the semiconductor mounting portion 10b of the substrate 10 with an epoxy paste adhesive.
【００４３】ワイヤー４は、半導体素子３上のパッドと
基板１０上の半導体素子用パッドとにボンディングされ
て、両者間にはり渡してある。The wire 4 is bonded to the pad on the semiconductor element 3 and the pad for semiconductor element on the substrate 10 and is spread between the both.
【００４４】樹脂パッケージ部５はエポキシ樹脂よりな
り、半導体素子３の上面および側面を覆って基板１０上
に形成され、半導体素子３を封止する。The resin package portion 5 is made of epoxy resin, is formed on the substrate 10 so as to cover the upper surface and the side surface of the semiconductor element 3, and seals the semiconductor element 3.
【００４５】したがって、このＢＧＡ型の半導体装置
は、基板本体１１の周側面１１ａが耐水性および撥水性
の良いソルダレジスト膜１２で覆われているので、この
周側面１１ａから水分が基板本体１１内に侵入しない構
造となる。Therefore, in this BGA type semiconductor device, since the peripheral side surface 11a of the substrate body 11 is covered with the solder resist film 12 having good water resistance and water repellency, moisture is absorbed from the peripheral side surface 11a into the substrate body 11. The structure will not invade.
【００４６】このため、基板本体１１の内層の配線およ
び電極パッド１３の腐食が防止される。この結果、ＢＧ
Ａ型の半導体装置の特性不良が生じない。Therefore, the wiring of the inner layer of the substrate body 11 and the electrode pad 13 are prevented from being corroded. As a result, BG
Characteristic defects of the A type semiconductor device do not occur.
【００４７】さらに、基板本体１１の内層の配線が腐食
しないので、内層の配線が断線しない。このため、ＢＧ
Ａ型の半導体装置の寿命が短くなることもない。Furthermore, since the wiring in the inner layer of the substrate body 11 does not corrode, the wiring in the inner layer does not break. Therefore, BG
The life of the A type semiconductor device is not shortened.
【００４８】次に、図１のＢＧＡ型の半導体装置の製造
方法を図２を用いて説明する。Next, a method of manufacturing the BGA type semiconductor device of FIG. 1 will be described with reference to FIG.
【００４９】図２（Ａ）において、多層化され、エポキ
シ樹脂にガラス繊維を混入した基板本体１１に、電極パ
ッド１３、半導体素子用パッド、スルーホールなどを形
成したものを３枚以上準備する。In FIG. 2 (A), three or more sheets are prepared in which the electrode pad 13, the semiconductor element pad, the through hole, etc. are formed on the substrate body 11 which is multi-layered and contains epoxy resin mixed with glass fiber.
【００５０】この準備したものを液状ソルダレジスト中
に浸積させる。この結果、各基板本体１１の露出面の全
て（上面１１ｃ、下面１１ｄ、周側面１１ａ）がソルダ
レジスト膜１２で被覆される。さらに、各基板本体１１
がソルダレジスト膜１２を介して接続される。This prepared product is immersed in a liquid solder resist. As a result, all the exposed surfaces (upper surface 11c, lower surface 11d, peripheral side surface 11a) of each substrate body 11 are covered with the solder resist film 12. Further, each board body 11
Are connected via the solder resist film 12.
【００５１】図２（Ｂ）において、各基板本体１１の接
続箇所のソルダレジスト膜１２を、１点鎖線Ａに沿って
ダイシングで切断する。In FIG. 2B, the solder resist film 12 at the connection portion of each substrate body 11 is cut along the one-dot chain line A by dicing.
【００５２】この結果、図２（Ｃ）に示すように、基板
本体１１の周側面１１ａには、ソルダレジスト膜１２が
被覆される。As a result, as shown in FIG. 2C, the peripheral side surface 11a of the substrate body 11 is covered with the solder resist film 12.
【００５３】図２（Ｄ）において、ソルダレジスト膜１
２の上面に半導体素子搭載用孔１４を、下面にバンプ用
孔１５をそれぞれ形成する。詳しくは、マスクフィルム
を用いてソルダレジスト膜１２を露光し、現像により不
要な部分を溶解除去することにより、各孔１４、１５が
形成される。In FIG. 2D, the solder resist film 1
2, a semiconductor element mounting hole 14 is formed on the upper surface of the substrate 2, and a bump hole 15 is formed on the lower surface thereof. In detail, the holes 14 and 15 are formed by exposing the solder resist film 12 using a mask film and dissolving and removing unnecessary portions by development.
【００５４】図２（Ｅ）において、基板本体１１の半導
体素子搭載部１１ｂ上にエポキシ系のペースト状接着剤
を介して半導体素子３の下面を接着固定する。この半導
体素子３上のパッドと基板本体１１の半導体素子用パッ
ドとをワイヤー４で接続する。半導体素子３の側面およ
び上面をエポキシ樹脂製の樹脂パッケージ５で覆う。こ
の結果、半導体素子３は封止される。In FIG. 2E, the lower surface of the semiconductor element 3 is adhesively fixed onto the semiconductor element mounting portion 11b of the substrate body 11 via an epoxy-based paste adhesive. The pads on the semiconductor element 3 and the semiconductor element pads of the substrate body 11 are connected by wires 4. A side surface and an upper surface of the semiconductor element 3 are covered with a resin package 5 made of epoxy resin. As a result, the semiconductor element 3 is sealed.
【００５５】次に、上下反転させ、電極パッド１３上に
フラックスを形成する。このフラックスの粘着力により
ハンダボールを電極パッド１３に点接触させる。ハンダ
ボールの融点以上の温度に赤外線で加熱する。Next, it is turned upside down to form a flux on the electrode pad 13. The solder ball is brought into point contact with the electrode pad 13 by the adhesive force of this flux. Infrared heat to a temperature above the melting point of the solder balls.
【００５６】この結果、ハンダボールが再溶融し、その
表面張力により電極パッド１３上にバンプ１がソルダレ
ジスト膜１２より突出して形成される。このとき、ソル
ダレジスト膜１２の融点はバンプより高いので、溶けな
い。As a result, the solder balls are remelted, and the bumps 1 are formed on the electrode pads 13 so as to project from the solder resist film 12 due to the surface tension. At this time, the melting point of the solder resist film 12 is higher than that of the bumps, and therefore the solder resist film 12 does not melt.
【００５７】以上により、図１のＢＧＡ型の半導体装置
が製造される。As described above, the BGA type semiconductor device of FIG. 1 is manufactured.
【００５８】次に、図３を用いて本発明の第２実施例に
係るＢＧＡ型の半導体装置を説明する。図３（Ａ）はこ
のＢＧＡ型の半導体装置の断面図を示し、図３（Ｂ）は
このＢＧＡ型の半導体装置の平面図を示す。図３におい
て図１と同一部分には同一符号を付している。Next, a BGA type semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. 3A shows a cross-sectional view of this BGA type semiconductor device, and FIG. 3B shows a plan view of this BGA type semiconductor device. 3, the same parts as those in FIG. 1 are designated by the same reference numerals.
【００５９】このＢＧＡ型の半導体装置は、基板２０を
有することが図１のものと異なる。この基板２０は、基
板本体１１とソルダレジスト膜２２、２３とフッ素樹脂
部材２４と電極パッド１３などで構成される。この基板
２０の下面２０ａには、バンプ１が格子状に形成されて
いる。This BGA type semiconductor device differs from that of FIG. 1 in that it has a substrate 20. The substrate 20 is composed of a substrate body 11, solder resist films 22 and 23, a fluororesin member 24, an electrode pad 13, and the like. The bumps 1 are formed in a grid pattern on the lower surface 20a of the substrate 20.
【００６０】この基板本体１１は基板本体１１の周側面
１１ａには、フッ素樹脂部材２４が被覆されている。ま
た、基板本体１１の上面１１ｃの所定箇所にはソルダレ
ジスト膜２２が、その下面１１ｄの所定箇所にはソルダ
レジスト膜２３がそれぞれ被覆されている。このフッ素
樹脂部材２４およびソルダレジスト膜２２、２３はバン
プ１より融点が高く、耐水性および撥水性が良好なもの
である。In the substrate body 11, the peripheral side surface 11a of the substrate body 11 is covered with a fluororesin member 24. Further, a predetermined portion of the upper surface 11c of the substrate body 11 is covered with a solder resist film 22, and a predetermined portion of the lower surface 11d thereof is covered with a solder resist film 23. The fluororesin member 24 and the solder resist films 22 and 23 have a higher melting point than the bump 1 and have good water resistance and water repellency.
【００６１】したがって、このＢＧＡ型の半導体装置
は、基板本体１１の周側面１１ａが耐水性および撥水性
の良いフッ素樹脂部材２４で覆われている。このため、
この周側面１１ａから水分が基板本体１１内に侵入しな
い構造となる。Therefore, in this BGA type semiconductor device, the peripheral side surface 11a of the substrate body 11 is covered with the fluororesin member 24 having excellent water resistance and water repellency. For this reason,
Water is prevented from entering the substrate body 11 from the peripheral side surface 11a.
【００６２】また、図３のＢＧＡ型の半導体装置は、図
９の従来のＢＧＡ型の半導体装置にフッ素樹脂部材２４
を設けた構造と同じである。このため、図３のＢＧＡ型
の半導体装置は、従来のものを利用することができる。The BGA type semiconductor device shown in FIG. 3 has the same structure as the conventional BGA type semiconductor device shown in FIG.
Is the same as the structure provided with. Therefore, the BGA type semiconductor device of FIG. 3 can use a conventional one.
【００６３】なお、基板本体１１の周側面１１ａを被覆
するものは、フッ素樹脂部材２４に代えて、ＳｉＮ部
材、バンプ１より融点の高い金属部材、または、バンプ
１より融点の高いポリエステル部材で被覆されてもよ
い。これらの部材は、耐水性および撥水性に優れてい
る。その他の作用および効果は、上記第１実施例のもの
と同じである。It should be noted that what covers the peripheral side surface 11a of the substrate body 11 is replaced with the fluororesin member 24 by a SiN member, a metal member having a melting point higher than that of the bump 1, or a polyester member having a melting point higher than that of the bump 1. May be done. These members are excellent in water resistance and water repellency. Other functions and effects are the same as those of the first embodiment.
【００６４】次に、図３のＢＧＡ型の半導体装置の製造
方法を図４を用いて説明する。Next, a method of manufacturing the BGA type semiconductor device of FIG. 3 will be described with reference to FIG.
【００６５】図４（Ａ）において、図２（Ａ）と同様
に、多層化され、エポキシ樹脂にガラス繊維が混入さ
れ、電極パッド等が形成された基板本体１１を３枚以上
準備する。この準備したものを液状ソルダレジスト中に
浸積させる。なお、電極パッドなどは、図２（Ａ）のと
きと同じであるので、図示されていない。In FIG. 4A, as in FIG. 2A, three or more substrate bodies 11 having multiple layers, glass fibers mixed in an epoxy resin, and electrode pads and the like are prepared. This prepared product is immersed in a liquid solder resist. The electrode pads and the like are not shown because they are the same as those in FIG.
【００６６】この結果、各基板本体１１の露出面の全て
がソルダレジスト膜２５で被覆される。さらに、各基板
本体１１がソルダレジスト膜２５を介して接続される。As a result, the entire exposed surface of each substrate body 11 is covered with the solder resist film 25. Further, each substrate body 11 is connected via the solder resist film 25.
【００６７】図４（Ｂ）において、ソルダレジスト膜２
５を介して各基板本体１１を１点鎖線Ｂに沿ってダイシ
ングで切断する。In FIG. 4B, the solder resist film 2
Each substrate main body 11 is cut by dicing along the one-dot chain line B through 5.
【００６８】この結果、基板本体１１の端部が切断さ
れ、基板本体１１の上面１１ｃにはソルダレジスト膜２
２が、その下面１１ｄにはソルダレジスト膜２３がそれ
ぞれ被覆される。さらに、基板本体１１の周側面１１ａ
は、露出している。As a result, the edge of the substrate body 11 is cut, and the solder resist film 2 is formed on the upper surface 11c of the substrate body 11.
2, the lower surface 11d thereof is covered with the solder resist film 23, respectively. Further, the peripheral side surface 11a of the substrate body 11
Is exposed.
【００６９】図４（Ｃ）において、各基板本体１１を平
面台２６上に載置する。このとき、各基板本体１１の周
側面１１ａ同士の間に一定の隙間２７を設ける。In FIG. 4C, each substrate body 11 is placed on the flat table 26. At this time, a constant gap 27 is provided between the peripheral side surfaces 11 a of each substrate body 11.
【００７０】図４（Ｄ）において、上記隙間２７に、耐
水性および撥水性の良いフッ素樹脂部材２４を形成す
る。この結果、各基板本体１１がフッ素樹脂部材２４で
接続され、各基板本体１１の周側面１１ａがフッ素樹脂
部材２４で被覆される。In FIG. 4D, a fluororesin member 24 having good water resistance and water repellency is formed in the gap 27. As a result, each substrate body 11 is connected by the fluororesin member 24, and the peripheral side surface 11 a of each substrate body 11 is covered by the fluororesin member 24.
【００７１】図４（Ｅ）において、フッ素樹脂部材２４
を１点鎖線Ｃに沿ってダイシングで切断する。この結
果、図４（Ｆ）に示すように、基板本体１１の周側面１
１ａがフッ素樹脂部材２４で、その上面１１ｃがソルダ
レジスト膜２２で、その下面１１ｄがソルダレジスト膜
２３でそれぞれ被覆された基板２０が製造される。In FIG. 4E, the fluororesin member 24
Is cut along the one-dot chain line C by dicing. As a result, as shown in FIG.
A substrate 20 in which 1a is a fluororesin member 24, its upper surface 11c is a solder resist film 22, and its lower surface 11d is a solder resist film 23 is manufactured.
【００７２】その後の孔明け工程などは、上記第１実施
例のときと同じである。Subsequent drilling steps are the same as those in the first embodiment.
【００７３】以上により、図３のＢＧＡ型の半導体装置
が製造される。そして、上記隙間２７に形成される部材
は、ＳｉＮ部材、バンプ１より融点の高い金属部材、ま
たは、バンプ１より融点の高いポリエステル部材でもよ
い。As described above, the BGA type semiconductor device of FIG. 3 is manufactured. The member formed in the gap 27 may be a SiN member, a metal member having a melting point higher than that of the bump 1, or a polyester member having a melting point higher than that of the bump 1.
【００７４】次に、図５を用いて本発明の第３実施例に
係るＢＧＡ型の半導体装置を説明する。図５（Ａ）はこ
のＢＧＡ型の半導体装置の断面図を示し、図５（Ｂ）は
このＢＧＡ型の半導体装置の平面図を示す。図５におい
て図３と同一部分には同一符号を付している。Next, a BGA type semiconductor device according to the third embodiment of the present invention will be described with reference to FIG. 5A shows a cross-sectional view of this BGA type semiconductor device, and FIG. 5B shows a plan view of this BGA type semiconductor device. 5, the same parts as those in FIG. 3 are designated by the same reference numerals.
【００７５】このＢＧＡ型の半導体装置は、基板３０を
有することが図３のものと異なる。この基板３０は、基
板本体１１とソルダレジスト膜２２、２３とポリイミド
部材３１と耐水部材３２と電極パッド１３などで構成さ
れる。この基板３０の下面３０ａには、バンプ１が格子
状に形成されている。This BGA type semiconductor device differs from that of FIG. 3 in that it has a substrate 30. The substrate 30 is composed of a substrate body 11, solder resist films 22 and 23, a polyimide member 31, a water resistant member 32, an electrode pad 13, and the like. The bumps 1 are formed in a grid pattern on the lower surface 30a of the substrate 30.
【００７６】この基板本体１１は基板本体１１の周側面
１１ａには、接着剤（図示略）を介してポリイミド部材
３１が被覆されている。このポリイミド部材３１はバン
プ１より融点が高い。In the substrate body 11, the peripheral side surface 11a of the substrate body 11 is covered with a polyimide member 31 via an adhesive (not shown). This polyimide member 31 has a higher melting point than the bump 1.
【００７７】このポリイミド部材３１の外周面には、耐
水部材３２が被着されている。この耐水部材３２はバン
プ１より融点が高く、耐水性および撥水性が良好なもの
であり、ポリイミド部材３１との接合強度が高いもので
ある。A water resistant member 32 is attached to the outer peripheral surface of the polyimide member 31. The water resistant member 32 has a melting point higher than that of the bump 1, has good water resistance and water repellency, and has high bonding strength with the polyimide member 31.
【００７８】したがって、このＢＧＡ型の半導体装置
は、基板本体１１の周側面１１ａがポリイミド部材３１
を介して耐水部材３２で覆われている。このため、この
周側面１１ａから基板本体１１内に水分が侵入しない構
造となる。Therefore, in this BGA type semiconductor device, the peripheral side surface 11a of the substrate body 11 is made of the polyimide member 31.
It is covered with the water resistant member 32 through. Therefore, the structure is such that moisture does not enter the substrate body 11 from the peripheral side surface 11a.
【００７９】また、図５のＢＧＡ型の半導体装置にあっ
ては、耐水部材３２が基板本体１１にポリイミド部材３
１を介して接合されている。このため、基板本体１１に
対する耐水部材３２の接合強度が小さなものでも、ポリ
イミド部材３１には耐水部材３２が強固に接合される。Further, in the BGA type semiconductor device of FIG. 5, the water resistant member 32 is formed on the substrate body 11 by the polyimide member 3.
It is joined via 1. Therefore, the water resistant member 32 is firmly bonded to the polyimide member 31, even if the water resistant member 32 has a small bonding strength to the substrate body 11.
【００８０】この耐水部材３２の材質としては、ポリイ
ミド部材３１と強固に接合され、バンプ１の融点より高
く、耐水性および撥水性に優れたものであればよい。例
えば、フッ素樹脂、ＳｉＮ、Ａｌが該当する。The water resistant member 32 may be made of any material that is firmly bonded to the polyimide member 31, is higher than the melting point of the bump 1, and is excellent in water resistance and water repellency. For example, fluororesin, SiN, and Al are applicable.
【００８１】その他の作用および効果は、上記第２実施
例のものと同じである。The other actions and effects are the same as those of the second embodiment.
【００８２】次に、図５のＢＧＡ型の半導体装置の製造
方法を図６を用いて説明する。図６（Ａ）、（Ｂ）の製
造工程は、図４（Ａ）、（Ｂ）のときと同じである。こ
の結果、図６（Ｃ）に示すように、基板本体１１の端部
が切断され、基板本体１１の上面１１ｃにはソルダレジ
スト膜２２が、その下面１１ｄにはソルダレジスト膜２
３がそれぞれ被覆される。さらに、基板本体１１の周側
面１１ａは、露出している。Next, a method of manufacturing the BGA type semiconductor device of FIG. 5 will be described with reference to FIG. The manufacturing process of FIGS. 6A and 6B is the same as that of FIGS. 4A and 4B. As a result, as shown in FIG. 6C, the end of the substrate body 11 is cut, the solder resist film 22 is formed on the upper surface 11c of the substrate body 11, and the solder resist film 2 is formed on the lower surface 11d.
3 are coated respectively. Further, the peripheral side surface 11a of the substrate body 11 is exposed.
【００８３】次に、下面に接着剤が貼着されたポリイミ
ド部材３１の上面に、ＣＶＤまたはＰＶＤで耐水部材３
２を被着させる。Next, the water resistant member 3 is formed by CVD or PVD on the upper surface of the polyimide member 31 whose lower surface is adhered with the adhesive.
Put on 2.
【００８４】図６（Ｄ）において、ポリイミド部材３１
の上面に耐水部材３２を被着させたものを、ポリイミド
部材３１の下面の接着剤を介して、各基板本体１１の周
側面１１ａに接合する。この結果、基板本体１１の周側
面１１ａが被覆され、基板３０が製造される。In FIG. 6D, the polyimide member 31
The water resistant member 32 adhered to the upper surface of the above is bonded to the peripheral side surface 11a of each substrate body 11 via the adhesive on the lower surface of the polyimide member 31. As a result, the peripheral side surface 11a of the substrate body 11 is covered and the substrate 30 is manufactured.
【００８５】その後の工程は、上記第１実施例のときと
同じである。以上により、図５のＢＧＡ型の半導体装置
が製造される。The subsequent steps are the same as those in the first embodiment. As described above, the BGA type semiconductor device of FIG. 5 is manufactured.
【００８６】次に、図７を用いて本発明の第４実施例に
係るＢＧＡ型の半導体装置を説明する。図７（Ａ）はこ
のＢＧＡ型の半導体装置の断面図を示し、図７（Ｂ）は
このＢＧＡ型の半導体装置の平面図を示す。図７におい
て図１と同一部分には同一符号を付している。Next, a BGA type semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 7A shows a sectional view of the BGA type semiconductor device, and FIG. 7B shows a plan view of the BGA type semiconductor device. 7, the same parts as those in FIG. 1 are designated by the same reference numerals.
【００８７】このＢＧＡ型の半導体装置は、基板４０を
有することが図１のものと異なる。この基板４０は、基
板本体１１とソルダレジスト膜１２と耐水部材４１と電
極パッド１３などで構成される。この基板４０の下面４
０ａには、バンプ１が格子状に形成されている。This BGA type semiconductor device differs from that of FIG. 1 in that it has a substrate 40. The substrate 40 is composed of a substrate body 11, a solder resist film 12, a water resistant member 41, an electrode pad 13, and the like. Lower surface 4 of this substrate 40
Bumps 1 are formed in a grid pattern on 0a.
【００８８】この基板本体１１は基板本体１１の周側面
１１ａには、上記ソルダレジスト膜１２が被覆されてい
る。このソルダレジスト膜１２の外周面には、耐水部材
４１が被着されている。この耐水部材４１はバンプ１よ
り融点が高く、耐水性および撥水性が良好なものであ
り、ソルダレジスト膜１２との接合強度が高いものであ
る。In the substrate body 11, the peripheral side surface 11a of the substrate body 11 is covered with the solder resist film 12. A water resistant member 41 is attached to the outer peripheral surface of the solder resist film 12. The water resistant member 41 has a higher melting point than the bumps 1, has good water resistance and water repellency, and has high bonding strength with the solder resist film 12.
【００８９】したがって、このＢＧＡ型の半導体装置
は、基板本体１１の周側面１１ａがソルダレジスト膜１
２で覆われている。このため、この周側面１１ａから基
板本体１１内に水分が侵入しない構造となる。Therefore, in this BGA type semiconductor device, the peripheral side surface 11 a of the substrate body 11 is solder resist film 1.
It is covered with 2. Therefore, the structure is such that moisture does not enter the substrate body 11 from the peripheral side surface 11a.
【００９０】また、図７のＢＧＡ型の半導体装置にあっ
ては、耐水部材４１が基板本体１１にソルダレジスト膜
１２を介して接合されている。このため、基板本体１１
に対する耐水部材４１の接合強度が小さなものでも、ソ
ルダレジスト膜１２には耐水部材４１が強固に接合され
る。In the BGA type semiconductor device of FIG. 7, the water resistant member 41 is joined to the substrate body 11 via the solder resist film 12. Therefore, the substrate body 11
Even if the bonding strength of the water resistant member 41 with respect to is small, the water resistant member 41 is firmly bonded to the solder resist film 12.
【００９１】この耐水部材４１の材質としては、ソルダ
レジスト膜１２と強固に接合され、バンプ１の融点より
高く、耐水性および撥水性に優れたものであればよい。
例えば、フッ素樹脂、ＳｉＮ、Ａｌが該当する。The water resistant member 41 may be made of any material that is firmly bonded to the solder resist film 12, is higher than the melting point of the bump 1, and is excellent in water resistance and water repellency.
For example, fluororesin, SiN, and Al are applicable.
【００９２】その他の作用および効果は、上記第２実施
例のものと同じである。The other actions and effects are the same as those of the second embodiment.
【００９３】次に、図７のＢＧＡ型の半導体装置の製造
方法を図８を用いて説明する。Next, a method of manufacturing the BGA type semiconductor device of FIG. 7 will be described with reference to FIG.
【００９４】図８（Ａ）において、基板本体１１を３枚
以上準備する。この準備したものを液状ソルダレジスト
中に浸積させる。この結果、各基板本体１１の上面１１
ｃ、下面１１ｄ、周側面１１ａがソルダレジスト膜１２
で被覆される。さらに、各基板本体１１がソルダレジス
ト膜１２を介して接続される。In FIG. 8A, three or more substrate bodies 11 are prepared. This prepared product is immersed in a liquid solder resist. As a result, the upper surface 11 of each substrate body 11
c, the lower surface 11d, and the peripheral side surface 11a are the solder resist film 12
Is covered with. Further, each substrate body 11 is connected via the solder resist film 12.
【００９５】図８（Ｂ）において、各基板本体１１の接
続箇所のソルダレジスト膜１２を、１点鎖線Ｄに沿って
ダイシングで切断する。In FIG. 8B, the solder resist film 12 at the connection portion of each substrate body 11 is cut along the one-dot chain line D by dicing.
【００９６】この結果、図８（Ｃ）に示すように、基板
本体１１の周側面１１ａには、ソルダレジスト膜１２が
被覆される。この各基板本体１１を平面台２６上に載置
する。このとき、各基板本体１１をソルダレジスト膜１
２で被覆したもの同士の間に一定の隙間４２を設ける。As a result, as shown in FIG. 8C, the peripheral side surface 11a of the substrate body 11 is covered with the solder resist film 12. The respective substrate bodies 11 are placed on the flat table 26. At this time, each substrate body 11 is attached to the solder resist film 1
A constant gap 42 is provided between the two covered with 2.
【００９７】図８（Ｄ）において、上記隙間４２に、耐
水部材４１を形成する。この結果、各基板本体１１をソ
ルダレジスト膜１２で被覆したものが、耐水部材４１で
接続される。In FIG. 8D, a water resistant member 41 is formed in the gap 42. As a result, each substrate body 11 covered with the solder resist film 12 is connected by the water resistant member 41.
【００９８】図８（Ｅ）において、耐水部材４１を１点
鎖線Ｅに沿ってダイシングで切断する。この結果、図８
（Ｆ）に示すように、基板本体１１がソルダレジスト膜
１２で覆われ、このソルダレジスト膜１２の外周面が耐
水部材４１で覆われた基板４０が製造される。In FIG. 8 (E), the water resistant member 41 is cut along the one-dot chain line E by dicing. As a result, FIG.
As shown in (F), the substrate 40 is manufactured in which the substrate body 11 is covered with the solder resist film 12, and the outer peripheral surface of the solder resist film 12 is covered with the water resistant member 41.
【００９９】その後の孔明け工程などは、上記第１実施
例のときと同じである。以上により、図７のＢＧＡ型の
半導体装置が製造される。Subsequent drilling steps and the like are the same as those in the first embodiment. As described above, the BGA type semiconductor device of FIG. 7 is manufactured.
【０１００】[0100]
【発明の効果】以上のように請求項１の発明によれば、
基板本体の周側面をバンプより高い融点を有する耐水部
材で被覆している。このため、耐水部材が基板本体内へ
の水分の侵入を防止する。この結果、基板本体内への水
分侵入に基づく半導体装置の特性不良の発生を防止する
ことができる。As described above, according to the invention of claim 1,
The peripheral side surface of the substrate body is covered with a water resistant member having a melting point higher than that of the bump. Therefore, the water resistant member prevents moisture from entering the substrate body. As a result, it is possible to prevent the occurrence of defective characteristics of the semiconductor device due to the intrusion of water into the substrate body.
【０１０１】さらに、基板本体内に水分が侵入しないの
で、基板本体の材質として、ガラス繊維を含んだエポキ
シ樹脂を用いることができる。このため、基板本体に高
い機械的強度および良好な耐熱性を付与することができ
る。Further, since water does not enter the substrate body, epoxy resin containing glass fiber can be used as the material of the substrate body. Therefore, high mechanical strength and good heat resistance can be imparted to the substrate body.
【０１０２】また、請求項２の発明によれば、請求項１
の基板本体が多層構造であり、この内層に配線が形成さ
れている。このため、耐水部材が基板本体の内層の配線
を腐食させないので、半導体装置の特性不良が引き起こ
されることがない。また、基板本体の内層の配線は腐食
しないので、断線することもない。さらに、基板本体の
内層の配線の断線がないので、半導体装置の寿命が短く
なることもない。According to the invention of claim 2, claim 1
The substrate body has a multi-layer structure, and the wiring is formed in this inner layer. Therefore, the water resistant member does not corrode the wiring in the inner layer of the substrate body, so that the characteristic failure of the semiconductor device is not caused. Moreover, since the wiring in the inner layer of the substrate body does not corrode, it is not broken. Further, since there is no disconnection of the wiring in the inner layer of the substrate body, the life of the semiconductor device will not be shortened.
【０１０３】また、請求項３の発明によれば、請求項１
の耐水部材がソルダレジスト膜である。このため、ソル
ダレジスト膜が基板本体の周側面を被覆する。この結
果、このソルダレジスト膜と、基板本体の上面及び下面
に被覆されたソルダレジスト膜とを一体化することがで
きる。このため、周側面のソルダレジスト膜と、上面及
び下面のソルダレジスト膜との接合強度を強固にするこ
とができる。According to the invention of claim 3, claim 1
The water resistant member is a solder resist film. Therefore, the solder resist film covers the peripheral side surface of the substrate body. As a result, this solder resist film and the solder resist film covering the upper surface and the lower surface of the substrate body can be integrated. Therefore, the bonding strength between the solder resist film on the peripheral side surface and the solder resist film on the upper and lower surfaces can be strengthened.
【０１０４】また、請求項４の発明によれば、請求項１
の耐水部材が接合部材を介して基板本体の周側面に被覆
されている。このため、接合部材が基板本体の周側面と
耐水部材との接合を介在する。この結果、基板本体の周
側面との接合強度の低い耐水部材を用いることができ
る。According to the invention of claim 4, claim 1
The water resistant member is coated on the peripheral side surface of the substrate body via the joining member. Therefore, the joining member intervenes the joining between the peripheral side surface of the substrate body and the water resistant member. As a result, it is possible to use a water resistant member having low bonding strength with the peripheral side surface of the substrate body.
【０１０５】また、請求項５の発明によれば、請求項１
の耐水部材がソルダレジスト膜に第２の耐水部材を被覆
したものである。このため、基板本体の周側面を被覆す
るソルダレジスト膜への水分の侵入を防止する。この結
果、さらに、基板本体の周側面への水分の侵入を防止す
ることができる。According to the invention of claim 5, claim 1
The water resistant member is a solder resist film coated with the second water resistant member. Therefore, it is possible to prevent water from entering the solder resist film covering the peripheral side surface of the substrate body. As a result, it is possible to further prevent moisture from entering the peripheral side surface of the substrate body.
【０１０６】また、請求項６の発明によれば、基板本体
の周側面をバンプより高い融点を有する耐水部材で被覆
する。このため、耐水部材がバンプ形成の際に溶けるこ
とがない。According to the invention of claim 6, the peripheral side surface of the substrate body is covered with a water resistant member having a melting point higher than that of the bump. Therefore, the water resistant member does not melt during bump formation.
【０１０７】また、請求項７の発明によれば、請求項６
の第２工程に代えて、基板の基板本体の周側面にソルダ
レジスト膜を形成する工程を有する。このため、第２工
程のソルダレジスト膜と上記第１工程のソルダレジスト
膜とを一体に形成することができる。すなわち、第１工
程と第２工程を同時に行うことができる。Further, according to the invention of claim 7, claim 6 is provided.
In place of the second step, there is a step of forming a solder resist film on the peripheral side surface of the substrate body of the substrate. Therefore, the solder resist film in the second step and the solder resist film in the first step can be integrally formed. That is, the first step and the second step can be performed simultaneously.
【０１０８】また、請求項８の発明によれば、請求項６
の第２工程に代えて、接合部材に耐水部材を形成し、基
板の基板本体の周側面にこの接合部材を形成する工程を
有する。このため、耐水部材と基板本体の周側面との接
合強度を強化することができる。According to the invention of claim 8, claim 6 is provided.
Instead of the second step, there is a step of forming a water resistant member on the joining member and forming the joining member on the peripheral side surface of the substrate body of the substrate. Therefore, the bonding strength between the water resistant member and the peripheral side surface of the substrate body can be enhanced.
【０１０９】また、請求項９の発明によれば、請求項６
の第２工程に代えて、基板の基板本体の周側面にソルダ
レジスト膜を形成し、このソルダレジスト膜に第２の耐
水部材を形成する工程を有する。このため、第２の耐水
部材によりソルダレジスト膜への水分の侵入を防止させ
ることができる。According to the invention of claim 9, claim 6
Instead of the second step, there is a step of forming a solder resist film on the peripheral side surface of the substrate main body of the substrate and forming a second water resistant member on the solder resist film. Therefore, the second water resistant member can prevent moisture from entering the solder resist film.
【図１】本発明の第１実施例に係るＢＧＡ型の半導体装
置を示す図である。FIG. 1 is a diagram showing a BGA type semiconductor device according to a first embodiment of the invention.
【図２】図１の製造工程図である。FIG. 2 is a manufacturing process diagram of FIG. 1.
【図３】本発明の第２実施例に係るＢＧＡ型の半導体装
置を示す図である。FIG. 3 is a diagram showing a BGA type semiconductor device according to a second embodiment of the invention.
【図４】図３の製造工程図である。FIG. 4 is a manufacturing process diagram of FIG. 3;
【図５】本発明の第３実施例に係るＢＧＡ型の半導体装
置を示す図である。FIG. 5 is a diagram showing a BGA type semiconductor device according to a third embodiment of the invention.
【図６】図５の製造工程図である。FIG. 6 is a manufacturing process diagram of FIG. 5;
【図７】本発明の第４実施例に係るＢＧＡ型の半導体装
置を示す図である。FIG. 7 is a diagram showing a BGA type semiconductor device according to a fourth embodiment of the present invention.
【図８】図７の製造工程図である。FIG. 8 is a manufacturing process diagram of FIG. 7;
【図９】従来のＢＧＡ型の半導体装置の断面図である。FIG. 9 is a cross-sectional view of a conventional BGA type semiconductor device.
１ バンプ ３ 半導体素子 ４ ワイヤー ５ 樹脂パッケージ １０ 基板 １１ 基板本体 １２ ソルダレジスト膜 １３ 電極パッド １４ 半導体素子用孔 １５ バンプ用孔 ２０ 基板 ２２ ソルダレジスト膜 ２３ ソルダレジスト膜 ２４ フッ素樹脂部材 ２５ 液状ソルダレジスト ２６ 平面台 ２７ 隙間 ３０ 基板 ３１ ポリイミド部材 ３２ 耐水部材 ４０ 基板 ４１ 耐水部材 ４２ 隙間 DESCRIPTION OF SYMBOLS 1 bump 3 semiconductor element 4 wire 5 resin package 10 substrate 11 substrate body 12 solder resist film 13 electrode pad 14 semiconductor element hole 15 bump hole 20 substrate 22 solder resist film 23 solder resist film 24 fluororesin member 25 liquid solder resist 26 Flat table 27 Gap 30 Substrate 31 Polyimide member 32 Water resistant member 40 Substrate 41 Water resistant member 42 Gap
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/31 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 23/31
Claims (9)
ａ）にバンプ（１）を有する基板（１０、２０、３０、
４０）と、 この基板（１０、２０、３０、４０）上に搭載され、該
バンプ（１）と電気的に接続された半導体素子（３）
と、 上記基板（１０、２０、３０、４０）上に形成され、上
記半導体素子（３）を封止する樹脂パッケージ部（５）
と、 上記基板（１０、２０、３０、４０）の基板本体（１
１）の上面（１１ｃ）および下面（１１ｄ）を被覆する
ソルダレジスト膜（１２、２２、２３）と、を備えた半
導体装置において、 上記基板本体（１１）の周側面（１１ａ）を上記バンプ
（１）より高い融点を有する耐水部材（１２、２４、３
２、４１）で被覆したことを特徴とする半導体装置。1. A lower surface (10a, 20a, 30a, 40
a) having the bumps (1) on the substrate (10, 20, 30,
40) and a semiconductor element (3) mounted on the substrate (10, 20, 30, 40) and electrically connected to the bump (1)
And a resin package part (5) formed on the substrate (10, 20, 30, 40) and encapsulating the semiconductor element (3).
And the substrate body (1) of the substrate (10, 20, 30, 40)
In a semiconductor device including a solder resist film (12, 22, 23) covering the upper surface (11c) and the lower surface (11d) of (1), the peripheral side surface (11a) of the substrate body (11) is connected to the bump ( 1) Water resistant members (12, 24, 3) having a higher melting point
2, 41) a semiconductor device characterized by being coated with.
であり、この内層に配線が形成されたことを特徴とする
半導体装置。2. A semiconductor device according to claim 1, wherein the substrate body (11) has a multi-layer structure, and wiring is formed in the inner layer.
（１２）であることを特徴とする半導体装置。3. A semiconductor device, wherein the water resistant member according to claim 1 is a solder resist film (12).
（３１）を介して基板本体（１１）の周側面（１１ａ）
に被覆されたことを特徴とする半導体装置。4. The water resistant member (32) according to claim 1, wherein a peripheral side surface (11a) of the substrate body (11) is interposed by a joining member (31).
A semiconductor device characterized by being coated on.
（１２）に第２の耐水部材（４１）を被覆したものであ
ることを特徴とする半導体装置。5. A semiconductor device, wherein the water resistant member according to claim 1 is a solder resist film (12) coated with a second water resistant member (41).
本体（１１）の上面（１１ｃ）および下面（１１ｄ）に
ソルダレジスト膜（１２、２２、２３）を形成する第１
工程と、 この基板本体（１１）の周側面（１１ａ）をバンプ
（１）より高い融点を有する耐水部材（１２、２４、３
２、４１）で被覆する第２工程と、 基板（１０、２０、３０、４０）上に半導体素子（３）
を搭載する第３工程と、 この半導体素子（３）を封止する樹脂パッケージ部
（５）を基板（１０、２０、３０、４０）上に形成する
第４工程と、 基板（１０、２０、３０、４０）の下面（１０ａ、２０
ａ、３０ａ、４０ａ）に半導体素子（３）と電気的に接
続されるバンプ（１）を形成する第５工程と、で構成し
たことを特徴とする半導体装置の製造方法。6. A first method for forming a solder resist film (12, 22, 23) on an upper surface (11c) and a lower surface (11d) of a substrate body (11) of a substrate (10, 20, 30, 40).
The process and the water resistant members (12, 24, 3) having a higher melting point than the bump (1) on the peripheral side surface (11a) of the substrate body (11).
Second step of coating with 2, 41) and semiconductor element (3) on substrate (10, 20, 30, 40)
And a fourth step of forming a resin package part (5) for sealing the semiconductor element (3) on the substrate (10, 20, 30, 40), and the substrate (10, 20, 30, 40) lower surface (10a, 20)
a step of forming bumps (1) electrically connected to the semiconductor element (3) on a, 30a, 40a), and a fifth step of manufacturing a semiconductor device.
０）の基板本体（１１）の周側面（１１ａ）にソルダレ
ジスト膜（１２）を形成する工程を有することを特徴と
する半導体装置の製造方法。7. The substrate (1) in place of the second step of claim 6,
0) A method for manufacturing a semiconductor device, which comprises the step of forming a solder resist film (12) on the peripheral side surface (11a) of the substrate body (11).
（３１）に耐水部材（３２）を形成し、基板（１０）の
基板本体（１１）の周側面（１１ａ）にこの接合部材
（３１）を形成する工程を有することを特徴とする半導
体装置の製造方法。8. A water resistant member (32) is formed on the joining member (31) instead of the second step of claim 6, and this joining is performed on the peripheral side surface (11a) of the substrate body (11) of the substrate (10). A method of manufacturing a semiconductor device, comprising the step of forming a member (31).
０）の基板本体（１１）の周側面（１１ａ）にソルダレ
ジスト膜（１２）を形成し、このソルダレジスト膜（１
２）に第２の耐水部材（４１）を形成する工程を有する
ことを特徴とする半導体装置の製造方法。9. A substrate (1) in place of the second step of claim 6.
0), a solder resist film (12) is formed on the peripheral side surface (11a) of the substrate body (11), and the solder resist film (1)
2) A method for manufacturing a semiconductor device, which comprises the step of forming a second water resistant member (41).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8193494A JPH07297313A (en) | 1994-04-20 | 1994-04-20 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8193494A JPH07297313A (en) | 1994-04-20 | 1994-04-20 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07297313A true JPH07297313A (en) | 1995-11-10 |
Family
ID=13760319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8193494A Withdrawn JPH07297313A (en) | 1994-04-20 | 1994-04-20 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07297313A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10270589A (en) * | 1997-03-25 | 1998-10-09 | Rohm Co Ltd | Structure of semiconductor device |
| KR100240525B1 (en) * | 1995-11-29 | 2000-01-15 | 가나이 쓰도무 | Semiconductor device and electronic system using the same |
| JP2007208164A (en) * | 2006-02-06 | 2007-08-16 | Shiima Denshi Kk | Substrate for semiconductor device, and its manufacturing method |
-
1994
- 1994-04-20 JP JP8193494A patent/JPH07297313A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100240525B1 (en) * | 1995-11-29 | 2000-01-15 | 가나이 쓰도무 | Semiconductor device and electronic system using the same |
| JPH10270589A (en) * | 1997-03-25 | 1998-10-09 | Rohm Co Ltd | Structure of semiconductor device |
| JP2007208164A (en) * | 2006-02-06 | 2007-08-16 | Shiima Denshi Kk | Substrate for semiconductor device, and its manufacturing method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20010703 |