JPH07288386A - Multilayer wiring board - Google Patents
Multilayer wiring boardInfo
- Publication number
- JPH07288386A JPH07288386A JP8031794A JP8031794A JPH07288386A JP H07288386 A JPH07288386 A JP H07288386A JP 8031794 A JP8031794 A JP 8031794A JP 8031794 A JP8031794 A JP 8031794A JP H07288386 A JPH07288386 A JP H07288386A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- linear expansion
- expansion coefficient
- glass cloth
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、多層配線板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board.
【０００２】[0002]
【従来の技術】電子機器の小型・高性能化に伴い、これ
に使用される電子部品の実装方法もデュアルインライン
パッケージの様に部品リードを配線板に挿入しはんだ付
けする方法から、フラットパック、チップキャリアの様
に配線板表面にはんだ付けする方法に高密度化してき
た。また、近年ワイヤーボンド法やフリップチップを用
いてＩＣチップを直接配線板上に実装する方法が採用さ
れはじめた。これら高密度実装に使用される配線板は、
技術情報協会発行「ベアチップ実装、最新技術開発と信
頼性対策」ｐ１００、図５に示される様に、高密度化す
るほどセラミックを絶縁基板とする配線板が使用されて
いる。2. Description of the Related Art With the miniaturization and high performance of electronic equipment, the mounting method of electronic parts used for this is also changed from the method of inserting the component leads into the wiring board and soldering like the dual in-line package to the flat pack, The density has been increased to the method of soldering on the surface of the wiring board like the chip carrier. Further, in recent years, a method of directly mounting an IC chip on a wiring board using a wire bond method or a flip chip has begun to be adopted. The wiring boards used for these high-density mounting are
As shown in FIG. 5, “Bare chip mounting, latest technology development and reliability countermeasures” published by Technical Information Association, wiring boards using ceramics as an insulating substrate are used as the density increases.
【０００３】[0003]
【発明が解決しようとする課題】セラミックを絶縁層と
する配線板は、高密度表面実装時の接続信頼性が高いと
いう特長がある。しかし、セラミック配線板は割れやす
いため、汎用製品としては数センチ角程度の配線板が限
界で、小さな配線板にしか適用できない問題点がある。
また、セラミック配線板はその製造において高温・長時
間の焼成を行う必要があるため、製造に多大なエネルギ
ーがかかり、導体の材料も限定されるため、結果として
コストが高くなるという課題がある。A wiring board having a ceramic as an insulating layer is characterized by high connection reliability during high-density surface mounting. However, since a ceramic wiring board is easily broken, a general-purpose product is limited to a wiring board of about several centimeters square, and there is a problem that it can be applied only to a small wiring board.
Further, since the ceramic wiring board needs to be fired at a high temperature for a long time in the production thereof, a large amount of energy is required for the production, and the material of the conductor is limited, resulting in a problem that the cost becomes high.
【０００４】本発明は、配線密度に優れ、かつ経済的な
多層配線板を提供することを目的とするものである。An object of the present invention is to provide an economical multilayer wiring board having excellent wiring density.
【０００５】[0005]
【課題を解決するための手段】本発明の多層配線板は、
複数層の導体回路層が絶縁層を介して積層接着され、所
定の導体回路層間を導体化された穴で電気的に接続して
なる多層配線板において、Ｘ及びＹ方向の線膨張率が１
３ｐｐｍ／℃以下のガラスクロス補強樹脂製の絶縁層を
１層以上有することを特徴とする。The multilayer wiring board of the present invention comprises:
In a multilayer wiring board in which a plurality of conductor circuit layers are laminated and adhered via an insulating layer, and predetermined conductor circuit layers are electrically connected to each other by holes made into a conductor, a linear expansion coefficient in the X and Y directions is 1
It is characterized by having at least one insulating layer made of a glass cloth reinforcing resin of 3 ppm / ° C. or less.
【０００６】本発明の導体回路層１は、２層以上必要
で、高密度化を達成するためには図１に例示する様に、
３層またはこれ以上が望ましい。導体回路層１は既存の
銅箔をエッチング法で回路形成したもの等、任意のもの
が使用できる。The conductor circuit layer 1 of the present invention requires two or more layers, and in order to achieve high density, as illustrated in FIG.
Three layers or more are desirable. As the conductor circuit layer 1, any one can be used, such as one in which a circuit is formed from an existing copper foil by an etching method.
【０００７】複数の導体回路層は絶縁層２で絶縁され、
この絶縁層の少なくとも１層には配線板の平面方向とな
るＸ及びＹ方向の線膨張率が室温付近で１３ｐｐｍ／℃
以下のガラスクロス補強された樹脂製の絶縁層２ａを使
用する必要がある。この特性を有する絶縁層は、厚いほ
ど良く、配線板総厚の１／２以上であることが特に好ま
しい。この絶縁層の厚み方向となるＺ方向の線膨張率
は、配線板自身の信頼性を確保するため低いほど良い
が、１３ｐｐｍ／℃以下である必要は無い。The plurality of conductor circuit layers are insulated by the insulating layer 2,
At least one of these insulating layers has a linear expansion coefficient in the X and Y directions, which is the plane direction of the wiring board, of 13 ppm / ° C. near room temperature.
It is necessary to use the following glass cloth-reinforced resin insulating layer 2a. The thicker the insulating layer having this characteristic is, the more preferable it is, and it is particularly preferable that the insulating layer has a thickness of ½ or more of the total thickness of the wiring board. The coefficient of linear expansion in the Z direction, which is the thickness direction of the insulating layer, is better as it is lower in order to secure the reliability of the wiring board itself, but it does not need to be 13 ppm / ° C. or less.
【０００８】複数層の配線層を電気的に接続するため、
導体化された穴３が必要である。この穴は図１−３に例
示した様な配線板を貫通する穴とこの穴内に銅めっき４
を施したスルーホールでも良く、導体化された非貫通ホ
ールでも良い。In order to electrically connect a plurality of wiring layers,
Conducted holes 3 are required. This hole is a hole that penetrates the wiring board as illustrated in Fig. 1-3 and copper plating 4
It may be a through hole provided with or a non-through hole made into a conductor.
【０００９】本発明の多層配線板は、図１に例示する様
に、最外層となる絶縁層２ｂにガラスクロスを含有しな
い樹脂フィルムを用いることが特に好ましい。この樹脂
フィルムはエポキシ樹脂、フェノール樹脂、ポリイミド
樹脂やこれらの混合物、供重合物等が使用できる。In the multilayer wiring board of the present invention, as illustrated in FIG. 1, it is particularly preferable to use a resin film containing no glass cloth as the outermost insulating layer 2b. For this resin film, an epoxy resin, a phenol resin, a polyimide resin, a mixture thereof, a copolymer, or the like can be used.
【００１０】[0010]
【作用】一般のガラスエポキシ基材（ＦＲ−４材）は
Ｘ，Ｙ方向の線膨張率が１６ｐｐｍ／℃であるのに比較
し、本発明の配線板は、線膨張率が１３ｐｐｍ／℃以下
の絶縁層を用いるため、配線板全体の線膨張率を所定量
以下にコントロールすることができる。。さらに、最外
層の絶縁層に樹脂フィルムを用いた場合、一般にフィル
ムはヤング率が低く柔軟であることと、厚みが薄いた
め、配線板全体の線膨張率を増加させない効果がある。In comparison with the general glass epoxy base material (FR-4 material) having a linear expansion coefficient of 16 ppm / ° C in the X and Y directions, the wiring board of the present invention has a linear expansion coefficient of 13 ppm / ° C or less. Since the insulating layer is used, the coefficient of linear expansion of the entire wiring board can be controlled to a predetermined amount or less. . Furthermore, when a resin film is used for the outermost insulating layer, the film generally has a low Young's modulus and is flexible, and since the film is thin, it has an effect of not increasing the linear expansion coefficient of the entire wiring board.
【００１１】[0011]
実施例１ Ｘ，Ｙ方向の線膨張率が１１ｐｐｍの、ガラスクロス・
エポキシ樹脂両面銅張り積層板であるＭＣＬ−Ｅ−６７
９ＬＤ（日立化成工業株式会社製、商品名）の表面銅箔
を既存のエッチング法で回路加工し、内層導体回路を形
成した。次いで、その表面に、ガラスクロス・エポキシ
プリプレグであるＧＥＡ−６７９（日立化成工業株式会
社製、商品名）と、銅箔とを重ね、１７０℃、４０ｋｇ
／ｃｍ2、６０分プレス積層し多層化した。次いで、ド
リル穴あけ機で貫通穴を形成し、穴内に銅めっきを施し
た後、既存のエッチング法で外層導体回路を形成し本発
明の多層配線板を得た。Example 1 A glass cloth having a linear expansion coefficient of 11 ppm in the X and Y directions.
Epoxy resin double-sided copper clad laminate MCL-E-67
A surface copper foil of 9LD (trade name, manufactured by Hitachi Chemical Co., Ltd.) was processed into a circuit by an existing etching method to form an inner conductor circuit. Next, GEA-679 (manufactured by Hitachi Chemical Co., Ltd.), which is a glass cloth / epoxy prepreg, and a copper foil are laminated on the surface thereof, and 170 ° C., 40 kg
/ Cm 2 , 60-minute press lamination to form a multilayer. Next, a through hole was formed by a drill hole puncher, copper was plated in the hole, and then an outer conductor circuit was formed by an existing etching method to obtain a multilayer wiring board of the present invention.
【００１２】実施例２ 実施例１のＧＥＡ−６７９（日立化成工業株式会社製、
商品名）に変えて、エポキシ接着フィルムであるＡＳ−
３０００（日立化成工業株式会社製、商品名）を使用
し、実施例１と同じ方法で本発明の多層配線板を得た。Example 2 GEA-679 of Example 1 (manufactured by Hitachi Chemical Co., Ltd.,
AS-, which is an epoxy adhesive film, instead of the product name)
Using 3000 (manufactured by Hitachi Chemical Co., Ltd., trade name), the multilayer wiring board of the present invention was obtained in the same manner as in Example 1.
【００１３】実施例３ 実施例２の、ＭＣＬ−Ｅ−６７９ＬＤ（日立化成工業株
式会社製、商品名）に変えて、Ｘ，Ｙ方向の線膨張率
が、８ｐｐｍのガラスクロス・エポキシ樹脂・セラミッ
ク両面銅張り積層板であるＭＣＬ−ＣＥ−６７（日立化
成工業株式会社製、商品名）を使用し、実施例２と同じ
方法で本発明の多層配線板を得た。Example 3 A glass cloth / epoxy resin / ceramic having a linear expansion coefficient of 8 ppm in the X and Y directions was used instead of the MCL-E-679LD (trade name, manufactured by Hitachi Chemical Co., Ltd.) of Example 2. Using MCL-CE-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a double-sided copper-clad laminate, the multilayer wiring board of the present invention was obtained in the same manner as in Example 2.
【００１４】比較例１ 絶縁材料に、アルミナセラミックスを用い、層間の絶縁
にもアルミナセラミックスを用い、回路は実施例１と同
じ回路を形成し、多層配線板を得た。Comparative Example 1 Alumina ceramics was used as an insulating material, and alumina ceramics was also used for insulation between layers, and the same circuit as in Example 1 was formed to obtain a multilayer wiring board.
【００１５】比較例２ 実施例１において、ガラスクロス・エポキシ樹脂両面銅
張り積層板であるＭＣＬ−Ｅ−６７９ＬＤ（日立化成工
業株式会社製、商品名）に代えて、Ｘ，Ｙ方向の線膨張
率が、１６ｐｐｍのガラスクロス・エポキシ樹脂両面銅
張り積層板であるＭＣＬ−Ｅ−６７（日立化成工業株式
会社製、商品名）を用い、ガラスクロス・エポキシプリ
プレグであるＧＥＡ−６７９（日立化成工業株式会社
製、商品名）に代えて、ＧＥＡ−６７Ｎ（日立化成工業
株式会社製、商品名）を用いた他は、実施例１と同様に
して、多層配線板を得た。Comparative Example 2 Instead of MCL-E-679LD (Hitachi Chemical Co., Ltd., trade name), which is a glass cloth / epoxy resin double-sided copper-clad laminate in Example 1, linear expansion in the X and Y directions is performed. Using a glass cloth / epoxy resin double-sided copper clad laminate MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a rate of 16 ppm, a glass cloth / epoxy prepreg GEA-679 (Hitachi Chemical Co., Ltd.) A multilayer wiring board was obtained in the same manner as in Example 1 except that GEA-67N (manufactured by Hitachi Chemical Co., Ltd., trade name) was used in place of the product name, manufactured by Co., Ltd.
【００１６】このようにして作成した配線板の接続信頼
性を、表面実装部品を配線板表面にはんだで実装し、
（−５５℃、１０分）／（１２５℃、１０分）の条件で
繰返して熱衝撃テストを行った。この結果を、断線しな
い状態を、２０００回保てれば◎、１０００回まで保て
れば○、５００回まで保てれば△、５００回まで保てな
ければ×と評価した。この評価結果を表１に示す。ま
た、使用した絶縁剤量の線膨張率を併記する。With respect to the connection reliability of the wiring board thus created, the surface mounting component is mounted on the surface of the wiring board by soldering,
The thermal shock test was repeated under the condition of (-55 ° C, 10 minutes) / (125 ° C, 10 minutes). The results were evaluated as ∘ if the state of no breakage can be kept 2000 times, ◯ if it can be kept up to 1000 times, Δ if it can be kept up to 500 times, and x if it cannot be kept up to 500 times. The evaluation results are shown in Table 1. In addition, the linear expansion coefficient of the amount of insulating agent used is also shown.
【００１７】[0017]
【表１】 接続信頼性：表面実装部品を配線板表面にはんだで実装
し −５５℃、１０分←→１２５℃、１０分に熱衝撃テスト
を行った。 ◎：2000回ＯＫ ○：1000回ＯＫ △： 500回ＯＫ
×： 500回ＮＧ[Table 1] Connection reliability: A surface mount component was mounted on the surface of a wiring board with solder, and a thermal shock test was conducted at -55 ° C, 10 minutes ← → 125 ° C, 10 minutes. ◎: 2000 times OK ○: 1000 times OK △: 500 times OK
×: NG 500 times
【００１８】[0018]
【発明の効果】以上に説明したように、本発明によっ
て、配線密度に優れ、かつ経済的な多層配線板を提供す
ることができる。As described above, according to the present invention, it is possible to provide an economical multilayer wiring board having excellent wiring density.
【図１】本発明の一実施例を示す多層配線板の断面図で
ある。FIG. 1 is a cross-sectional view of a multilayer wiring board showing an embodiment of the present invention.
【図２】本発明の別の実施例を示す多層配線板の断面図
である。FIG. 2 is a sectional view of a multilayer wiring board showing another embodiment of the present invention.
１．導体回路層 ２，２ａ，２ｂ．絶縁層 ３．スルーホール ４．銅めっき ５．表面実装部品 1. Conductor circuit layer 2, 2a, 2b. Insulation layer 3. Through hole 4. Copper plating 5. Surface mount components
フロントページの続き (72)発明者 山岸 一次 茨城県下館市大字小川1500番地 日立化成 工業株式会社下館工場内 (72)発明者 田村 義広 茨城県下館市大字小川1500番地 日立化成 工業株式会社下館工場内 (72)発明者 河田 健一 茨城県下館市大字小川1500番地 日立化成 工業株式会社下館工場内Front page continuation (72) Inventor Kazushi Yamagishi 1500 Ogawa, Shimodate-shi, Ibaraki Hitachi Chemical Co., Ltd. Shimodate factory (72) Inventor Yoshihiro Tamura 1500, Ogawa, Shimodate-shi, Ibaraki Hitachi Chemical Co., Ltd. Shimodate factory (72) Inventor Kenichi Kawada 1500 Ogawa, Shimodate City, Ibaraki Prefecture Hitachi Chemical Co., Ltd. Shimodate Factory
Claims (2)
接着され、所定の導体回路層間を導体化された穴で電気
的に接続してなる多層配線板において、Ｘ及びＹ方向の
線膨張率が１３ｐｐｍ／℃以下のガラスクロス補強樹脂
製の絶縁層を１層以上有することを特徴とする多層配線
板。1. A multi-layer wiring board in which a plurality of conductor circuit layers are laminated and adhered via an insulating layer, and predetermined conductor circuit layers are electrically connected to each other by a hole made into a conductor, in the X and Y directions. A multilayer wiring board having one or more insulating layers made of a glass cloth reinforcing resin having a linear expansion coefficient of 13 ppm / ° C. or less.
ない樹脂フィルムであることを特徴とする請求項１記載
の多層配線板。2. The multilayer wiring board according to claim 1, wherein the outermost layer of the insulating layer is a resin film containing no glass cloth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8031794A JPH07288386A (en) | 1994-04-19 | 1994-04-19 | Multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8031794A JPH07288386A (en) | 1994-04-19 | 1994-04-19 | Multilayer wiring board |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004005721A Division JP2004112001A (en) | 2004-01-13 | 2004-01-13 | Multilayer wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07288386A true JPH07288386A (en) | 1995-10-31 |
Family
ID=13714888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8031794A Pending JPH07288386A (en) | 1994-04-19 | 1994-04-19 | Multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07288386A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7415761B2 (en) | 1998-09-03 | 2008-08-26 | Ibiden Co., Ltd. | Method of manufacturing multilayered circuit board |
| JP2009206326A (en) * | 2008-02-28 | 2009-09-10 | Sumitomo Bakelite Co Ltd | Multi-layer printed wiring board and semiconductor device |
-
1994
- 1994-04-19 JP JP8031794A patent/JPH07288386A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7415761B2 (en) | 1998-09-03 | 2008-08-26 | Ibiden Co., Ltd. | Method of manufacturing multilayered circuit board |
| US7832098B2 (en) | 1998-09-03 | 2010-11-16 | Ibiden Co., Ltd. | Method of manufacturing a multilayered printed circuit board |
| US8148643B2 (en) | 1998-09-03 | 2012-04-03 | Ibiden Co., Ltd. | Multilayered printed circuit board and manufacturing method thereof |
| JP2009206326A (en) * | 2008-02-28 | 2009-09-10 | Sumitomo Bakelite Co Ltd | Multi-layer printed wiring board and semiconductor device |
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