JPH07283340A - Package for mounting semiconductor chip and semiconductor device with package - Google Patents
Package for mounting semiconductor chip and semiconductor device with packageInfo
- Publication number
- JPH07283340A JPH07283340A JP6070506A JP7050694A JPH07283340A JP H07283340 A JPH07283340 A JP H07283340A JP 6070506 A JP6070506 A JP 6070506A JP 7050694 A JP7050694 A JP 7050694A JP H07283340 A JPH07283340 A JP H07283340A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor chip
- line
- signal
- transmission line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップ実装用パ
ッケージ及び半導体装置に関し、特に、ＬＳＩ用パッケ
ージ及びそれを有する半導体装置に適用して有効な技術
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting package and a semiconductor device, and more particularly to a technique effective when applied to an LSI package and a semiconductor device having the same.
【０００２】[0002]
【従来の技術】従来の半導体チップ実装用パッケージ
は、信号数が少ない半導体装置の場合は、特願平０４−
３１３１８８号に開示されているように信号用の伝送線
路のすべてをパッケージの表層に設けていた。2. Description of the Related Art A conventional semiconductor chip mounting package is disclosed in Japanese Patent Application No. 04-
All the signal transmission lines were provided on the surface layer of the package as disclosed in No. 313188.
【０００３】一方、ＣＰＵなどのように多数の信号を扱
う半導体装置の場合は、すべての信号をパッケージの外
周から取ることは不可能であるため、通常はピングリッ
ドアレイ（ＰＧＡ）と呼ばれるパッケージの裏面からア
レイ状にピンを並べ、内層にて信号配線を行った多層パ
ッケージが用いられていた。On the other hand, in the case of a semiconductor device that handles a large number of signals, such as a CPU, it is impossible to take all the signals from the outer periphery of the package, so that a package called a pin grid array (PGA) is usually used. A multilayer package has been used in which pins are arranged in an array from the back surface and signal wiring is performed in the inner layer.
【０００４】半導体チップ実装用パッケージは、半導体
装置、情報処理、伝送分野を始め多くの分野で使われて
いるが、その処理速度は高速化の一途を成して特に近
年、高速ディジタル伝送分野ではその伝送速度が１Ｇｂ
／ｓをはるかに越え、１０Ｇｂ／ｓの伝送速度を持つ伝
送装置も実用化されようとしいる。The semiconductor chip mounting package is used in many fields including the semiconductor device, information processing, and transmission fields, and its processing speed has been accelerating, especially in recent years in the high-speed digital transmission field. The transmission speed is 1 Gb
/ S, which is much higher than 10 Gbps, is being put to practical use.
【０００５】また、情報処理の分野においても、ＣＰＵ
のクロック周波数は数１００ＭＨｚに達しており、この
ような状況下では、伝送線の自己インダクタンス及び線
間インダクタンス、対地容量及び線間容量を無視できな
くなり、この高速の伝送速度を持つ信号を半導体装置が
扱うためには、その伝送線上で電圧波、電流波の反射が
起こらないようにインピーダンスを整合する必要があ
る。Also in the field of information processing, the CPU
Has reached a frequency of several hundred MHz, and under such circumstances, the self-inductance and line-to-line inductance of the transmission line, the ground capacitance and the line-to-line capacitance cannot be ignored, and a signal having this high transmission speed is transmitted to the semiconductor device. In order to handle, the impedance must be matched so that the reflection of voltage wave and current wave does not occur on the transmission line.
【０００６】[0006]
【発明が解決しようとする課題】本発明者は、上記従来
技術を検討した結果、以下の問題点を見いだした。DISCLOSURE OF THE INVENTION The present inventors have found the following problems as a result of examining the above prior art.
【０００７】従来のＰＧＡパッケージにおいては、信号
線のインピーダンス整合を無視できるクロック周波数１
ＧＨｚ以下を対象に用いられていたため、１ＧＨｚを超
えるような超高速信号には適用できないという問題点が
あった。In the conventional PGA package, the clock frequency 1 in which the impedance matching of the signal line can be ignored
Since it was used for GHz or less, there was a problem that it could not be applied to ultra-high speed signals exceeding 1 GHz.
【０００８】本発明の目的は、周波数１ＧＨｚを超える
ような超高速信号に適用可能な半導体チップ実装用パッ
ケージを提供することにある。An object of the present invention is to provide a semiconductor chip mounting package applicable to an ultra high speed signal having a frequency exceeding 1 GHz.
【０００９】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１０】[0010]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.
【００１１】パッケージ内に該半導体チップの回路形成
面に対して垂直方向に該接地用、電源用及び信号線用の
伝送線路を設け、該接地用や電源用の伝送線路は前記信
号線用の伝送線路の周りを取り囲む位置に設ける。The grounding, power supply and signal line transmission lines are provided in the package in a direction perpendicular to the circuit forming surface of the semiconductor chip, and the grounding and power supply transmission lines are for the signal lines. It is provided at a position surrounding the transmission line.
【００１２】[0012]
【作用】上述した手段によれば、パッケージ内に該半導
体チップの回路形成面に対して垂直方向に該接地用、電
源用及び信号線用の伝送線路を設け、該接地用や電源用
の伝送線路は前記信号線用の伝送線路の周りを取り囲む
位置に設けることにより、その信号線用伝送線路と接用
地や電源用の伝送線路間の距離を調整し、両者の線路間
容量を制御することにより、信号線用伝送線路に所定の
特性インピーダンスを持たせることができ、伝送線路上
で電圧波、電流波の反射が起こらないようにインピーダ
ンスを整合することができるので、周波数１ＧＨｚを超
えるような超高速信号に適用可能となる。According to the above-mentioned means, the grounding, power supply and signal line transmission lines are provided in the package in the direction perpendicular to the circuit forming surface of the semiconductor chip, and the grounding and power supply transmissions are performed. By providing the line at a position surrounding the transmission line for the signal line, the distance between the transmission line for the signal line and the transmission line for the contact point or the power supply is adjusted to control the capacitance between the lines. As a result, the signal line transmission line can have a predetermined characteristic impedance, and the impedance can be matched so that the reflection of the voltage wave and the current wave does not occur on the transmission line. It can be applied to ultra high speed signals.
【００１３】以下、本発明の構成について、実施例とと
もに説明する。The structure of the present invention will be described below together with embodiments.
【００１４】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００１５】[0015]
【実施例】図１は、本発明の一実施例である半導体チッ
プ実装用パッケージについて説明するためのものであ
り、本実施例ではベアチップ型のパッケージで示してあ
る。1 is a view for explaining a semiconductor chip mounting package according to an embodiment of the present invention. In this embodiment, a bare chip type package is shown.
【００１６】図１（ａ）は本実施例パッケージの半導体
チップ実装面を上から示した平面図であり、図１（ｂ）
は図１（ａ）のＡ−Ａ線で切ったパッケージの断面図を
それぞれ示す。FIG. 1A is a plan view showing the semiconductor chip mounting surface of the package of this embodiment from above, and FIG.
Shows a cross-sectional view of the package taken along the line AA in FIG.
【００１７】図１において、１０１は信号線用伝送線路
である信号線、１０２は接地用や電源用伝送線路である
接地・電源線、１０３はセラミック基板（パッケー
ジ）、１０４は接続ピン、Ｌはパッケージ厚をそれぞれ
示してある。In FIG. 1, 101 is a signal line that is a signal line transmission line, 102 is a ground / power line that is a ground or power transmission line, 103 is a ceramic substrate (package), 104 is a connection pin, and L is L. The package thickness is shown respectively.
【００１８】図１（ａ）に示すように、セラミック基板
１０３に信号線１０１を設け、その信号線１０１を中心
とした６角形の頂点に接地・電源線１０２を設けてあ
る。As shown in FIG. 1A, a signal line 101 is provided on a ceramic substrate 103, and a ground / power supply line 102 is provided at the apex of a hexagon centered on the signal line 101.
【００１９】また、前述のそれぞれの線路は、図１
（ｂ）に示すように、セラミック基板１０３内に形成さ
れたビアホールで構成されており、セラミック基板（パ
ッケージ）１０３裏面にはそれぞれの線路に対して他の
回路基板等と接続する接続ピン１０４が取りけられてい
る。Further, the above-mentioned respective lines are shown in FIG.
As shown in (b), the ceramic substrate (package) 103 is formed of via holes formed in the ceramic substrate 103. On the back surface of the ceramic substrate (package) 103, there are connection pins 104 for connecting to other circuit boards or the like for the respective lines. It has been taken away.
【００２０】本実施例のパッケージにおいて、図１
（ａ）に示すように、セラミックの比誘電率を１０、ビ
アホール直径を０．１ｍｍ、各線間距離を１．４ｍｍと
すれば、信号の伝送インピーダンスはほぼ５０Ωとな
る。このインピーダンスは、基板の比誘電率、ビアホー
ル直径、各線間距離等により、信号線のインダクタンス
及びＧＮＤとの容量を制御することにより、決定される
ものであり、図示しない実装基板との接続を考慮に入れ
て所望のインピーダンス値に設定する。In the package of this embodiment, FIG.
As shown in (a), when the relative permittivity of the ceramic is 10, the diameter of the via hole is 0.1 mm, and the distance between the wires is 1.4 mm, the signal transmission impedance is about 50Ω. This impedance is determined by controlling the inductance of the signal line and the capacitance with the GND according to the relative permittivity of the substrate, the diameter of the via hole, the distance between each line, etc., and the connection with the mounting substrate (not shown) is considered. And set to the desired impedance value.
【００２１】次に、本実施例のパッケージにおいて、パ
ッケージ厚Ｌ＝８ｍｍ、５０Ω規格化時のシミュレーシ
ョン結果を図２に示す。Next, FIG. 2 shows a simulation result when the package thickness L = 8 mm and the standardization of 50Ω in the package of this embodiment.
【００２２】図２は、横軸に周波数（ＧＨｚ)、縦軸に
ＶＳＷＲとＳ２１をとったグラフであり、ＶＳＷＲは本
実施例のパッケージに形成された伝送線路において、入
力電圧がどれくらい反射しているか示した電圧定在波比
であり、Ｓ２１は入力電圧に対して出力電圧がどれくら
い損失（ｄＢ）したかを示してある。FIG. 2 is a graph in which the horizontal axis represents frequency (GHz) and the vertical axis represents VSWR and S21. VSWR shows how much the input voltage is reflected in the transmission line formed in the package of this embodiment. S21 indicates how much the output voltage has lost (dB) with respect to the input voltage.
【００２３】前述のＶＳＷＲ（電圧定在波比）は、図２
の実線で示したものであり、伝送線路の電圧の透過係数
によって求められるもので、値が１に近づくほど入力電
圧は反射されず、入力波形が劣化したり、なまったりす
ることなく、そのままの形で伝送されることを示す。The above-mentioned VSWR (voltage standing wave ratio) is shown in FIG.
Of the transmission line, the input voltage is not reflected as the value approaches 1, and the input waveform is not deteriorated or blunted, It is transmitted in the form.
【００２４】本実施例のパッケージに形成された伝送線
路は、周波数１〜１０ＧＨｚにおいて、ＶＳＷＲの値は
１〜２付近であり、高周波数においてもほとんど反射さ
れずに入力波形がそのままの形で伝送されるとがわか
る。The transmission line formed in the package of this embodiment has a VSWR value of around 1 to 2 at a frequency of 1 to 10 GHz, and the input waveform is transmitted as it is with almost no reflection even at high frequencies. I understand that it will be done.
【００２５】また、Ｓ２１（損失）は、図２の破線で示
したものであり、入力に対する出力の割合を常用対数に
とって求めたもので、０ｄＢに近づくほど損失がないこ
とを示す。Further, S21 (loss) is shown by a broken line in FIG. 2, and is obtained by using the logarithm of the ratio of the output to the input, and indicates that there is no loss as it approaches 0 dB.
【００２６】本実施例のパッケージに形成された伝送線
路は、周波数１〜１０ＧＨｚにおいて、ー１ｄＢ（１０
％）以下の損失であり、高周波数においてもほとんど損
失しないことがわかる。The transmission line formed in the package of this embodiment has a frequency of 1 to 10 GHz and a level of -1 dB (10
%) Or less, and it can be seen that there is almost no loss even at high frequencies.
【００２７】したがって、パッケージ内に該半導体チッ
プの回路形成面に対して垂直方向に該接地用、電源用及
び信号線用の伝送線路を設け、該接地用や電源用の伝送
線路は前記信号線用の伝送線路の周りを取り囲む位置に
設けることにより、その信号線用伝送線路と接用地や電
源用の伝送線路間の距離を調整し、両者の線路間容量を
制御することにより、信号線用伝送線路に所定の特性イ
ンピーダンスを持たせることができ、伝送線路上で電圧
波、電流波の反射が起こらないようにインピーダンスを
整合することができるので、周波数１ＧＨｚを超えるよ
うな超高速信号に適用可能となる。Therefore, the grounding, power supply and signal line transmission lines are provided in the package in a direction perpendicular to the circuit forming surface of the semiconductor chip, and the grounding and power supply transmission lines are the signal lines. By arranging in the position surrounding the transmission line for the signal line, the distance between the transmission line for the signal line and the transmission line for the ground or the power source is adjusted, and the capacitance between the lines is controlled to control the signal line. Since the transmission line can have a predetermined characteristic impedance and the impedance can be matched so that the reflection of voltage waves and current waves does not occur on the transmission line, it is applied to ultra-high-speed signals with a frequency exceeding 1 GHz. It will be possible.
【００２８】また、複数本の信号線間をＧＮＤピンで取
り囲んでいるので、信号間のアイソレーションが図れ
る。Since a plurality of signal lines are surrounded by GND pins, isolation between signals can be achieved.
【００２９】次に、本発明の他の実施例について説明す
る。Next, another embodiment of the present invention will be described.
【００３０】図３は、上記説明した伝送線路に、ストリ
ップ線を組み合わせた半導体チップ実装用パッケージの
例を示したものである。FIG. 3 shows an example of a semiconductor chip mounting package in which a strip line is combined with the above-described transmission line.
【００３１】図３において、３０１は半導体チップを、
３０２は実装用の半田バンプ、３０３はストリップ線、
３０４は接地層をそれぞれ示す。In FIG. 3, reference numeral 301 denotes a semiconductor chip,
302 is a solder bump for mounting, 303 is a strip line,
Reference numerals 304 respectively indicate ground layers.
【００３２】図３に示すように、半導体チップ実装用パ
ッケージに、接地層３０４に挟まれたチッ化アルミ、ア
ルミナ等からなるストッリプ線（マイクロストリップ
線）３０３を介在させた信号用伝送線路１０１を設ける
ことにより、前述した半導体チップ実装用パッケージと
同様に、周波数１ＧＨｚを超えるような超高速信号に適
用可能であり、かつ、ストリップ線上の任意の位置に接
続ピン１０４に繋がる信号用伝送線路を設けることがで
き、パッケージサイズは半導体チップサイズに依存しな
いで設計することが可能となる。As shown in FIG. 3, a signal transmission line 101 in which a strip line (microstrip line) 303 made of aluminum nitride, alumina or the like sandwiched between ground layers 304 is interposed in a package for mounting a semiconductor chip. By providing the signal, like the above-described package for mounting a semiconductor chip, it can be applied to an ultra-high-speed signal with a frequency exceeding 1 GHz, and a signal transmission line connected to the connection pin 104 is provided at an arbitrary position on the strip line. Therefore, the package size can be designed without depending on the semiconductor chip size.
【００３３】ここでのストリップ線は、マイクロストリ
ップ線を設けたが、使用周波数や応用回路等により、コ
プレーナ線、スロット線等を設けてもかまわない。The strip line here is a microstrip line, but a coplanar line, a slot line, or the like may be provided depending on the frequency used and the application circuit.
【００３４】なお、前述した本発明の半導体チップ実装
用パッケージは、接地・電源用伝送線路の配置は６角形
に限らず、４角形、８角形等、多種考えられることはい
うまでもない。In the package for mounting a semiconductor chip of the present invention described above, it goes without saying that the arrangement of the ground / power transmission lines is not limited to hexagonal, and various types such as quadrangular and octagonal can be considered.
【００３５】また、本実施例の半導体チップ実装用パッ
ケージは、ベアチップ型の場合のみを取り挙げて説明し
てきたが、樹脂やキャップ等で半導体チップが封止され
ている場合にも適用でき、かつ、誘電体の材質、寸法に
ついても、本実施例に示したもの以外に多種考えられる
ことはいうまでもない。Although the semiconductor chip mounting package of this embodiment has been described by taking only the bare chip type package, it can be applied to the case where the semiconductor chip is sealed with resin or a cap, and It goes without saying that various kinds of dielectric materials and dimensions other than those shown in this embodiment can be considered.
【００３６】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the inventions made by the present inventor are
Although the specific description has been given based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００３７】[0037]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００３８】信号線用伝送線路と接用地や電源用の伝送
線路間の距離を調整し、両者の線路間容量を制御するこ
とにより、信号線用伝送線路に所定の特性インピーダン
スを持たせることができ、伝送線路上で電圧波、電流波
の反射が起こらないようにインピーダンスを整合するこ
とができるので、周波数１ＧＨｚを超えるような超高速
信号に適用可能となる。By adjusting the distance between the transmission line for the signal line and the transmission line for the ground or the power supply and controlling the capacitance between both lines, the transmission line for the signal line can have a predetermined characteristic impedance. Since the impedance can be matched so that the voltage wave and the current wave are not reflected on the transmission line, it can be applied to an ultrahigh-speed signal having a frequency exceeding 1 GHz.
【００３９】また、複数本の信号線間をＧＮＤピンで取
り囲んでいるので、信号間のアイソレーションが図れ
る。Further, since a plurality of signal lines are surrounded by GND pins, isolation between signals can be achieved.
【００４０】さらに、半導体チップ実装用パッケージ
に、接地層に挟まれたストッリプ線を介在させた信号用
伝送線路１０１を設けることにより、ストリップ線上の
任意の位置に接続ピン１０４に繋がる信号用伝送線路を
設けることができ、パッケージサイズは半導体チップサ
イズに依存しないで設計することが可能となる。Further, the package for mounting a semiconductor chip is provided with the signal transmission line 101 with the strip line sandwiched between the ground layers interposed, so that the signal transmission line connected to the connection pin 104 at an arbitrary position on the strip line. Can be provided, and the package size can be designed without depending on the semiconductor chip size.
【図１】本発明の一実施例である半導体チップ実装用パ
ッケージを説明するための図である。FIG. 1 is a diagram for explaining a semiconductor chip mounting package that is an embodiment of the present invention.
【図２】本実施例の半導体チップ実装用パッケージのシ
ミュレーション結果を示したグラフである。FIG. 2 is a graph showing a simulation result of the semiconductor chip mounting package of this embodiment.
【図３】本発明の他の実施例である半導体チップ実装用
パッケージを説明するための図である。FIG. 3 is a diagram for explaining a semiconductor chip mounting package that is another embodiment of the present invention.
１０１…信号線用伝送線路である信号線、１０２…接地
用や電源用伝送線路である接地・電源線、１０３…セラ
ミック基板（パッケージ）、１０４…接続ピン、Ｌ…パ
ッケージ厚、３０１…半導体チップを、３０２…実装用
の半田バンプ、３０３…ストリップ線、３０４…接地
層。101 ... Signal line which is transmission line for signal line, 102 ... Grounding / power supply line which is transmission line for grounding and power supply, 103 ... Ceramic substrate (package), 104 ... Connection pin, L ... Package thickness, 301 ... Semiconductor chip 302 ... Solder bumps for mounting, 303 ... Strip lines, 304 ... Ground layer.
Claims (3)
を有し、素子形成面を下にした半導体チップを実装する
半導体チップ実装用パッケージであって、 前記パッケージ内に該半導体チップの回路形成面に対し
て垂直方向に該接地用、電源用及び信号線用の伝送線路
を設け、該接地用や電源用の伝送線路は前記信号線用の
伝送線路の周りを取り囲む位置に設けたことを特徴とす
る半導体チップ実装用パッケージ。1. A semiconductor chip mounting package having a grounding, power supply and signal line transmission line, and mounting a semiconductor chip with an element formation surface facing down, wherein the semiconductor chip is mounted in the package. The grounding, power supply, and signal line transmission lines are provided in a direction perpendicular to the circuit formation surface, and the grounding and power supply transmission lines are provided at positions surrounding the signal line transmission line. A package for mounting a semiconductor chip, characterized in that
ッケージであって、 前記伝送線路は、ビアホールもしくはビアポールと、ス
トリップ線との組み合わせで構成されていることを特徴
とする半導体チップ用パッケージ。2. The semiconductor chip package according to claim 1, wherein the transmission line is configured by a combination of a via hole or via pole and a strip line.
側に向けて半導体チップ実装用パッケージにボンディン
グされたフリップチップボンディング型の半導体装置で
あって、 該半導体チップの回路形成面に対して垂直方向に信号
用、接地用及び電源用伝送線路を前記パッケージ内に設
け、該接地用や電源用伝送経路を該信号用伝送線路の周
りを取り囲む位置に配したことを特徴とする半導体装
置。3. A flip chip bonding type semiconductor device in which an element forming surface of a semiconductor chip faces a package side and is bonded to a semiconductor chip mounting package in a direction perpendicular to a circuit forming surface of the semiconductor chip. A semiconductor device, wherein signal, ground, and power transmission lines are provided in the package, and the ground and power transmission paths are arranged at positions surrounding the signal transmission line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6070506A JPH07283340A (en) | 1994-04-08 | 1994-04-08 | Package for mounting semiconductor chip and semiconductor device with package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6070506A JPH07283340A (en) | 1994-04-08 | 1994-04-08 | Package for mounting semiconductor chip and semiconductor device with package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07283340A true JPH07283340A (en) | 1995-10-27 |
Family
ID=13433492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6070506A Pending JPH07283340A (en) | 1994-04-08 | 1994-04-08 | Package for mounting semiconductor chip and semiconductor device with package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07283340A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7164592B2 (en) | 2004-05-24 | 2007-01-16 | Renesas Technology Corp. | Semiconductor device |
| JP2008047773A (en) * | 2006-08-18 | 2008-02-28 | National Institute Of Advanced Industrial & Technology | Semiconductor device |
| JP4605930B2 (en) * | 2001-03-29 | 2011-01-05 | 京セラ株式会社 | High frequency semiconductor device storage package |
-
1994
- 1994-04-08 JP JP6070506A patent/JPH07283340A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4605930B2 (en) * | 2001-03-29 | 2011-01-05 | 京セラ株式会社 | High frequency semiconductor device storage package |
| US7164592B2 (en) | 2004-05-24 | 2007-01-16 | Renesas Technology Corp. | Semiconductor device |
| JP2008047773A (en) * | 2006-08-18 | 2008-02-28 | National Institute Of Advanced Industrial & Technology | Semiconductor device |
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