JPH0728000B2 - Cooling / signal connection board, manufacturing method thereof, and semiconductor integrated circuit device - Google Patents
Cooling / signal connection board, manufacturing method thereof, and semiconductor integrated circuit deviceInfo
- Publication number
- JPH0728000B2 JPH0728000B2 JP60150100A JP15010085A JPH0728000B2 JP H0728000 B2 JPH0728000 B2 JP H0728000B2 JP 60150100 A JP60150100 A JP 60150100A JP 15010085 A JP15010085 A JP 15010085A JP H0728000 B2 JPH0728000 B2 JP H0728000B2
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- Prior art keywords
- substrate
- cooling
- integrated circuit
- groove
- grooves
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Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は計算機高密度実装技術に係り、特に、ウェハス
ケール半導体集積回路基板の積層実装、所謂ウェハ・ス
タック実装に好適な冷却兼信号接続基板およびその製造
方法、並びに半導体集積回路装置に関する。Description: FIELD OF THE INVENTION The present invention relates to a computer high-density mounting technology, and particularly to a cooling and signal connection board suitable for stacked mounting of wafer scale semiconductor integrated circuit boards, so-called wafer stack mounting, and The present invention relates to a manufacturing method thereof and a semiconductor integrated circuit device.
電子計算機の集積回路の集積度を高めることは、単に体
積効率を高めるだけでなく、信号の遅延時間を減らすな
ど、性能の向上に重要な要因となる。この目的では、回
路を搭載したSi基板（ウェハースケールーインテグレイ
ション（Wafer-Scale-Integration））を複数枚積層す
る所謂ウェハスタック実装が有力な手段になる。この構
造で、更に配線の長さを短くするには、回路基板面の法
線方向に信号を取り出し、その方向で次の回路基板面上
に接続することが最も効果がある。このような構造を可
能にするため、グリンズバーグ（Grinsberg）らは基板
上に金属製のブリッジを形成して、機械的に基板間を接
続している。（「ア セルラー ヴィ・エル・エス・ア
イ アーキテクチャ・コンピュータ」アイ・イー・イー
・イー トランザクション（A Cellular VLSI Architec
ture,Computer,IEEE Trans.）Ｃ−33巻１号（1984年１
月）69〜81頁） この構造は各ウェハスケール集積回路基板を直接積層実
装するもので、冷却については考慮されておらず、小数
の接続点を有する場合にのみ有効であり、基板を大面積
化して接続点数を増大すると、全接続点における接触の
信頼性が低下すること、また、基板からの放熱が困難に
なること等の問題があった。Increasing the degree of integration of an integrated circuit of an electronic computer is an important factor for improving not only volume efficiency but also signal delay time. For this purpose, so-called wafer stack mounting in which a plurality of Si substrates (Wafer-Scale-Integration) on which circuits are mounted are laminated is an effective means. In this structure, in order to further shorten the length of the wiring, it is most effective to take out a signal in the normal direction of the circuit board surface and connect it to the next circuit board surface in that direction. To enable such a structure, Grinsberg et al. Form a metal bridge on the substrates to mechanically connect the substrates. (“A Cellular VLSI Architec”)
ture, Computer, IEEE Trans.) C-33 Vol. 1 (1984 1
(Mon.) 69-81) This structure directly mounts each wafer-scale integrated circuit board, cooling is not taken into consideration, and it is effective only when there are a small number of connection points. However, if the number of connection points is increased by increasing the number of connection points, there is a problem that reliability of contact at all connection points is reduced and heat dissipation from the substrate becomes difficult.
さらに、信号接続のために板厚を貫通する導線群を高密
度に配置する技術としては、Si基板にAlを拡散するサー
モマイグレイションがあるが、導体部の抵抗値は数Ωと
比較的高く、Siの電気的絶縁性にも問題がある。（ピー
タースン，ケイ・イー（Petersen,K,E.）による「シリ
コン アズ ア メカニカル マティリアル」プロスィ
ーディングス アイ・イー・イー・イー（Sillicon as
a Mechanical Material,Prod.IEEE）70−５巻（1982年
５月）429頁） 〔発明の目的〕 本発明の目的は、ウェハスタック実装に好適なコンパク
トな冷却および信号接続手段を有する基板およびその製
造方法、並びに半導体集積回路装置を提供することにあ
る。Furthermore, as a technique for arranging a group of conductors penetrating the plate thickness at a high density for signal connection, there is thermomigration which diffuses Al into the Si substrate, but the resistance value of the conductor part is relatively high, a few Ω. , Si also has a problem in electrical insulation. (Petersen, K, E.'s "Silicon as a Mechanical Materia" Pro-Sweddings, Sillicon as
a Mechanical Material, Prod. IEEE) 70-5 (May 1982) page 429) [Object of the Invention] An object of the present invention is to provide a substrate having compact cooling and signal connecting means suitable for wafer stack mounting, and a substrate thereof. A manufacturing method and a semiconductor integrated circuit device are provided.
ウェハ・スタック実装は、数十万ゲートを集積し、数百
Ｗに達する発熱量、数千本にも達する入出力信号線を有
するウェハスケール集積回路基板を、数十枚〜数百枚積
層実装するものである。Wafer stack mounting integrates hundreds of thousands of gates, stacks several tens to several hundreds of wafer-scale integrated circuit boards each having a heating value of several hundred W and input / output signal lines of several thousand. To do.
したがって、各集積回路基板の冷却手段、各集積回路基
板の信号接続手段をコンパクトに構成できることが必要
である。Therefore, it is necessary to make the cooling means for each integrated circuit board and the signal connection means for each integrated circuit board compact.
大容量計算機に用いる大面積基板例えば一辺が約100mm
の複数の基板間で104個以上の電気的接続を得るには、
第５図に示すように基板間に電気的接続部材11を挿入す
ることが一つの解決策となるこの接続部材は、その板厚
方向に貫通した導電体群12を面内に有し、更に回路から
発生する熱を排出する冷媒13を通じるための流路14を共
存させる必要がある。Large area substrate used for large capacity computer
To obtain more than 10 4 electrical connections between multiple boards in
One of the solutions is to insert an electrical connecting member 11 between the substrates as shown in FIG. 5, which has a conductor group 12 penetrating in the plate thickness direction in the plane, It is necessary to coexist with the flow path 14 for passing the refrigerant 13 for discharging the heat generated from the circuit.
本発明は、各ウェハスケール集積回路基板を直接積層実
装しないで、別に、冷却および信号接続手段を一体に形
成した冷却兼信号接続基板を用意し、各集積回路基板間
にはさみ込んで積層実装するものである。The present invention does not directly stack and mount each wafer-scale integrated circuit board, but separately prepares a cooling and signal connection board integrally formed with cooling and signal connection means, and sandwiches and mounts each integrated circuit board between the integrated circuit boards. It is a thing.
すなわち、本発明の冷却兼信号接続基板は、冷媒を循環
させるための溝と、相互に電気的に絶縁され、当該基板
の表面と裏面とを電気的に接続する複数の導体部とを有
し、前記導体部と電気的に接続され、かつ、相互に電気
的に絶縁された電極が、前記表面、前記裏面の少なくと
も一方に配列して設けられ、かつ、前記電極が、当該基
板と接続される集積回路基板上に設けられた電極と共に
積層時にコンデンサを形成することを特徴とする。That is, the cooling and signal connection board of the present invention has a groove for circulating a coolant and a plurality of conductor portions electrically insulated from each other and electrically connecting the front surface and the back surface of the board. An electrode electrically connected to the conductor portion and electrically insulated from each other is provided in an array on at least one of the front surface and the back surface, and the electrode is connected to the substrate. The capacitor is formed at the time of stacking together with the electrodes provided on the integrated circuit substrate.
また、本発明の冷却兼信号接続基板の製造方法は、基板
を貫通する導電性部材を形成する工程と、前記基板に冷
媒循環用溝を形成する工程と、前記導電性部材を分断し
て、前記基板の表面と裏面とを電気的に接続する複数の
導体部を形成する工程とを含むことを特徴とする。Further, the cooling and signal connection board manufacturing method of the present invention, a step of forming a conductive member penetrating the substrate, a step of forming a coolant circulation groove in the substrate, the conductive member is divided, And a step of forming a plurality of conductor portions that electrically connect the front surface and the back surface of the substrate.
さらに、本発明の半導体集積回路装置は、その表面に回
路素子が形成された複数の半導体集積回路基板を、絶縁
基板を介して積層した半導体集積回路装置であって、前
記半導体集積回路基板の各々は該表面に形成された信号
電極と、該表面と裏面とを電気的に接続するスルーホー
ルとを有し、前記絶縁基板はその一方の主面側に配置さ
れる前記半導体集積回路基板のスルーホールと他方の主
面側に配置される前記半導体集積回路装置の信号電極と
の間で信号を伝達するための導体部と、該絶縁基板内部
に形成され、冷媒を循環させるための溝とを有すること
を特徴とする。Further, the semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device in which a plurality of semiconductor integrated circuit substrates having circuit elements formed on the surface thereof are laminated via an insulating substrate, each of the semiconductor integrated circuit substrates being Has a signal electrode formed on the front surface and a through hole for electrically connecting the front surface and the back surface, and the insulating substrate is a through hole of the semiconductor integrated circuit substrate arranged on one main surface side thereof. A conductor portion for transmitting a signal between the hole and the signal electrode of the semiconductor integrated circuit device arranged on the other main surface side; and a groove formed inside the insulating substrate for circulating a coolant. It is characterized by having.
本発明の製造方法の望ましい実施態様においては、絶縁
性材料の板材を素材として、その表面に複数の互いに平
行な第１の溝を形成し、更に裏面から前記第１の溝と直
交して出会う複数の第２の溝または前記第１の溝と出会
う複数の孔を形成し、次いでこれらの溝および孔の内部
に導電性材料を充填することにより、基板面を貫通する
導電性部材を形成する。この後、板面の少なくとも一面
に存在する縞状の前記導電性部材と直交する方向に溝加
工を行なって該導体部を分断することにより、板面を貫
通する互いに独立した複数の導体部を形成し、同時にこ
れらの導体部間を冷却する冷媒流路を形成する。In a preferred embodiment of the manufacturing method of the present invention, a plate material made of an insulating material is used as a raw material, and a plurality of first grooves parallel to each other are formed on the surface of the plate material. Forming a plurality of second grooves or a plurality of holes that meet the first groove, and then filling the inside of these grooves and holes with a conductive material to form a conductive member that penetrates the substrate surface. . After that, a groove is formed in a direction orthogonal to the striped conductive member present on at least one surface of the plate surface to divide the conductor portion, thereby forming a plurality of independent conductor portions penetrating the plate surface. At the same time, a coolant channel is formed to cool these conductor parts.
このような構成により、２基板の対向する電極パッドを
電気的につなぐ多数の独立した導体部群を基板中に高密
度に形成し、かつ電気回路から発生する熱を排出する冷
却媒体の流路を高密度に形成することができる。With such a structure, a large number of independent conductor portions that electrically connect the opposing electrode pads of the two substrates are formed in the substrate at a high density, and the flow path of the cooling medium that discharges the heat generated from the electric circuit. Can be formed with high density.
以下、本発明の冷却兼信号接続基板および半導体集積回
路装置の一実施例を第１図により説明する。同図は半導
体集積回路基板１と冷却兼信号接続基板２の１組の部分
断面図である。これらの多数組を積層圧接することによ
り所望のウェハスタック実装体（半導体集積回路装置）
を得ることができる。集積回路基板１の表面（同図では
上面）には所望の回路素子、入出力信号電極８、絶縁膜
３、また、裏面にはスルーホール４、さらに、表面に前
記回路素子、信号電極８およびスルーホール４間の配線
が形成されている。なお、同図では回路素子、配線の図
示を省略している。An embodiment of the cooling and signal connection board and the semiconductor integrated circuit device of the present invention will be described below with reference to FIG. The figure is a partial sectional view of a set of a semiconductor integrated circuit board 1 and a cooling and signal connection board 2. A desired wafer stack mounting body (semiconductor integrated circuit device) is obtained by laminating and pressing a large number of these sets.
Can be obtained. A desired circuit element, an input / output signal electrode 8, an insulating film 3 is provided on the front surface (upper surface in the figure) of the integrated circuit substrate 1, a through hole 4 is provided on the back surface, and the circuit element, the signal electrode 8 and Wiring between the through holes 4 is formed. Note that illustration of circuit elements and wirings is omitted in FIG.
本実施例の冷却兼信号接続基板２は、溝６を有する高熱
伝導電気絶縁性炭化ケイ素から成る冷却ブロック７と銅
ピン９、入出力信号電極10から構成される。溝６には
水、フロリナート（3M社登録商標）または空気等の冷媒
流体が循環される。The cooling / signal connection substrate 2 of this embodiment is composed of a cooling block 7 having a groove 6 and made of high thermal conductive electrically insulating silicon carbide, a copper pin 9, and an input / output signal electrode 10. A coolant fluid such as water, Fluorinert (registered trademark of 3M Company), or air is circulated in the groove 6.
集積回路基板１のスルーホール４に冷却兼信号接続基板
２の銅ピン９を嵌合させ、スルーホール４内に充填した
半田等の低融点金属16により固着する。その際、集積回
路基板１と冷却兼信号接続基板２の間には熱伝導グリー
ス５等を介在させ、熱抵抗を低減している。The copper pin 9 of the cooling / signal connection board 2 is fitted into the through hole 4 of the integrated circuit board 1 and fixed by the low melting point metal 16 such as solder filled in the through hole 4. At that time, thermal conductive grease 5 or the like is interposed between the integrated circuit board 1 and the cooling / signal connection board 2 to reduce the thermal resistance.
このような集積回路基板１と冷却兼信号接続基板２の組
を多数組積層圧接して、所望のウェハスタック実装体を
得る。このとき、基板２の電極10とその直下の集積回路
基板１の電極８は絶縁膜３を介して対向してコンデンサ
を形成する。A large number of such sets of the integrated circuit board 1 and the cooling / signal connection board 2 are laminated and pressure-bonded to obtain a desired wafer stack mounting body. At this time, the electrode 10 of the substrate 2 and the electrode 8 of the integrated circuit substrate 1 immediately below the electrode 10 face each other with the insulating film 3 interposed therebetween to form a capacitor.
本実施例では、集積回路基板１は100mm□で厚さ0.4mm、
冷却ブロック７は100mm□で高さ1.5mm、溝幅0.5mm、溝
壁厚さ0.5mm、銅ピン９は直径0.3mm、長さ1.7mm、信号
電極８、10の対向部は0.6mm□、前記コンデンサの容量
は約1PFである。ピン・ピッチは2mmで、2500本の信号接
続が可能である。In this embodiment, the integrated circuit board 1 is 100 mm square and 0.4 mm thick,
The cooling block 7 is 100 mm □, the height is 1.5 mm, the groove width is 0.5 mm, the groove wall thickness is 0.5 mm, the copper pin 9 has a diameter of 0.3 mm, the length is 1.7 mm, and the signal electrodes 8 and 10 have a facing portion of 0.6 mm □. The capacitance of the capacitor is about 1PF. The pin pitch is 2 mm, and 2500 signal connections are possible.
集積回路基板１で発生した熱は熱伝導グリース５、冷却
ブロック７を経由して冷媒流体に伝達される。熱抵抗は
0.05℃/W以下で、数百Ｗの発熱に十分耐えられる。The heat generated in the integrated circuit board 1 is transferred to the refrigerant fluid via the heat conductive grease 5 and the cooling block 7. Thermal resistance
It can withstand heat generation of several hundred W at 0.05 ° C / W or less.
また、集積回路基板１と冷却兼信号接続基板２とは相互
に容易に分解することができるので、集積回路に故障が
生じた場合に便利である。Further, the integrated circuit board 1 and the cooling / signal connection board 2 can be easily disassembled from each other, which is convenient when a failure occurs in the integrated circuit.
集積回路基板１からの信号パルスはスルーホール４、銅
ピン９、信号電極８、10で形成されるコンデンサを経由
して、隣接する集積回路基板に伝送される。なお、容量
結合による信号伝送方式の具体例については、例えば特
開昭56−2662号に詳しく記載されている。The signal pulse from the integrated circuit board 1 is transmitted to the adjacent integrated circuit board via the capacitor formed by the through hole 4, the copper pin 9, and the signal electrodes 8 and 10. A concrete example of the signal transmission system by capacitive coupling is described in detail, for example, in Japanese Patent Laid-Open No. 56-2662.
容量接合では、半田付け等の固着接合に比べて、保守点
検のために必要な着脱が格段に容易になる。また、コネ
クタ接合では、通常、そうであるが、ピン数が多くなっ
た場合、挿抜力が大きくなり、着脱が困難になるが、容
量接合では、挿抜力がほぼ０である。さらに、容量接合
では、３枚以上の基板をスタックした場合、中ほどの基
板を横方向に容易に取り出すことができるが、固着接
合、コネクタ接合では、実質的に不可能である。In capacitive bonding, attachment / detachment required for maintenance and inspection is much easier than in fixed bonding such as soldering. In connector joining, which is usually the case, when the number of pins is large, the inserting / withdrawing force becomes large and it becomes difficult to attach / detach, but in the capacitive joining, the inserting / withdrawing force is almost zero. Further, in capacitive bonding, when three or more substrates are stacked, the middle substrate can be easily taken out in the lateral direction, but it is practically impossible with fixed bonding or connector bonding.
第５図に、第１図に示した半導体集積回路基板と冷却兼
信号接続基板を用いてウェハスタッフ実装した全体構成
を示す。図において、11、11′、11″は本発明による冷
却兼信号接続基板、22は導体部、13は冷媒、14は冷媒循
環用溝、15、15′、15″、15は集積回路基板で、これ
らの冷却兼信号接続基板11、11′、11″および集積回路
基板15、15′、15″、15を積層圧接することによりウ
エハスタック実装体を得ることができる。FIG. 5 shows an overall configuration of wafer stuff mounting using the semiconductor integrated circuit board and the cooling / signal connection board shown in FIG. In the figure, 11, 11 'and 11 "are cooling and signal connection boards according to the present invention, 22 is a conductor portion, 13 is a coolant, 14 is a coolant circulation groove, 15, 15', 15" and 15 are integrated circuit boards. A wafer stack mounting body can be obtained by laminating and pressing these cooling and signal connection boards 11, 11 ', 11 "and integrated circuit boards 15, 15', 15", 15 together.
以上、本発明の冷却兼信号接続基板の実施例について述
べたが、あくまで一つの実施例であり、これに限定され
ることはない。Although the embodiment of the cooling and signal connecting board of the present invention has been described above, it is merely an embodiment and the present invention is not limited to this.
次に、本発明の冷却兼信号接続基板の製造方法の実施例
を詳細に説明する。Next, an embodiment of the method for manufacturing a cooling and signal connection board according to the present invention will be described in detail.
第２図（ａ）〜（ｃ）は、本発明の製造方法の第１の実
施例を示す工程図である。同図は板状の部品の一部を切
り出して拡大しており、図中の（ａ）（ｂ）（ｃ）の順
で工程を進める。本実施例では、絶縁体として0.5mmの
厚さの炭化ケイ素（SiC）板を用いる。2 (a) to 2 (c) are process charts showing the first embodiment of the manufacturing method of the present invention. In the figure, a part of a plate-shaped part is cut out and enlarged, and the steps are performed in the order of (a), (b) and (c) in the figure. In this embodiment, a silicon carbide (SiC) plate having a thickness of 0.5 mm is used as the insulator.
まず、同図（ａ）に示すように、SiC板１の表面から、
深さ0.26mm、幅0.08mmの溝12を0.5mm間隔で相互に平
行、かつ等間隔に形成する。この工程は砥石を用いた研
削によって容易に行うことができる。また、裏面には、
表面側の溝と直交する方向に、表面と同寸法、同配列の
溝12′を形成する。これら２組の溝列は、板の厚さの中
央で出会い、両者が交わる点において、板を貫通する孔
が形成される。すなわち、板の面内の縦・横方向にそれ
ぞれ0.5mmピッチの正方配列の貫通孔が形成される。First, from the surface of the SiC plate 1, as shown in FIG.
Grooves 12 having a depth of 0.26 mm and a width of 0.08 mm are formed at 0.5 mm intervals in parallel with each other and at equal intervals. This step can be easily performed by grinding with a grindstone. Also, on the back side,
Grooves 12 'having the same size and arrangement as the surface are formed in a direction orthogonal to the grooves on the surface side. These two sets of groove rows meet at the center of the thickness of the plate, and a hole penetrating the plate is formed at the point where they meet. That is, the through holes are formed in a square array with a pitch of 0.5 mm in each of the vertical and horizontal directions in the plane of the plate.
次いで、同図（ｂ）に示すように、前記の溝の内部に導
電性材料を充填する。このための最も一般的な方法は、
金属をメッキすることである。ここでは、SiC板の両面
からAuを蒸着し、その後に板面上のAuをはく離して、溝
の内面のみにAuを残留せしめる。この後、Auを電極とし
てクロムメッキを施した。この結果、溝列２、２′の内
部に充填されたCr3、３′は互いに連結してSiCの板厚を
貫通する導電性部材が形成される。Then, as shown in FIG. 6B, the inside of the groove is filled with a conductive material. The most common way to do this is
It is to plate metal. Here, Au is vapor-deposited from both sides of the SiC plate, and then Au on the plate surface is peeled off to leave Au only on the inner surface of the groove. After that, chrome plating was performed using Au as an electrode. As a result, the Cr3 and 3'filled inside the groove rows 2 and 2'are connected to each other to form a conductive member penetrating the thickness of SiC.
次に、同図（ｃ）に示すように、板の表面において縞状
に形成された導電性部材を、これと直交する方向に分断
して、導電性部材を正方配列状に電気的に独立させる。
この際に加工する溝14および14′の深さは、導電性材料
を充填した溝の深さより大であり、かつ板厚よりも小さ
い値でなければならない。本実施例では溝の寸法を、深
さ0.28mm、幅0.1mm、ピッチ0.5mmとした。また、溝列14
と裏面の導電性部材の列３′とは互いの位置を半ピッチ
分だけずらし、両者が出会わないように設定する。この
結果、SiC板の表裏を貫通する独立した導電性部材群
が、板面内の縦、横方向にそれぞれ0.5mmピッチで形成
され、同時に回路から発生する熱を排出する冷媒流路が
溝14、14′によって形成される。Next, as shown in FIG. 3C, the conductive members formed in stripes on the surface of the plate are divided in a direction orthogonal to the stripes to electrically separate the conductive members in a square array. Let
The depth of the grooves 14 and 14 'to be machined at this time must be larger than the depth of the grooves filled with the conductive material and smaller than the plate thickness. In this embodiment, the dimensions of the groove are 0.28 mm in depth, 0.1 mm in width, and 0.5 mm in pitch. Also, the groove row 14
The position of the conductive member row 3'on the back and the position of the conductive member line 3'on the back surface are shifted by a half pitch so that they do not meet. As a result, a group of independent conductive members that penetrate the front and back of the SiC plate are formed at a pitch of 0.5 mm in each of the vertical and horizontal directions in the plate surface, and at the same time, a refrigerant flow path for discharging heat generated from the circuit is formed in the groove 14. , 14 '.
冷媒流路には前記の状態のまま、冷媒を流すことも可能
であるが、導体間の電気的絶縁を更に保証する目的で、
必要に応じて高分子膜を内面に蒸着することも可能であ
る。Although it is possible to flow the refrigerant in the refrigerant flow path in the above state, for the purpose of further assuring electrical insulation between the conductors,
If necessary, a polymer film may be vapor-deposited on the inner surface.
前記実施例において、溝の深さ、幅、間隔等の寸法は板
面内で一定である必要は無く、また、表裏が対称でなく
ても良い。In the above-mentioned embodiment, the dimensions such as the depth, width and spacing of the grooves do not have to be constant within the plate surface, and the front and back sides do not have to be symmetrical.
本発明の製造方法の第２の実施例を第３図に示す。この
場合は、第１の実施例の第２図（ａ）の工程において溝
を板の片面からのみ加工し、他の一面は直径が0.08mmの
孔開けを行ったものである。板厚が0.5mmと孔径に対し
て大きいので、全板厚を円筒状に孔開けすることは非常
に難しいが、裏面から溝加工を行って孔開けに必要な深
さを減じた結果、厚い板厚を貫く孔が形成できる。この
後、第１の実施例と同じく、導電性材料を充填し、更に
裏面側の縞状の導電性部材を分断すれば、独立した導体
部の配列と冷媒のための流路が形成される。第４図に
は、この場合に形成される個々の導体部の形状を取り出
して示した。A second embodiment of the manufacturing method of the present invention is shown in FIG. In this case, in the step of FIG. 2 (a) of the first embodiment, the groove is processed only from one side of the plate, and the other side is perforated with a diameter of 0.08 mm. Since the plate thickness is 0.5 mm, which is large compared to the hole diameter, it is very difficult to drill the entire plate thickness in a cylindrical shape, but as a result of reducing the depth required for drilling by performing groove processing from the back side, it is thick Holes can be formed through the plate thickness. Thereafter, as in the first embodiment, by filling the conductive material and further dividing the striped conductive member on the back surface side, an array of independent conductors and a flow path for the coolant are formed. . FIG. 4 shows the shapes of the individual conductors formed in this case.
以上に述べた、第１および第２の実施例の製造方法によ
り絶縁体内部に形成された導体部の密度は50×50mmのエ
リアにおいて10000個に達する。これらの導体部の表面
から裏面までの電気抵抗は単体当たり10-2Ω以下であ
り、Siウエハを貫通するAlマイグレーションよりも十分
に小さい。The density of the conductor portion formed inside the insulator by the above-described manufacturing methods of the first and second embodiments reaches 10,000 in the area of 50 × 50 mm. The electric resistance from the front surface to the back surface of these conductor parts is 10 -2 Ω or less per unit, which is sufficiently smaller than the Al migration penetrating the Si wafer.
一方、冷媒の流路は、前記の導体群に接して走ることが
できるので、冷却効果は非常に大きい。On the other hand, since the flow path of the coolant can run in contact with the conductor group, the cooling effect is very large.
以上、本発明の冷却兼信号接続基板の製造方法の実施例
について述べたが、あくまで一つの実施例であり、これ
に限定されることはない。The embodiment of the method for manufacturing the cooling and signal connection board according to the present invention has been described above, but the embodiment is only one embodiment and the present invention is not limited to this.
以上説明したように、本発明の冷却兼信号接続基板およ
び半導体集積回路装置によれば、コンパクトな冷却手
段、信号接続手段を実現できるので、数百Ｗの発熱量を
有し、数千本の入出力信号線を有する集積回路基板を超
高密度にスタック実装することができる。As described above, according to the cooling / signal connection board and the semiconductor integrated circuit device of the present invention, it is possible to realize a compact cooling means and a signal connection means. It is possible to stack and mount an integrated circuit board having input / output signal lines at a very high density.
また、本発明の冷却兼信号接続基板の製造方法によれ
ば、高い絶縁性を有する板材に対して、その板厚を貫通
する低抵抗（10-2Ω以下）の導体部を高密度に形成でき
ると同時に、電子回路から発生する熱を排出するための
冷媒用流路を高密度に形成することが可能になるので、
ウェハ−スケール−インテグレイションの設計思想にも
とづく計算機において、著しい容量規模の拡大をもたら
すという効果がある。Further, according to the method for manufacturing a cooling and signal connecting board of the present invention, a conductor portion having a low resistance (10 −2 Ω or less) penetrating the plate thickness is formed in a high density on a plate material having a high insulating property. At the same time, because it becomes possible to form the flow path for the refrigerant for discharging the heat generated from the electronic circuit with high density,
In the computer based on the design concept of wafer-scale-integration, there is an effect that the capacity scale is significantly expanded.
第１図は、本発明の冷却兼信号接続基板および半導体集
積回路装置の一実施例の部分断面図、第２図（ａ）〜
（ｃ）は、それぞれ本発明の製造方法の第１の実施例の
工程を示す斜視図、第３図は、本発明の製造方法の別の
実施例を示す斜視図、第４図は、第３図に示した製造方
法によって形成された導体部の斜視図、第５図は、本発
明の概念を示す計算機の実装構造の斜視図である。 １、15、15′、15″、15…半導体集積回路基板 ２…冷却兼信号接続基板、３、３′…導電性材料 ４…スルーホール、５…熱伝導グリース ６…溝、７…冷却ブロック ８、10…入出力信号電極、９…導体ピン 12、12…溝、14、14′…冷媒流路 11、11′、11″…冷却兼信号接続基板 12…導電体部材、13…冷媒 16…低融点金属FIG. 1 is a partial sectional view of an embodiment of a cooling and signal connection board and a semiconductor integrated circuit device of the present invention, and FIG.
(C) is a perspective view showing the steps of the first embodiment of the manufacturing method of the present invention, FIG. 3 is a perspective view showing another embodiment of the manufacturing method of the present invention, and FIG. FIG. 5 is a perspective view of a conductor portion formed by the manufacturing method shown in FIG. 3, and FIG. 5 is a perspective view of a mounting structure of a computer showing the concept of the present invention. 1, 15, 15 ', 15 ", 15 ... Semiconductor integrated circuit board 2 ... Cooling and signal connecting board 3, 3' ... Conductive material 4 ... Through hole, 5 ... Thermal conductive grease 6 ... Groove, 7 ... Cooling block 8, 10 ... Input / output signal electrodes, 9 ... Conductor pins 12, 12 ... Grooves, 14, 14 ′ ... Refrigerant flow paths 11, 11 ′, 11 ″ ... Cooling / signal connection board 12 ... Conductor member, 13 ... Refrigerant 16 … Low melting point metal
Claims (9)
的に絶縁され、当該基板の表面と裏面とを電気的に接続
する複数の導体部とを有し、前記導体部と電気的に接続
され、かつ、相互に電気的に絶縁された電極が、前記表
面、前記裏面の少なくとも一方に配列して設けられ、か
つ、前記電極が、当該基板と接続される集積回路基板上
に設けられた電極と共に積層時にコンデンサを形成する
ことを特徴とする冷却兼信号接続基板。1. A groove for circulating a coolant, and a plurality of conductors electrically insulated from each other and electrically connecting a front surface and a back surface of the substrate to each other. Electrodes disposed on at least one of the front surface and the back surface and electrically connected to each other, and the electrodes are provided on an integrated circuit substrate connected to the substrate. A cooling / signal connection board, wherein a capacitor is formed at the time of lamination together with the formed electrodes.
ることを特徴とする特許請求の範囲第１項記載の冷却兼
信号接続基板。2. The cooling / signal connection board according to claim 1, wherein the conductor portion is formed in a wall of the groove.
材料からなることを特徴とする特許請求の範囲第１項記
載の冷却兼信号接続基板。3. The cooling and signal connection board according to claim 1, wherein the board is made of an electrically insulating material having high heat conductivity.
の炭化ケイ素からなることを特徴とする特許請求の範囲
第１項記載の冷却兼信号接続基板。4. The cooling / signal connection board according to claim 1, wherein the board is made of silicon carbide having high heat conductivity and electrical insulation.
と、前記基板に冷媒循環用溝を形成する工程と、前記導
電性部材を分断して、前記基板の表面と裏面とを電気的
に接続する複数の導体部を形成する工程とを含むことを
特徴とする冷却兼信号接続基板の製造方法。5. A step of forming a conductive member penetrating the substrate, a step of forming a coolant circulation groove in the substrate, and a step of electrically separating the front and back surfaces of the substrate by dividing the conductive member. And a step of forming a plurality of conductor parts connected to the cooling and signal connection board.
し、該基板の裏面に前記第１の溝と交差する複数の第２
の溝を形成し、前記第１および第２の溝内に導電性材料
を充填して前記導電性部材を形成し、次に、前記第１ま
たは第２の溝と交差する複数の前記冷媒循環用溝を形成
することにより前記導電性部材を分断して相互に電気的
に絶縁された複数の導体部を形成することを特徴とする
特許請求の範囲第５項記載の冷却兼信号接続基板の製造
方法。6. A plurality of first grooves are formed on the front surface of the substrate, and a plurality of second grooves intersect with the first grooves on the back surface of the substrate.
A plurality of the refrigerant circulations that intersect the first or second groove by forming a groove of the first and second grooves and filling a conductive material into the first and second grooves to form the conductive member. 6. The cooling and signal connection board according to claim 5, wherein the conductive member is divided by forming grooves for use to form a plurality of conductor portions electrically insulated from each other. Production method.
し、該基板の裏面に前記第１の溝と交差する複数の孔を
形成し、前記第１の溝および前記孔内に導電性材料を充
填して前記導電性部材を形成し、次に、前記第１の溝と
交差する複数の前記冷媒循環用溝を形成することにより
前記導電性部材を分断して相互に電気的に絶縁された複
数の導体部を形成することを特徴とする特許請求の範囲
第５項記載の冷却兼信号接続基板の製造方法。7. A plurality of first grooves are formed on the front surface of the substrate, a plurality of holes intersecting the first groove are formed on the back surface of the substrate, and the first grooves and the holes are formed in the first groove and the holes. The conductive member is filled with a conductive material to form the conductive member, and then the plurality of coolant circulation grooves intersecting with the first groove are formed to divide the conductive member to electrically connect to each other. The method for manufacturing a cooling and signal connecting board according to claim 5, wherein a plurality of conductor portions insulated from each other are formed.
ることを特徴とする特許請求の範囲第５項ないし第７項
のいずれかに記載の冷却兼信号接続基板の製造方法。8. The method for manufacturing a cooling / signal connection board according to claim 5, wherein an insulating plate material is used as the board.
導体集積回路基板を、絶縁基板を介して積層した半導体
集積回路装置であって、前記半導体集積回路基板の各々
は該表面に形成された信号電極と、該表面と裏面とを電
気的に接続するスルーホールとを有し、前記絶縁基板は
その一方の主面側に配置される前記半導体集積回路基板
のスルーホールと他方の主面側に配置される前記半導体
集積回路装置の信号電極との間で信号を伝達するための
導体部と、該絶縁基板内部に形成され、冷媒を循環させ
るための溝とを有することを特徴とする半導体集積回路
装置。9. A semiconductor integrated circuit device in which a plurality of semiconductor integrated circuit substrates each having a circuit element formed on the surface thereof are laminated via an insulating substrate, each of the semiconductor integrated circuit substrates being formed on the surface. A signal electrode and a through hole for electrically connecting the front surface and the back surface, and the insulating substrate is disposed on one main surface side of the semiconductor integrated circuit board through hole and the other main surface. A conductor portion for transmitting a signal to and from the signal electrode of the semiconductor integrated circuit device arranged on the side, and a groove formed inside the insulating substrate for circulating a coolant. Semiconductor integrated circuit device.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60150100A JPH0728000B2 (en) | 1985-07-10 | 1985-07-10 | Cooling / signal connection board, manufacturing method thereof, and semiconductor integrated circuit device |
| US07/240,443 US4893174A (en) | 1985-07-08 | 1988-09-02 | High density integration of semiconductor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60150100A JPH0728000B2 (en) | 1985-07-10 | 1985-07-10 | Cooling / signal connection board, manufacturing method thereof, and semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6212146A JPS6212146A (en) | 1987-01-21 |
| JPH0728000B2 true JPH0728000B2 (en) | 1995-03-29 |
Family
ID=15489506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60150100A Expired - Lifetime JPH0728000B2 (en) | 1985-07-08 | 1985-07-10 | Cooling / signal connection board, manufacturing method thereof, and semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0728000B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4608763B2 (en) * | 2000-11-09 | 2011-01-12 | 日本電気株式会社 | Semiconductor device |
| US7432592B2 (en) | 2005-10-13 | 2008-10-07 | Intel Corporation | Integrated micro-channels for 3D through silicon architectures |
| US8035223B2 (en) * | 2007-08-28 | 2011-10-11 | Research Triangle Institute | Structure and process for electrical interconnect and thermal management |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5651849A (en) * | 1979-10-05 | 1981-05-09 | Hitachi Ltd | Cooling device for integrated circuit |
-
1985
- 1985-07-10 JP JP60150100A patent/JPH0728000B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6212146A (en) | 1987-01-21 |
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