JPH07249735A - Parallel connection of semiconductor element - Google Patents
Parallel connection of semiconductor elementInfo
- Publication number
- JPH07249735A JPH07249735A JP6064598A JP6459894A JPH07249735A JP H07249735 A JPH07249735 A JP H07249735A JP 6064598 A JP6064598 A JP 6064598A JP 6459894 A JP6459894 A JP 6459894A JP H07249735 A JPH07249735 A JP H07249735A
- Authority
- JP
- Japan
- Prior art keywords
- parallel
- semiconductor element
- semiconductor
- connection
- semiconductor elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Power Conversion In General (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、並列接続された３個以
上の半導体素子（半導体素子のチップ、サブモジュ−ル
やモジュ−ルを含む）間の分担電流の均等化を図る半導
体素子の並列接続方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel semiconductor device in which three or more semiconductor devices (including semiconductor device chips, sub-modules and modules) connected in parallel are provided with equalization of shared current. Regarding connection method.
【０００２】[0002]
【従来の技術】一般に、微細構造の半導体素子（トラン
ジスタ、ＩＧＢＴ、ＭＯＳ−ＦＥＴ）は、半導体素子の
チップを大きくするに従って歩留まりが低下する。この
ため、大容量化する時は、モジュ−ルの中でチップを並
列に接続する。この場合、モジュ−ルに流れる電流変化
率（ｄｉ／ｄｔ）が大きくなる程、並列配線のインダク
タンスＬに発生する電圧（Ｌ・ｄｉ／ｄｔ）が大きくな
るので、並列素子間の分担電流に影響を与える。このた
めに並列配線のインダクタンスＬを均等化する方法（特
開昭６１−２１８１５１号公報、特願平２−４０７５６
７号公報）が提案されている。例えば、特開昭６１−２
１８１５１号公報には、半導体素子を搭載したサブモジ
ュ−ル２個を対称に配置することにより、並列配線のイ
ンダクタンスＬの均等化を実現することが記載されてい
る。これは、半導体素子が多数個でも、それらを二分割
してサブモジュ−ル化し、それを対称に配置すること
で、両者の分担電流を均等化するに好適な並列接続方法
である。2. Description of the Related Art Generally, a semiconductor element having a fine structure (transistor, IGBT, MOS-FET) has a lower yield as the chip of the semiconductor element is enlarged. Therefore, when the capacity is increased, the chips are connected in parallel in the module. In this case, as the rate of change in current flowing through the module (di / dt) increases, the voltage (L · di / dt) generated in the inductance L of the parallel wiring increases, which affects the shared current between the parallel elements. give. For this reason, a method of equalizing the inductance L of parallel wiring (Japanese Patent Application Laid-Open No. 61-218151, Japanese Patent Application No. 2-40756).
No. 7) is proposed. For example, JP-A-61-2
Japanese Patent No. 18151 discloses that two sub-modules having semiconductor elements are symmetrically arranged to realize equalization of inductance L of parallel wiring. This is a parallel connection method that is suitable for equalizing the shared currents of both semiconductor devices even if they have a large number of semiconductor devices by dividing them into two submodules and arranging them symmetrically.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、サブモ
ジュ−ルに搭載するチップの数が多くなり過ぎると、並
列配線のインダクタンスＬの不均一が発生し、分担電流
の不均一の問題が生じてくる。このために、搭載するチ
ップの数が限定され、その結果、チップの大きさやサブ
モジュ−ルの大きさを変える必要にせまられ、チップや
サブモジュ−ルの大きさを標準化することが難しくな
る、という問題がある。本発明の目的は、このような問
題点を解決するために、半導体素子（半導体素子のチッ
プ、サブモジュ−ルやモジュ−ルを含む）を３個以上並
列接続しても、それらの分担電流を均等化するに好適な
半導体素子の並列接続方法を提供することにある。However, if the number of chips mounted on the sub-module becomes too large, the inductance L of the parallel wiring becomes non-uniform, which causes the problem of non-uniform sharing of current. For this reason, the number of chips to be mounted is limited, and as a result, it is necessary to change the size of the chip or the size of the sub-module, and it becomes difficult to standardize the size of the chip or the sub-module. There's a problem. In order to solve such a problem, an object of the present invention is to provide three or more semiconductor elements (including semiconductor element chips, sub-modules and modules) in parallel, but to share the shared currents among them. Another object of the present invention is to provide a parallel connection method of semiconductor devices suitable for equalization.
【０００４】[0004]
【課題を解決するための手段】前記目的を達成するため
に、同一基盤上に３個以上の半導体素子を配し、前記半
導体素子を並列接続する半導体素子の並列接続方法にお
いて、前記３個以上の半導体素子を並列接続する上位と
下位からなる接続体によってト−ナメント接続し、各半
導体素子の電流分担が均等に作用されるべく、前記上位
接続体と前記下位接続体の接続点を前記下位接続体の中
心より一方に片寄らせることを特徴としている。また、
同一基盤上に３個以上の半導体素子を配し、前記半導体
素子を並列接続する半導体素子の並列接続方法におい
て、前記３個以上の半導体素子を並列接続する接続体に
スリットを設け、向かい合う上位と下位の接続体を形成
し、上位接続体に給電導体を接続すると共に、下位接続
体に前記３個以上の半導体素子を並列接続し、前記給電
導体から前記各半導体素子までのインピ−ダンスが等し
くなるように前記スリットを形成することを特徴として
いる。In order to achieve the above-mentioned object, in the method of parallel connection of semiconductor elements, wherein three or more semiconductor elements are arranged on the same substrate and the semiconductor elements are connected in parallel, Tournament connection is performed by a connection body composed of upper and lower semiconductor elements connected in parallel, and the connection points of the upper connection body and the lower connection body are connected to each other so that the current sharing of each semiconductor element acts evenly. The feature is that it is offset to one side from the center of the connection body. Also,
In a parallel connection method of semiconductor elements, in which three or more semiconductor elements are arranged on the same substrate and the semiconductor elements are connected in parallel, a slit is provided in a connecting body which connects the three or more semiconductor elements in parallel, and the slits are provided to face each other. A lower connection body is formed, a power supply conductor is connected to the upper connection body, the three or more semiconductor elements are connected in parallel to the lower connection body, and the impedance from the power supply conductor to each semiconductor element is equal. The slit is formed so that
【０００５】[0005]
【作用】３個以上の半導体素子を並列接続する電極にト
−ナメント接続し、ト−ナメント接続点の位置を特定す
ることにより、電極間の一部に相互誘導作用が働き、給
電導体から各半導体素子までの配線インダクタンスの均
等化が図られるため、配線インダクタンスによる誘起電
圧の均等化を実現し、各半導体素子の分担電流を均等化
する。また、３個以上の半導体素子を並列接続する並列
接続体の電極にスリットを設け、上位接続体と下位接続
体の連結部分を下位接続体の特定位置に連結することに
より、上位接続体と下位接続体との間に相互誘導作用が
働き、給電導体から各半導体素子までの配線インダクタ
ンスの均等化が図られるため、配線インダクタンスによ
る誘起電圧の均等化を実現し、各半導体素子の分担電流
を均等化する。[Function] When three or more semiconductor elements are tournament-connected to the electrodes connected in parallel and the position of the tournament connection point is specified, a mutual induction action works on a part between the electrodes, and each of the power-feeding conductors causes Since the wiring inductance up to the semiconductor element is equalized, the induced voltage due to the wiring inductance is equalized, and the shared current of each semiconductor element is equalized. In addition, a slit is provided in an electrode of a parallel connection body that connects three or more semiconductor elements in parallel, and a connection portion of the higher connection body and the lower connection body is connected to a specific position of the lower connection body, so that the upper connection body and the lower connection body are connected. Mutual inductive action works with the connection body to equalize the wiring inductance from the power supply conductor to each semiconductor element, so that the induced voltage due to the wiring inductance is equalized and the shared current of each semiconductor element is equalized. Turn into.
【０００６】[0006]
【実施例】以下、本発明の実施例を図面を用いて説明す
る。図１は、本発明の一実施例による半導体素子の並列
接続方法を適用したＩＧＢＴモジュ−ルの概要構成を示
す模式図である。図１において、放熱板１の上にＩＧＢ
Ｔチップ２１を搭載した３個のサブモジュ−ル（２ａ、
２ｂ、２ｃ）を配置し、３個のサブモジュ−ル（２ａ、
２ｂ、２ｃ）はコレクタ電極３に並列接続される。すな
わち、コレクタ電極３は上位接続体３’と下位接続体
３”から形成され、上位接続体３’にサブモジュ−ル２
ｃを直接接続し、下位接続体３”にサブモジュ−ル２
ａ、２ｂを接続して、下位接続体３”を上位接続体３’
に接続する。また、コレクタ電極３の上位接続体３’は
給電導体３１に接続する。図の複雑化を避けるために、
ゲ−ト信号用の引出電極とエミッタ電極を省略してある
が、それぞれが並列接続される構成となっている。サブ
モジュ−ル（２ａ、２ｂ、２ｃ）は、基板２２の上に銅
を貼付てあり、これらがコレクタ領域２３、エミッタ領
域２４、ゲ−ト領域２５に分離されている。 コレクタ
領域２３にはＩＧＢＴチップ２１が搭載され、チップ上
面からエミッタ領域２４及びゲ−ト領域２５にアルミニ
ウムのワイヤ２６が配線されている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing a schematic configuration of an IGBT module to which a semiconductor device parallel connection method according to an embodiment of the present invention is applied. In FIG. 1, the IGB is placed on the heat sink 1.
Three sub-modules (2a,
2b, 2c) and three sub-modules (2a,
2b, 2c) are connected in parallel to the collector electrode 3. That is, the collector electrode 3 is formed of the upper connection body 3'and the lower connection body 3 ", and the sub-module 2 is formed on the upper connection body 3 '.
c is directly connected, and the sub-module 2 is connected to the lower connection body 3 ".
a and 2b are connected, and the lower connection body 3 ″ is connected to the upper connection body 3 ′.
Connect to. The upper connection body 3 ′ of the collector electrode 3 is connected to the power feeding conductor 31. To avoid complicating the figure,
Although the extraction electrode and the emitter electrode for the gate signal are omitted, they are connected in parallel. The sub-modules (2a, 2b, 2c) have copper adhered on the substrate 22, and these are separated into a collector region 23, an emitter region 24, and a gate region 25. The IGBT chip 21 is mounted in the collector region 23, and an aluminum wire 26 is wired from the chip upper surface to the emitter region 24 and the gate region 25.
【０００７】次に、本実施例のコレクタ電極３について
説明する。図１で明らかなように、サブモジュ−ル（２
ａ、２ｂ、２ｃ）のコレクタ領域２３は、コレクタ電極
３の上位接続体３’と下位接続体３”とによりト−ナメ
ント方式の接続構成となっていることが分かる。下位接
続体３”は引出接続部分を介して上位接続体３’に接続
され、上位接続体３’から引出接続部分に当たる給電導
体３１が接続されている。図２には、図１のコレクタ電
極３の上位接続体３’と下位接続体３”のみを示す。な
お、以下に示す図面では、本文に記載する長さ”ｌ”を
筆記体小文字のエルで表示している。図２は、上位接続
体３’の一端（図面左端）から給電導体３１の中点Ｙま
での上位接続体３’の長さｌ１と上位接続体３’の他端
（図面右端）から給電導体３１の中点Ｙまでの上位接続
体３’の長さｌ２を、ｌ１＜ｌ２の構成にし、また、下
位接続体３”の一端（図面左端）からＸ点までの下位接
続体３”の長さｌ４と下位接続体３”の他端（図面右
端）からＸ点までの下位接続体３”の長さｌ５を、ｌ４
＜ｌ５の構成にし、また、の一端から給電導体３１の中
点Ｙまでの上位接続体３’（長さｌ１）と下位接続体
３”の他端からＸ点までの下位接続体３”（長さｌ５）
との向かい合わせ距離をＷとすることによって、給電導
体３１から各々のサブモジュ−ル（２ａ、２ｂ、２ｃ）
までの配線インダクタンスの均等化を実現するものであ
る。ここで、Ａ、Ｂは下位接続体３”をサブモジュ−ル
２ａ、２ｂに、また、Ｃは上位接続体３’をサブモジュ
−ル２ｃにそれぞれ設置する箇所を示す。Next, the collector electrode 3 of this embodiment will be described. As is clear from FIG. 1, the submodule (2
It can be seen that the collector region 23 of a, 2b, 2c) has a tournament-type connection configuration by the upper connection body 3'and the lower connection body 3 "of the collector electrode 3. The lower connection body 3" is The power supply conductor 31 is connected to the upper connection body 3 ′ via the lead-out connection portion, and is connected from the upper connection body 3 ′ to the lead-out connection portion. FIG. 2 shows only the upper connection body 3 ′ and the lower connection body 3 ″ of the collector electrode 3 of FIG. 1. In the drawings shown below, the length “l” described in the text is indicated by a lower case cursive letter. 2 shows the length l1 of the upper connection body 3 ′ from one end (the left end in the drawing) of the upper connection body 3 ′ to the midpoint Y of the feeding conductor 31 and the other end of the upper connection body 3 ′ ( The length l2 of the upper connection body 3 ′ from the right end of the drawing to the midpoint Y of the power supply conductor 31 is set to l1 <l2, and the lower connection from one end (left end of the drawing) of the lower connection body 3 ″ to the X point. The length l4 of the connector 3 "and the length l5 of the lower connector 3" from the other end (right end in the drawing) of the lower connector 3 "to the point X are
<15, the upper connection body 3 '(length l1) from one end to the midpoint Y of the feeding conductor 31 and the lower connection body 3 "from the other end of the lower connection body 3" to the X point (" Length 15)
By setting the facing distance between the power supply conductor 31 and each sub-module (2a, 2b, 2c)
It realizes equalization of wiring inductance. Here, A and B are locations where the lower connection body 3 ″ is installed in the sub-modules 2a and 2b, and C is a location where the upper connection body 3 ′ is installed in the sub-module 2c.
【０００８】次に、図２の構成によってインダクタンス
を均等化できる理由について説明する。図３は、図２の
電極の配線インダクタンスを示すものである。例えば、
図２に示す長さｌ１の配線のインダクタンスは、図３に
示すＬ１に対応させており、以下、同様に図２のｌと、
図３のＬを対応させて示している。また、Ｌ１とＬ５の
間には相互誘導インダクタンスＭを発生する。給電導体
３１からサブモジュ−ル（２ａ、２ｂ、２ｃ）に流れる
電流を均等化するためには、配線インダクタンスによる
誘起電圧を均等化すればよい。すなわち、サブモジュ−
ル２ａと２ｂに等しい電流変化率（ｄｉ／ｄｔ）の電流
が流れた時、Ａ−Ｙ間とＢ−Ｙ間で発生する誘起電圧Ｖ
を均等化する。 Ｖ(Ａ−Ｙ間)＝Ｖ(Ｂ−Ｙ間) (１) (１)式を満たすように配線インダクタンスＬを求める
と、 （２(Ｌ１＋Ｌ３)＋Ｌ４＋Ｌ６−Ｍ）ｄｉ／ｄｔ＝（２
（Ｌ１＋Ｌ３）＋Ｌ５＋Ｌ６−２Ｍ）ｄｉ／ｄｔ Ｌ４＝Ｌ５−Ｍ 従って、 Ｌ４＜Ｌ５ (２) (２)式の配線のインダクタンスの関係を成立させるため
には、配線の長さをｌ４＜ｌ５にする。つまり、Ｘ点を
サブモジュ−ル２ａ、２ｂの中間点よりもサブモジュ−
ル２ａ側に設ける。同様に、サブモジュ−ル２ａまたは
２ｂと２ｃの場合、 Ｖ(Ａ−Ｙ間)＝（Ｖ(Ｂ−Ｙ間)）=Ｖ(Ｃ−Ｙ間) (３) 条件(３)を満たすように配線インダクタンスＬを求める
と、 （Ｌ２＋Ｌ３＋Ｌ６）ｄｉ／ｄｔ＝（２（Ｌ１＋Ｌ３）
＋Ｌ４＋Ｌ６−Ｍ）ｄｉ／ｄｔ Ｌ２＝２Ｌ１＋Ｌ３＋Ｌ４−Ｍ 従って、 Ｌ２＞Ｌ１ (４) (４)式の配線のインダクタンスの関係を成立させるため
には、配線の長さをｌ２＞ｌ１にする。つまり、Ｙ点を
Ｘ点とＣ点の中間点よりもＸ点側に設ける。このよう
に、本実施例では、サブモジュ−ル（２ａ、２ｂ、２
ｃ）のコレクタ領域２３をコレクタ電極３の上位接続体
３’と下位接続体３”によりト−ナメント接続し、Ｘ点
をサブモジュ−ル２ａ、２ｂの中間点よりもサブモジュ
−ル２ａ側に設け、Ｙ点をＸ点とＣ点の中間点よりもＸ
点側に設け、また、上位接続体３’と下位接続体３”間
の一部に相互誘導インダクタンスＭが発生するように両
接続体を設置することによって、配線インダクタンスに
よる誘起電圧の均等化を実現することができる。これに
より、各半導体素子の分担電流を均等化することが可能
となる。Next, the reason why the inductance can be equalized by the configuration of FIG. 2 will be described. FIG. 3 shows the wiring inductance of the electrodes of FIG. For example,
The inductance of the wiring having the length l1 shown in FIG. 2 is made to correspond to L1 shown in FIG.
The L of FIG. 3 is shown correspondingly. Further, a mutual induction inductance M is generated between L1 and L5. In order to equalize the currents flowing from the power feeding conductor 31 to the sub-modules (2a, 2b, 2c), the induced voltage due to the wiring inductance may be equalized. That is, the sub module
When a current having a current change rate (di / dt) equal to that of the electric currents 2a and 2b flows, an induced voltage V generated between A-Y and BY
Equalize. V (between A and Y) = V (between B and Y) (1) When the wiring inductance L is calculated so as to satisfy the equation (1), (2 (L1 + L3) + L4 + L6-M) di / dt = (2
(L1 + L3) + L5 + L6-2M) di / dt L4 = L5-M Therefore, in order to establish the relationship of the wiring inductance of L4 <L5 (2) (2), the wiring length is set to l4 <l5 . That is, the X point is more sub-module than the midpoint between the sub-modules 2a and 2b.
Provided on the side of the rule 2a. Similarly, in the case of submodules 2a or 2b and 2c, V (between A and Y) = (V (between B and Y)) = V (between C and Y) (3) In order to satisfy the condition (3), When the wiring inductance L is calculated, (L2 + L3 + L6) di / dt = (2 (L1 + L3)
+ L4 + L6-M) di / dt L2 = 2L1 + L3 + L4-M Therefore, in order to establish the wiring inductance relationship of L2> L1 (4) (4), the wiring length is set to l2> l1. That is, the Y point is provided on the X point side with respect to the intermediate point between the X point and the C point. Thus, in this embodiment, the sub-modules (2a, 2b, 2
The collector region 23 of c) is tournament-connected by the upper connection body 3'and the lower connection body 3 "of the collector electrode 3, and the point X is provided closer to the sub-module 2a than the midpoint between the sub-modules 2a and 2b. , Y point is X more than the midpoint between X point and C point
By providing both connecting bodies so that mutual induction inductance M is generated in a part between the upper connecting body 3 ′ and the lower connecting body 3 ″, the induced voltage is equalized by the wiring inductance. This makes it possible to equalize the shared current of each semiconductor element.
【０００９】図４に、本発明の他の実施例を示す。本実
施例は、電極にスリットを設けることを特徴とする。ス
リットを設けることにより、給電導体から各々のサブモ
ジュ−ル（２ａ、２ｂ、２ｃ）までの配線インダクタン
スの均等化を実現するものである。図４には、図１のコ
レクタ電極３のみを示し、サブモジュ−ル２ａ、２ｂ、
２ｃの配置は図１と同様とする。図４において、コレク
タ電極３にはスリットｓを設け、スリットｓを介して電
極３を上位接続体３−１と下位接続体３−２に分離し、
上位接続体３−１の中間位置に給電導体３１を設置し、
上位接続体３−１の両端と下位接続体３−２を連結し、
下位接続体３−２の配線の長さＡ−Ｂ間とＢ−Ｃ間が等
しくなるように、Ａ、Ｂ、Ｃの各点をそれぞれサブモジ
ュ−ル２ａ、２ｂ、２ｃに設置する。ここで、上位接続
体３−１の一端（図面左側）または他端（図面右側）か
ら給電導体３１の中点Ｙまでの長さｌ１、上位接続体３
−１の両端と下位接続体３−２のそれぞれの接続点の連
結部分の長さｌ２、同じくそれぞれの連結部分からＢ点
までの長さｌ３、同じくそれぞれの連結部分からＡ点ま
たはＣ点までの長さｌ４＋ｌ５として表す。FIG. 4 shows another embodiment of the present invention. The present embodiment is characterized in that the electrodes are provided with slits. By providing the slits, the wiring inductances from the feeding conductor to the respective sub-modules (2a, 2b, 2c) are equalized. FIG. 4 shows only the collector electrode 3 of FIG. 1, and the sub-modules 2a, 2b,
The arrangement of 2c is the same as in FIG. In FIG. 4, a slit s is provided in the collector electrode 3, and the electrode 3 is separated into an upper connection body 3-1 and a lower connection body 3-2 through the slit s,
The feeding conductor 31 is installed at an intermediate position of the upper connection body 3-1.
Connect both ends of the upper connection body 3-1 and the lower connection body 3-2,
The points A, B, and C are installed in the sub-modules 2a, 2b, and 2c, respectively, so that the wiring lengths A-B and B-C of the lower connection body 3-2 are equal. Here, the length l1 from one end (left side in the drawing) or the other end (right side in the drawing) of the upper connection body 3-1 to the midpoint Y of the feeding conductor 31, the upper connection body 3
-1, the length l2 of the connecting portion between both ends of -1 and each connecting point of the lower connecting body 3-2, the length l3 from each connecting portion to the point B, the same from each connecting portion to the point A or the point C Expressed as the length l4 + 15.
【００１０】次に、図４の構成によってインダクタンス
を均等化できる理由について説明する。図５は、図４の
電極の配線インダクタンスを示すものである。例えば、
図４に示す長さｌ１の配線のインダクタンスは、図５に
示すＬ１に対応させており、以下、同様に図４のｌと、
図５のＬを対応させて示している。また、それぞれのＬ
１とＬ３の間には相互誘導インダクタンスＭを発生す
る。このように、Ｂ点からみたＹ点までの電極３の配線
インダクタンスは対象である。ここで、給電導体３１か
らの配線の経路をみると、スリットｓを設けることによ
り、サブモジュ−ル２ｂまでの配線（Ｂ−Ｙ間）が最も
長く、また、サブモジュ−ル２ａ及び２ｃ側の上位接続
体３−１と下位接続体３−２のそれぞれの配線インダク
タンスＬ１とＬ３の間には、スリットｓを介して相互誘
導作用が起こる。そこで、給電導体３１からサブモジュ
−ル（２ａ、２ｂ、２ｃ）に流れる電流を均等化するた
めには、配線インダクタンスによる誘起電圧を均等化す
ればよい。すなわち、サブモジュ−ル２ａと２ｂ（また
は２ｃと２ｂ）に等しい電流変化率（ｄｉ／ｄｔ）の電
流が流れた時、Ａ−Ｙ間とＢ−Ｙ間（またはＣ−Ａ間と
Ｂ−Ｙ間）で発生する誘起電圧Ｖを均等化する。 Ｖ(Ａ−Ｙ間)＝Ｖ（Ｂ−Ｙ間） （５） （５）を満たすように配線インダクタンスＬを求める
と、以下の関係式が成立する。 （１．５Ｌ１＋１．５Ｌ２＋Ｌ４−０．５Ｍ＋Ｌ５）ｄ
ｉ／ｄｔ＝（１．５Ｌ１＋１．５Ｌ２＋０．５Ｌ３−
０．５Ｍ−１．５Ｍ＋Ｌ５） ｄｉ／ｄｔ Ｌ３＝３Ｍ＋２Ｌ４ 従って、 Ｌ３＞Ｌ４ （６） (６)式の配線のインダクタンスの関係を成立させるため
には、配線の長さをｌ３＞ｌ４にする。つまり、上位接
続体３−１の両端と下位接続体３−２を接続する連結部
分をＡ点とＢ点の中間点よりそれぞれＡ点またはＣ点側
に設けることによって、配線インダクタンスによる誘起
電圧の均等化を実現することができる。これにより、各
半導体素子の分担電流を均等化することが可能となる。Next, the reason why the inductance can be equalized by the configuration of FIG. 4 will be described. FIG. 5 shows the wiring inductance of the electrodes of FIG. For example,
The inductance of the wiring having the length l1 shown in FIG. 4 is made to correspond to L1 shown in FIG.
The L of FIG. 5 is shown correspondingly. Also, each L
A mutual induction inductance M is generated between 1 and L3. Thus, the wiring inductance of the electrode 3 from the point B to the point Y is a target. Here, looking at the route of the wiring from the power feeding conductor 31, by providing the slit s, the wiring to the sub-module 2b (between BY) is the longest, and the upper side of the sub-modules 2a and 2c side. A mutual induction action occurs between the wiring inductances L1 and L3 of the connection body 3-1 and the lower connection body 3-2 via the slit s. Therefore, in order to equalize the currents flowing from the power feeding conductor 31 to the sub-modules (2a, 2b, 2c), the induced voltage due to the wiring inductance may be equalized. That is, when a current having a current change rate (di / dt) equal to that of the sub-modules 2a and 2b (or 2c and 2b) flows, between A-Y and BY (or between CA and BY). The induced voltage V generated in (between) is equalized. V (between A and Y) = V (between B and Y) (5) When the wiring inductance L is calculated so as to satisfy (5), the following relational expression holds. (1.5L1 + 1.5L2 + L4-0.5M + L5) d
i / dt = (1.5L1 + 1.5L2 + 0.5L3-
0.5M-1.5M + L5) di / dt L3 = 3M + 2L4 Therefore, in order to establish the wiring inductance relationship of L3> L4 (6) (6), the wiring length is set to l3> l4. That is, by providing the connecting portions connecting both ends of the upper connection body 3-1 and the lower connection body 3-2 to the points A or C from the midpoint between the points A and B, respectively, the induced voltage of the wiring inductance can be reduced. Equalization can be realized. As a result, it becomes possible to equalize the shared current of each semiconductor element.
【００１１】以上、サブモジュ−ル３個に本発明を適用
した実施例で説明したが、４個以上の場合であっても同
様のル−ルで実現できることは明らかである。また、半
導体素子としてサブモジュ−ル３個に本発明を適用した
実施例で説明したが、半導体素子が個別素子またはモジ
ュ−ルであっても同様に本発明を適用できることは言う
までもない。また、本発明の実施例では、半導体素子を
ＩＧＢＴを例に説明したが、これに限定されるものでは
なく、半導体素子として、トランジスタやダイオ−ド等
であっても同様に本発明を適用できることは言うまでも
ない。Although the embodiment in which the present invention is applied to three sub-modules has been described above, it is obvious that the same rule can be realized even in the case of four or more sub-modules. Further, although the present invention has been described in the embodiment in which the present invention is applied to three sub-modules as semiconductor elements, it goes without saying that the present invention can be similarly applied even if the semiconductor elements are individual elements or modules. Further, in the embodiment of the present invention, the semiconductor element is described by taking the IGBT as an example, but the present invention is not limited to this, and the present invention can be similarly applied to a semiconductor element such as a transistor or a diode. Needless to say.
【００１２】[0012]
【発明の効果】以上説明したように、本発明によれば、
３個以上の半導体素子を並列接続する電極にト−ナメン
ト接続し、ト−ナメント接続点の位置を特定し、電極間
の一部に相互誘導作用を起こさせることにより、配線イ
ンダクタンスによる誘起電圧の均等化を実現し、各半導
体素子の分担電流を均等化することができる。また、３
個以上の半導体素子を並列接続する並列接続体の電極に
スリットを設け、上位接続体と下位接続体の連結部分を
下位接続体の特定位置に連結し、上位接続体と下位接続
体との間に相互誘導作用を起こさせることにより、配線
インダクタンスによる誘起電圧の均等化を実現し、各半
導体素子の分担電流を均等化することができる。これに
より、半導体素子のチップ及びサブモジュ−ルの標準化
が可能となり、モジュ−ルの信頼性の向上とコストの低
減化を図ることができる。As described above, according to the present invention,
The three or more semiconductor elements are tournament-connected to the electrodes connected in parallel, the position of the tournament connection point is specified, and a mutual induction action is caused in a part between the electrodes. The equalization can be realized, and the shared currents of the respective semiconductor elements can be equalized. Also, 3
A slit is provided in the electrode of the parallel connection body that connects more than one semiconductor element in parallel, the connection part of the upper connection body and the lower connection body is connected to a specific position of the lower connection body, and between the upper connection body and the lower connection body. By inducing a mutual induction action in, the equalization of the induced voltage due to the wiring inductance can be realized and the sharing current of each semiconductor element can be equalized. As a result, the chips and sub-modules of the semiconductor element can be standardized, and the reliability of the module can be improved and the cost can be reduced.
【図１】本発明の一実施例を示すモジュ−ルの構成図FIG. 1 is a block diagram of a module showing an embodiment of the present invention.
【図２】図１の電極部FIG. 2 is an electrode part of FIG.
【図３】図２の電極部の配線インダクタンスの等価回路FIG. 3 is an equivalent circuit of the wiring inductance of the electrode part of FIG.
【図４】本発明の他の実施例を示す電極の構成FIG. 4 is a constitution of an electrode showing another embodiment of the present invention.
【図５】図４の電極部の配線インダクタンスの等価回路5 is an equivalent circuit of the wiring inductance of the electrode part of FIG.
１ 放熱板 ２ａ、２ｂ、２ｃ サブモジュ−ル ２１ ＩＧＢＴチップ ２２ 基板 ２３ コレクタ領域 ２４ エミッタ領域 ２５ ゲ−ト領域 ２６ アルミニウムのワイヤ ３ コレクタ電極 ３’、３−１ コレクタ電極の上位接続体 ３”、３−２ コレクタ電極の下位接続体 ３１ 給電導体 ｓ スリット DESCRIPTION OF SYMBOLS 1 Heat sink 2a, 2b, 2c Submodule 21 IGBT chip 22 Substrate 23 Collector region 24 Emitter region 25 Gate region 26 Aluminum wire 3 Collector electrode 3 ', 3-1 Upper connection body of collector electrode 3 ", 3" -2 lower connection body of collector electrode 31 feeding conductor s slit
───────────────────────────────────────────────────── フロントページの続き (72)発明者 井上 広一 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichi Inoue 7-1, 1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory
Claims (8)
し、前記半導体素子を並列接続する半導体素子の並列接
続方法において、前記３個以上の半導体素子を並列接続
する上位と下位からなる接続体によってト−ナメント接
続し、各半導体素子の電流分担が均等に作用されるべ
く、前記上位接続体と前記下位接続体の接続点を前記下
位接続体の中心より一方に片寄らせることを特徴とする
半導体素子の並列接続方法。1. A parallel connection method of semiconductor elements, in which three or more semiconductor elements are arranged on the same substrate and the semiconductor elements are connected in parallel, the method comprises a higher order and a lower order in which the three or more semiconductor elements are connected in parallel. A tournament connection is made by a connecting body, and the connection point of the upper connecting body and the lower connecting body is deviated from the center of the lower connecting body to one side so that the current sharing of each semiconductor element acts uniformly. And parallel connection method of semiconductor devices.
し、前記半導体素子を並列接続する半導体素子の並列接
続方法において、前記３個以上の半導体素子を並列接続
する上位と下位からなる接続体によってト−ナメント接
続し、各半導体素子の電流分担が均等に作用されるべ
く、前記上位接続体と前記下位接続体の接続点を前記下
位接続体の中心より一方に片寄らせると共に、前記上位
接続体と前記下位接続体との間に相互誘導作用を起こさ
せることを特徴とする半導体素子の並列接続方法。2. A parallel connection method of semiconductor elements, in which three or more semiconductor elements are arranged on the same substrate and the semiconductor elements are connected in parallel, the method comprising a higher order and a lower order in which the three or more semiconductor elements are connected in parallel. Tournament connection by the connecting body, in order that the current sharing of each semiconductor element acts evenly, the connecting point of the upper connecting body and the lower connecting body is offset to one side from the center of the lower connecting body, and A parallel connection method of semiconductor elements, characterized in that mutual induction is caused between an upper connection body and the lower connection body.
前記半導体素子を並列接続する半導体素子の並列接続方
法において、第１の半導体素子と第３の半導体素子の中
央に第２の半導体素子を配置し、前記第１の半導体素子
と第２の半導体素子を下位接続体に接続し、前記下位接
続体の第１の引出接続点を前記第１の半導体素子と第２
の半導体素子の中間点よりも前記第１の半導体素子側と
すると共に、前記第１の引出接続点と前記第３の半導体
素子を上位接続体に接続し、前記上位接続体の第２の引
出接続点を前記第１の引出接続点と前記第３の半導体素
子の中間点より前記第１の引出接続点側とすることを特
徴とする半導体素子の並列接続方法。3. Arranging three semiconductor elements on the same substrate,
In the semiconductor element parallel connection method for connecting the semiconductor elements in parallel, a second semiconductor element is arranged in the center of the first semiconductor element and the third semiconductor element, and the first semiconductor element and the second semiconductor element are arranged. Is connected to the lower connection body, and the first lead-out connection point of the lower connection body is connected to the first semiconductor element and the second
Of the semiconductor element is closer to the first semiconductor element than the middle point of the semiconductor element, and the first lead-out connection point and the third semiconductor element are connected to a host connection body, and the second lead-out of the host connection body is connected. A parallel connection method for semiconductor elements, wherein a connection point is located closer to the first extraction connection point side than an intermediate point between the first extraction connection point and the third semiconductor element.
前記半導体素子を並列接続する半導体素子の並列接続方
法において、第１の半導体素子と第３の半導体素子の中
央に第２の半導体素子を配置し、前記第１の半導体素子
と第２の半導体素子を電極の下位接続体に接続し、前記
下位接続体の第１の引出接続点を前記第１の半導体素子
と第２の半導体素子の中間点よりも前記第１の半導体素
子側とすると共に、前記第１の引出接続点と前記第３の
半導体素子を電極の上位接続体に接続し、前記上位接続
体の第２の引出接続点を前記第１の引出接続点と前記第
３の半導体素子の中間点より前記第１の引出接続点側と
し、向かい合う前記上位接続体と前記下位接続体との間
に相互誘導作用を起こさせることを特徴とする半導体素
子の並列接続方法。4. Three semiconductor devices are arranged on the same substrate,
In the semiconductor element parallel connection method for connecting the semiconductor elements in parallel, a second semiconductor element is arranged in the center of the first semiconductor element and the third semiconductor element, and the first semiconductor element and the second semiconductor element are arranged. Is connected to the lower connection body of the electrode, and the first lead-out connection point of the lower connection body is closer to the first semiconductor element than the midpoint between the first semiconductor element and the second semiconductor element, The first lead-out connection point and the third semiconductor element are connected to an upper connection body of electrodes, and the second lead-out connection point of the upper connection body is connected to the first lead-out connection point and the third semiconductor element. A parallel connection method for semiconductor devices, characterized in that a mutual induction action is caused between the upper connection body and the lower connection body facing each other on the side closer to the first lead-out connection point than the intermediate point.
し、前記半導体素子を並列接続する半導体素子の並列接
続方法において、前記３個以上の半導体素子を並列接続
する接続体にスリットを設け、向かい合う上位と下位の
接続体を形成し、上位接続体に給電導体を接続すると共
に、下位接続体に前記３個以上の半導体素子を並列接続
し、前記給電導体から前記各半導体素子までのインピ−
ダンスが等しくなるように前記スリットを形成すること
を特徴とする半導体素子の並列接続方法。5. A method for parallel connection of semiconductor elements, wherein three or more semiconductor elements are arranged on the same substrate, and the semiconductor elements are connected in parallel, and a slit is provided in a connection body for connecting the three or more semiconductor elements in parallel. The upper and lower connection bodies are provided to face each other, the power supply conductor is connected to the upper connection body, the three or more semiconductor elements are connected in parallel to the lower connection body, and the power supply conductor to each of the semiconductor elements are connected. Impey
A method for connecting semiconductor devices in parallel, characterized in that the slits are formed so as to have an equal dance.
し、前記半導体素子を並列接続する半導体素子の並列接
続方法において、前記３個以上の半導体素子を並列接続
する接続体にスリットを設け、向かい合う上位と下位の
接続体を形成し、上位接続体に給電導体を接続すると共
に、下位接続体に前記３個以上の半導体素子を並列接続
し、前記上位接続体と前記下位接続体との間に相互誘導
作用を起こさせ、前記給電導体から前記各半導体素子ま
でのインピ−ダンスが等しくなるように前記スリットを
形成することを特徴とする半導体素子の並列接続方法。6. A method for parallel connection of semiconductor elements, wherein three or more semiconductor elements are arranged on the same substrate and the semiconductor elements are connected in parallel, and a slit is provided in a connection body for connecting the three or more semiconductor elements in parallel. The upper connection body and the lower connection body are provided with the upper connection body and the lower connection body that are opposed to each other, the feeding conductor is connected to the upper connection body, and the three or more semiconductor elements are connected in parallel to the lower connection body. A parallel connection method of semiconductor elements, wherein the slits are formed so that mutual induction action is caused between them and impedances from the power feeding conductor to each of the semiconductor elements are equalized.
前記半導体素子を並列接続する半導体素子の並列接続方
法において、第１の半導体素子と第３の半導体素子の中
央に第２の半導体素子を配置すると共に、前記３個の半
導体素子を並列接続する接続体にスリットを設け、向か
い合う上位と下位の接続体を形成し、上位接続体の中間
位置に給電導体を接続すると共に、下位接続体に前記３
個の半導体素子を並列接続し、前記上位接続体と前記下
位接続体との間に相互誘導作用を起こさせ、この際、給
電導体から第１の半導体素子までのインピ−ダンスと給
電導体から第２の半導体素子までのインピ−ダンスが等
しくなるように、上位接続体と下位接続体の接続点を下
位接続体の第１の半導体素子側とし、また、給電導体か
ら第３の半導体素子までのインピ−ダンスと給電導体か
ら第２の半導体素子までのインピ−ダンスが等しくなる
ように、上位接続体と下位接続体の接続点を下位接続体
の第３の半導体素子側とすることを特徴とする半導体素
子の並列接続方法。7. The three semiconductor elements are arranged on the same substrate,
A method for connecting semiconductor elements in parallel, wherein the semiconductor elements are connected in parallel, in which a second semiconductor element is arranged in the center of a first semiconductor element and a third semiconductor element, and the three semiconductor elements are connected in parallel. The body is provided with slits to form the upper and lower connecting bodies facing each other, the feeding conductor is connected to an intermediate position of the upper connecting body, and the lower connecting body is provided with the above-mentioned 3
A plurality of semiconductor elements are connected in parallel to cause mutual induction between the upper connection body and the lower connection body. At this time, the impedance from the feeding conductor to the first semiconductor element and the feeding conductor to the first The connection point of the upper connection body and the lower connection body is set to the first semiconductor element side of the lower connection body so that the impedance to the second semiconductor element is equal, and the connection point from the power supply conductor to the third semiconductor element is set. The connection point of the upper connection body and the lower connection body is on the third semiconductor element side of the lower connection body so that the impedance and the impedance from the power supply conductor to the second semiconductor element are equal. Method for parallel connection of semiconductor devices.
て、半導体素子は個別素子、サブモジュ−ルまたはモジ
ュ−ルであることを特徴とする半導体素子の並列接続方
法。8. The parallel connection method for semiconductor devices according to claim 1, wherein the semiconductor device is an individual device, a sub-module or a module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6064598A JPH07249735A (en) | 1994-03-08 | 1994-03-08 | Parallel connection of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6064598A JPH07249735A (en) | 1994-03-08 | 1994-03-08 | Parallel connection of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07249735A true JPH07249735A (en) | 1995-09-26 |
Family
ID=13262860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6064598A Pending JPH07249735A (en) | 1994-03-08 | 1994-03-08 | Parallel connection of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07249735A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002134568A (en) * | 2000-10-30 | 2002-05-10 | Mitsubishi Electric Corp | Semiconductor module |
| US6521992B2 (en) | 2000-04-21 | 2003-02-18 | Kabushiki Kaisha Toyoda Jidoshokki Seisakusho | Semiconductor apparatus |
| JP2006203974A (en) * | 2005-01-18 | 2006-08-03 | Fuji Electric Fa Components & Systems Co Ltd | Wiring structure of power converter |
| WO2014016925A1 (en) * | 2012-07-25 | 2014-01-30 | トヨタ自動車株式会社 | Power converter |
| US8710674B2 (en) | 2011-02-17 | 2014-04-29 | Fuji Electric Co., Ltd. | Internal wiring structure of semiconductor device |
| WO2014192118A1 (en) * | 2013-05-30 | 2014-12-04 | 三菱電機株式会社 | Semiconductor device |
| US10128625B2 (en) | 2014-11-18 | 2018-11-13 | General Electric Company | Bus bar and power electronic device with current shaping terminal connector and method of making a terminal connector |
| US11373988B2 (en) | 2018-06-01 | 2022-06-28 | Fuji Electric Co., Ltd. | Semiconductor device |
| US11521933B2 (en) | 2018-04-18 | 2022-12-06 | Fuji Electric Co., Ltd. | Current flow between a plurality of semiconductor chips |
-
1994
- 1994-03-08 JP JP6064598A patent/JPH07249735A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6521992B2 (en) | 2000-04-21 | 2003-02-18 | Kabushiki Kaisha Toyoda Jidoshokki Seisakusho | Semiconductor apparatus |
| JP2002134568A (en) * | 2000-10-30 | 2002-05-10 | Mitsubishi Electric Corp | Semiconductor module |
| JP2006203974A (en) * | 2005-01-18 | 2006-08-03 | Fuji Electric Fa Components & Systems Co Ltd | Wiring structure of power converter |
| JP4609075B2 (en) * | 2005-01-18 | 2011-01-12 | 富士電機システムズ株式会社 | Power converter wiring structure |
| US8710674B2 (en) | 2011-02-17 | 2014-04-29 | Fuji Electric Co., Ltd. | Internal wiring structure of semiconductor device |
| WO2014016925A1 (en) * | 2012-07-25 | 2014-01-30 | トヨタ自動車株式会社 | Power converter |
| JPWO2014016925A1 (en) * | 2012-07-25 | 2016-07-07 | トヨタ自動車株式会社 | Power converter |
| WO2014192118A1 (en) * | 2013-05-30 | 2014-12-04 | 三菱電機株式会社 | Semiconductor device |
| US10128625B2 (en) | 2014-11-18 | 2018-11-13 | General Electric Company | Bus bar and power electronic device with current shaping terminal connector and method of making a terminal connector |
| US11521933B2 (en) | 2018-04-18 | 2022-12-06 | Fuji Electric Co., Ltd. | Current flow between a plurality of semiconductor chips |
| US11373988B2 (en) | 2018-06-01 | 2022-06-28 | Fuji Electric Co., Ltd. | Semiconductor device |
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