JPH07249644A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07249644A JPH07249644A JP4073594A JP4073594A JPH07249644A JP H07249644 A JPH07249644 A JP H07249644A JP 4073594 A JP4073594 A JP 4073594A JP 4073594 A JP4073594 A JP 4073594A JP H07249644 A JPH07249644 A JP H07249644A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- transistor chip
- gaas
- metal film
- slit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の構造、特に
パッケージに溶着するときに反りが発生しないように改
良された半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device, and more particularly to a semiconductor device improved so as not to be warped when being welded to a package.
【０００２】[0002]
【従来の技術】半導体装置、例えばＧａＡｓ基板上にマ
イクロ波用パワートランジスタ等が形成されているＧａ
Ａｓトランジスタチップをパッケージに取り付けるに
は、図２に示すように、ＧａＡｓトランジスタチップ１
の背面の全面に金等の金属膜２を付着し、これを図３に
示すように、金錫（ＡｕＳｎ）等の半田５を使用してパ
ッケージ４に溶着する。2. Description of the Related Art A semiconductor device such as a GaAs substrate on which a power transistor for microwaves is formed.
To attach the As transistor chip to the package, as shown in FIG.
A metal film 2 made of gold or the like is attached to the entire back surface of the above, and this is welded to the package 4 using a solder 5 such as gold tin (AuSn) as shown in FIG.
【０００３】[0003]
【発明が解決しようとする課題】ＡｕＳｎ半田５を使用
して半導体装置、例えばＧａＡｓトランジスタチップを
パッケージ４に溶着する際に、ＧａＡｓトランジスタチ
ップ１の背面に付着された金等の金属とチップ基板のＧ
ａＡｓとの膨張係数の違いによってＧａＡｓトランジス
タチップ１は図３に示すように反り易い。ＧａＡｓトラ
ンジスタチップの縦と横の長さの比が小さい間は、Ｇａ
Ａｓトランジスタチップをピンセットで押さえながらパ
ッケージに溶着することで、ある程度反りを抑えること
ができた。When a semiconductor device, for example, a GaAs transistor chip is welded to the package 4 by using the AuSn solder 5, a metal such as gold attached to the back surface of the GaAs transistor chip 1 and the chip substrate. G
Due to the difference in expansion coefficient from aAs, the GaAs transistor chip 1 tends to warp as shown in FIG. As long as the ratio of the length to the width of the GaAs transistor chip is small, Ga
Warping could be suppressed to some extent by welding the As transistor chip to the package while pressing it with tweezers.
【０００４】しかしながら、ＧａＡｓトランジスタの高
周波化、高出力化が進むにつれてＧａＡｓトランジスタ
チップの横（長手方向）の長さが大きくなり、縦と横の
長さの比が従来の１：４．４２から１：５．６３と約３
０％も大きくなってきたので、これまでの方法で反らず
に溶着することは難しくなってきた。However, the lateral (longitudinal direction) length of the GaAs transistor chip becomes larger as the frequency and output of the GaAs transistor become higher, and the ratio of the longitudinal length to the lateral length is changed from the conventional 1: 4.42. 1: 5.63 and about 3
Since it has increased by 0%, it has become difficult to weld it without warping by the conventional method.
【０００５】ＧａＡｓトランジスタチップが反ると、図
３に示すように、ＧａＡｓトランジスタチップ１とパッ
ケージ４との間に形成されるＡｕＳｎ半田膜５の厚さが
部分的に厚くなって熱抵抗が増大するという問題やＧａ
Ａｓトランジスタチップ１に歪みが発生してトランジス
タの性能に悪影響を及ぼすという問題が発生する。When the GaAs transistor chip is warped, as shown in FIG. 3, the thickness of the AuSn solder film 5 formed between the GaAs transistor chip 1 and the package 4 is partially increased and the thermal resistance is increased. The problem of doing and Ga
There is a problem that distortion occurs in the As transistor chip 1 and the performance of the transistor is adversely affected.
【０００６】本発明の目的は、この欠点を解消すること
にあり、パッケージに溶着したときに反りが発生しない
ように改良された半導体装置を提供することにある。An object of the present invention is to eliminate this drawback, and to provide a semiconductor device improved so that no warpage occurs when it is welded to a package.
【０００７】[0007]
【課題を解決するための手段】上記の目的は、背面に金
属膜が付着されている半導体装置において、前記の金属
膜（２）がスリット（３）により複数領域に分割されて
いることによって達成される。The above object is achieved by a semiconductor device having a metal film attached to the back surface thereof, in which the metal film (2) is divided into a plurality of regions by slits (3). To be done.
【０００８】なお、前記のスリット（３）は、前記の半
導体装置（１）の外周形状における短辺に平行に形成さ
れていることが好ましく、また、前記のスリット（３）
の幅の合計長さが、前記の半導体装置（１）の長手方向
の長さの０．７〜１．０％であることが好ましい。The slit (3) is preferably formed parallel to the short side of the outer peripheral shape of the semiconductor device (1), and the slit (3) is also formed.
It is preferable that the total length of the widths is 0.7 to 1.0% of the length of the semiconductor device (1) in the longitudinal direction.
【０００９】[0009]
【作用】半導体装置の基板材料、例えばＧａＡｓと背面
に付着されている金属膜の材料、例えば金との膨張係数
の差により半導体装置に発生する曲げ応力は、金属膜２
がスリット３によって半導体装置の長手方向に複数領域
に分割されることによって半導体装置に分散して作用
し、半導体装置全体に発生する反りが抑制される。The bending stress generated in the semiconductor device due to the difference in expansion coefficient between the substrate material of the semiconductor device, for example, GaAs, and the material of the metal film attached to the back surface, for example, gold, is caused by the metal film 2.
Are divided into a plurality of regions in the longitudinal direction of the semiconductor device by the slits 3 and act in a distributed manner on the semiconductor device, and warpage occurring in the entire semiconductor device is suppressed.
【００１０】金の膨張係数をαAUとすると、長さｌO の
金膜がΔｔの温度変化によって伸びる長さΔｌは、[0010] The expansion coefficient of gold When alpha AU, length Δl gold film length l O stretches due to a temperature change of Δt is
【００１１】[0011]
【数１】Δｌ＝αAU・ｌO ・Δｔ となる。半導体装置１をＡｕＳｎ半田５を使用してパッ
ケージ４に溶着するときの温度は３５０℃程度であり、
金の膨張係数αAUは５００Ｋで１５．４×１０-6である
ので、Δｔ＝４００℃、αAU≒１６×１０-6として金膜
の伸びΔｌを求めると０．００６４ｌO となる。したが
って、金膜２に形成するスリット３の幅の合計長さが半
導体装置１の長手方向の長さの０．７〜１．０％になる
ようにスリット３を形成すれば、隣接する金膜２が膨張
時に相互に接触して押し合うことはない。[Formula 1] Δl = α AU · l O · Δt. The temperature when the semiconductor device 1 is welded to the package 4 using the AuSn solder 5 is about 350 ° C.,
Since the expansion coefficient α AU of gold is 15.4 × 10 −6 at 500 K, the elongation Δl of the gold film is 0.0064 l O when Δt = 400 ° C. and α AU ≈16 × 10 −6 . Therefore, if the slits 3 are formed such that the total width of the slits 3 formed in the gold film 2 is 0.7 to 1.0% of the length of the semiconductor device 1 in the longitudinal direction, the adjacent gold films 2 The two do not come into contact with each other and expand when they expand.
【００１２】なお、本発明に係る半導体装置に使用され
る基板はＧａＡｓに限定されるものではなく、すべての
半導体に適用されるものであるが、中でも、もろい性質
を有するＧａＡｓ、ＩｎＰ等の化合物半導体が使用され
る場合には、本発明に係る反りの抑制方法は特に有効で
ある。The substrate used in the semiconductor device according to the present invention is not limited to GaAs but is applicable to all semiconductors. Among them, compounds such as GaAs and InP having a fragile property are used. The warp suppressing method according to the present invention is particularly effective when a semiconductor is used.
【００１３】[0013]
【実施例】以下、図面を参照して、本発明の一実施例に
係るＧａＡｓトランジスタチップについて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A GaAs transistor chip according to an embodiment of the present invention will be described below with reference to the drawings.
【００１４】図１（ａ）参照 図１（ａ）において、１は図示されていないがＧａＡｓ
基板上にマイクロ波用パワートランジスタ等が形成され
ているＧａＡｓトランジスタチップであり、２はＧａＡ
ｓトランジスタチップの背面に付着された金膜であり、
金膜２はＧａＡｓトランジスタチップ１の短辺に平行に
形成されたスリット３によって複数領域に分割されてい
る。Referring to FIG. 1A, in FIG. 1A, 1 is not shown, but GaAs
A GaAs transistor chip in which microwave power transistors and the like are formed on a substrate, and 2 is GaA
A gold film attached to the back of the s-transistor chip,
The gold film 2 is divided into a plurality of regions by a slit 3 formed in parallel with the short side of the GaAs transistor chip 1.
【００１５】１例としてＧａＡｓトランジスタチップ１
の長手方向の長さが３ｍｍの場合には、スリット３の幅
の合計長さｌs が、As an example, a GaAs transistor chip 1
When the length in the longitudinal direction of is 3 mm, the total length l s of the widths of the slits 3 is
【００１６】[0016]
【数２】ｌs ＝３０００×（０．００７〜０．０１）＝
２１〜３０μｍ となるようにスリット３を形成する。例えば、幅が５μ
ｍのスリット３を５個所もしくは６個所形成すればよ
い。## EQU2 ## l s = 3000 × (0.007 to 0.01) =
The slit 3 is formed to have a thickness of 21 to 30 μm. For example, the width is 5μ
The slit 3 of m may be formed at 5 or 6 positions.
【００１７】図１（ｂ）参照 図１（ｂ）はＧａＡｓトランジスタチップ１がパッケー
ジ４にＡｕＳｎ半田５によって溶着された状態を示し、
ＧａＡｓトランジスタチップ１の反りは従来例に比べて
抑制される。FIG. 1B shows a state in which the GaAs transistor chip 1 is welded to the package 4 by AuSn solder 5,
The warpage of the GaAs transistor chip 1 is suppressed as compared with the conventional example.
【００１８】なお、金膜２に形成するスリット３の形状
については、図１に示す形状の他に、図４に示すように
リング状に形成したもの、図５に示すように格子状に形
成したもの、図６に示すようにリング状のスリットをマ
トリックス状に形成したもの、図７に示すようにチップ
一辺の長さより短いスリットを交互に形成したもの、ま
たは、図８に示すように斜め格子状に形成したものでも
よく、要は半導体装置の外形内に描かれる直線のうち、
最短のものよりも長い直線を１本または複数本のスリッ
トで横断するようにすれば半導体装置の作用する曲げ応
力を半導体装置上に分散作用させることができ、反りを
抑制することができる。Regarding the shape of the slits 3 formed in the gold film 2, in addition to the shape shown in FIG. 1, a ring-shaped one as shown in FIG. 4 and a lattice-shaped one as shown in FIG. 6, the ring-shaped slits are formed in a matrix as shown in FIG. 6, the slits shorter than the length of one side of the chip are alternately formed as shown in FIG. 7, or the slant is formed as shown in FIG. It may be formed in a lattice shape, in short, among the straight lines drawn in the outer shape of the semiconductor device,
If a straight line longer than the shortest one is traversed by one or a plurality of slits, the bending stress exerted by the semiconductor device can be dispersed on the semiconductor device and warpage can be suppressed.
【００１９】[0019]
【発明の効果】以上説明したとおり、本発明に係る半導
体装置においては、半導体装置の背面に付着された金属
膜がスリットによって複数領域に分割されているので、
半導体装置の基板と金属膜との膨張係数の違いによって
半導体装置に作用する曲げ応力が半導体装置上に分散さ
れるので、半導体装置に発生する反りが低減されて熱抵
抗の増大や歪みによる性能劣化が抑制され、半導体装置
の信頼性の向上に寄与するところが大きい。As described above, in the semiconductor device according to the present invention, since the metal film attached to the back surface of the semiconductor device is divided into a plurality of regions by the slits,
Since the bending stress acting on the semiconductor device is dispersed on the semiconductor device due to the difference in the expansion coefficient between the substrate and the metal film of the semiconductor device, the warpage occurring in the semiconductor device is reduced and the thermal resistance increases or the performance deteriorates due to strain. Is suppressed and contributes to the improvement of the reliability of the semiconductor device.
【図１】（ａ）は本発明に係るＧａＡｓトランジスタチ
ップの断面図であり、（ｂ）はＧａＡｓトランジスタチ
ップをパッケージに溶着した状態の断面図である。FIG. 1A is a sectional view of a GaAs transistor chip according to the present invention, and FIG. 1B is a sectional view showing a state in which a GaAs transistor chip is welded to a package.
【図２】従来技術に係るＧａＡｓトランジスタチップの
断面図である。FIG. 2 is a cross-sectional view of a GaAs transistor chip according to the related art.
【図３】従来技術に係るＧａＡｓトランジスタチップを
パッケージに溶着した状態の断面図である。FIG. 3 is a cross-sectional view showing a state in which a GaAs transistor chip according to a conventional technique is welded to a package.
【図４】金属膜に形成されたスリットの形状を示す平面
図である。FIG. 4 is a plan view showing a shape of a slit formed in a metal film.
【図５】金属膜に形成されたスリットの形状を示す平面
図である。FIG. 5 is a plan view showing a shape of a slit formed in a metal film.
【図６】金属膜に形成されたスリットの形状を示す平面
図である。FIG. 6 is a plan view showing a shape of a slit formed in a metal film.
【図７】金属膜に形成されたスリットの形状を示す平面
図である。FIG. 7 is a plan view showing a shape of a slit formed in a metal film.
【図８】金属膜に形成されたスリットの形状を示す平面
図である。FIG. 8 is a plan view showing a shape of a slit formed in a metal film.
１ 半導体装置（ＧａＡｓトランジスタチップ） ２ 金属膜（金膜） ３ スリット ４ パッケージ ５ ＡｕＳｎ半田 1 Semiconductor Device (GaAs Transistor Chip) 2 Metal Film (Gold Film) 3 Slit 4 Package 5 AuSn Solder
Claims (3)
置において、 前記金属膜（２）がスリット（３）により複数領域に分
割されてなることを特徴とする半導体装置。1. A semiconductor device having a metal film attached to a back surface thereof, wherein the metal film (2) is divided into a plurality of regions by slits (3).
（１）の外周形状における短辺に平行に形成されてなる
ことを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the slit (3) is formed parallel to a short side of the outer peripheral shape of the semiconductor device (1).
前記半導体装置（１）の長手方向の長さの０．７〜１．
０％であることを特徴とする請求項１または２記載の半
導体装置。3. The total width of the slits (3) is
0.7 to 1. of the length in the longitudinal direction of the semiconductor device (1).
It is 0%, The semiconductor device of Claim 1 or 2 characterized by the above-mentioned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4073594A JP3302815B2 (en) | 1994-03-11 | 1994-03-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4073594A JP3302815B2 (en) | 1994-03-11 | 1994-03-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07249644A true JPH07249644A (en) | 1995-09-26 |
| JP3302815B2 JP3302815B2 (en) | 2002-07-15 |
Family
ID=12588899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4073594A Expired - Fee Related JP3302815B2 (en) | 1994-03-11 | 1994-03-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3302815B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008132559A1 (en) * | 2007-04-27 | 2008-11-06 | Freescale Semiconductor, Inc. | Semiconductor wafer processing |
-
1994
- 1994-03-11 JP JP4073594A patent/JP3302815B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008132559A1 (en) * | 2007-04-27 | 2008-11-06 | Freescale Semiconductor, Inc. | Semiconductor wafer processing |
| US8456023B2 (en) | 2007-04-27 | 2013-06-04 | Freescale Semiconductor, Inc. | Semiconductor wafer processing |
| TWI452637B (en) * | 2007-04-27 | 2014-09-11 | Freescale Semiconductor Inc | Semiconductor wafer processing |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3302815B2 (en) | 2002-07-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5652452A (en) | Semiconductor device with pluralities of gate electrodes | |
| JP2757805B2 (en) | Semiconductor device | |
| WO2010007916A1 (en) | Semiconductor device and display device | |
| JP3302815B2 (en) | Semiconductor device | |
| JPH05152461A (en) | Ceramic circuit board | |
| JP3274633B2 (en) | Semiconductor integrated circuit device | |
| JPH08222658A (en) | Semiconductor element package and production thereof | |
| JP4855179B2 (en) | Array type semiconductor laser device | |
| JPH0529506A (en) | Semiconductor device | |
| JP3003114B2 (en) | Lead frame | |
| JP2713200B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH06224359A (en) | Semiconductor device | |
| JPH11204704A (en) | Semiconductor device | |
| JPS63140556A (en) | Semiconductor device | |
| WO2021079427A1 (en) | Semiconductor device | |
| JPH07193315A (en) | Semiconductor laser system and manufacture thereof | |
| JP3070566B2 (en) | Semiconductor device | |
| JPH07288299A (en) | Semiconductor device | |
| JP3302811B2 (en) | Microwave semiconductor device | |
| JP2000124370A (en) | Package for semiconductor device | |
| JP2003151998A (en) | Method for manufacturing semiconductor device | |
| JPH05299445A (en) | Semiconductor device sealed with resin | |
| JPH0737908A (en) | Semiconductor element | |
| JPH07320542A (en) | Directly copper bonded substrate | |
| JPS6373651A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20020416 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080426 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090426 Year of fee payment: 7 |
|
| LAPS | Cancellation because of no payment of annual fees |