JPH07235406A - Chip capacitive varistor - Google Patents
Chip capacitive varistorInfo
- Publication number
- JPH07235406A JPH07235406A JP6028124A JP2812494A JPH07235406A JP H07235406 A JPH07235406 A JP H07235406A JP 6028124 A JP6028124 A JP 6028124A JP 2812494 A JP2812494 A JP 2812494A JP H07235406 A JPH07235406 A JP H07235406A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- chip
- capacitive varistor
- forming
- varistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、容量性バリスタが内蔵
されたチップ容量性バリスタに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip capacitive varistor having a built-in capacitive varistor.
【０００２】[0002]
【従来の技術】従来より、電子楽器のノイズ及びサージ
対策用としてバリスタが使用されている。従来は、チッ
プコンデンサとチップバリスタが基板上に必要な場合、
１回路につき各々１個ずつ実装されていた。2. Description of the Related Art Conventionally, a varistor has been used as a countermeasure for noise and surge of electronic musical instruments. Conventionally, when chip capacitors and chip varistors are required on the board,
One was mounted for each circuit.
【０００３】[0003]
【発明が解決しようとする課題】ところが、上述のよう
に、従来はノイズ、サージ対策用として、１回路に各々
１個ずつ基板に実装していたため実装密度が低いという
問題を抱えていた。本発明は、上記事情に鑑み、実装密
度を向上させることのできるノイズ，サージ対策用素子
としてのチップ容量性バリスタを提供することを目的と
する。However, as described above, there has been a problem that the mounting density is low because conventionally, one circuit is mounted on each circuit board for noise and surge protection. In view of the above circumstances, it is an object of the present invention to provide a chip capacitive varistor as a noise / surge countermeasure element capable of improving the packaging density.
【０００４】[0004]
【課題を解決するための手段】上記目的を達成する本発
明のチップ容量性バリスタは、 （１）電圧非直線性抵抗磁器を有するシート状の基体 （２）基体を挟む、各ペアを構成する少なくとも一方ど
うしが互いに電気的に非接触に形成された複数ペアの内
部電極 を備えたことを特徴とするチップ容量性バリスタ。The chip capacitive varistor of the present invention which achieves the above object comprises (1) a sheet-shaped substrate having a voltage non-linear resistance porcelain, and (2) a pair of substrates sandwiching the substrate. A chip capacitive varistor, characterized in that at least one of them is provided with a plurality of pairs of internal electrodes which are formed in electrical contact with each other.
【０００５】ここで、上記電圧非直線性抵抗磁器は、酸
化チタン、酸化セリウムを基本成分とした焼結体であっ
て、その基本成分組成が、酸化セリウムをＣｅＯ2 に換
算して０．０２〜２０．０モル％含み、残部が酸化チタ
ンであることが好ましい。あるいは、上記電圧非直線性
抵抗磁器は、酸化チタン、酸化セリウム及び半導体化元
素酸化物を基本成分とした焼結体であって、その基本成
分組成が、酸化セリウムをＣｅＯ2 に換算して０．０２
〜２０．０モル％、半導体化元素酸化物をＭ2 Ｏ5 に換
算して０．５０モル％以下含み、残部が酸化チタンであ
ってもよい。The voltage non-linear resistance porcelain is a sintered body containing titanium oxide and cerium oxide as basic components, and the basic component composition is 0.02 when cerium oxide is converted into CeO 2. It is preferable that the content is ˜20.0 mol% and the balance is titanium oxide. Alternatively, the voltage non-linear resistance porcelain is a sintered body containing titanium oxide, cerium oxide, and a semiconducting element oxide as basic components, and the basic component composition thereof is 0 when cerium oxide is converted into CeO 2. .02
˜20.0 mol%, 0.50 mol% or less of the semiconducting element oxide in terms of M 2 O 5 may be contained, and the balance may be titanium oxide.
【０００６】[0006]
【作用】本発明のチップ容量性バリスタは、基板が電圧
非直線性抵抗磁器を含み、その基板の一面に電気的に非
接触の複数の内部電極が形成されており、したがって１
つのチップ内に複数のチップ容量性バリスタが形成され
ている。このため１つの素子で複数回路のノイズ，サー
ジ対策を行うことができ、回路基板への実装密度が向上
する。In the chip capacitive varistor of the present invention, the substrate includes a voltage non-linear resistance porcelain, and a plurality of electrically non-contacting internal electrodes are formed on one surface of the substrate.
Multiple chip capacitive varistors are formed in one chip. Therefore, one element can be used to prevent noise and surge in a plurality of circuits, and the mounting density on the circuit board is improved.
【０００７】[0007]
【実施例】以下、本発明の実施例について説明する。図
１は、２つの容量性バリスタ素子が内蔵されたチップ容
量性バリスタの各グリーンシートの例を示した図、図２
はその外観斜視図、図３はその等価回路図である。EXAMPLES Examples of the present invention will be described below. FIG. 1 is a diagram showing an example of each green sheet of a chip capacitive varistor in which two capacitive varistor elements are incorporated, FIG.
Is an external perspective view thereof, and FIG. 3 is an equivalent circuit diagram thereof.
【０００８】ここでは図示の４枚のグリーンシート１〜
４が用意される。それらのグリーンシート１〜４には、
ポリエステルのベースシートに後述する電圧非直線性抵
抗磁器材料のスラリーをドクターブレード法により印刷
し、乾燥することにより形成される。ここで用いる電圧
非直線性抵抗磁器材料としては、例えばＴｉＯ2 ９９．
４８モル％、Ｓｂ2 Ｏ5 ０．１２モル％、ＣｅＯ2 ０．
４０モル％のものが採用され、これにさらに焼結材とし
て、ＳｉＯ2 を０．５重量％、ＳｒＣＯ2 ３〜７％が加
えられる。尚、電圧非直線性抵抗磁器材料の詳細につい
ては、特開昭６１−１７４６０１号公報を参照された
い。Here, four green sheets 1 to 1 are shown.
4 is prepared. In those green sheets 1-4,
It is formed by printing a slurry of a voltage non-linear resistance porcelain material described below on a polyester base sheet by a doctor blade method and drying. The voltage non-linear resistance porcelain material used here is, for example, TiO 2 99.
48 mol%, Sb 2 O 5 0.12 mol%, CeO 2 0.
40 mol% is used, and 0.5 wt% of SiO 2 and 3 to 7% of SrCO 2 are further added as a sintering material. For details of the voltage non-linear resistance porcelain material, refer to Japanese Patent Application Laid-Open No. 61-174601.
【０００９】それら４枚のグリーンシート１〜４のうち
グリーンシート２，３には、電圧非直線性抵抗磁器材料
を印刷、乾燥した後、さらに、それぞれ図示の形状とな
るように導電性ペーストをドクターブレード法により印
刷、乾燥し、これにより内部電極５，６ａ，６ｂが形成
される。これらの内部電極５，６ａ，６ｂのうち、グリ
ーンシート２を形成する電圧非直線性抵抗磁器材料を挟
む、内部電極５，６ａのペア、内部電極５，６ｂのペア
により、それぞれ、図３に示す等価回路中の容量性バリ
スタ素子１１，１２が構成される。Of the four green sheets 1 to 4, the green sheets 2 and 3 are printed with a voltage non-linear resistance porcelain material and dried, and then a conductive paste is further applied so as to have the illustrated shapes. Printing and drying are carried out by the doctor blade method, whereby internal electrodes 5, 6a, 6b are formed. Of these internal electrodes 5, 6a, 6b, the pair of internal electrodes 5, 6a and the pair of internal electrodes 5, 6b sandwiching the voltage non-linear resistance porcelain material forming the green sheet 2 are respectively shown in FIG. The capacitive varistor elements 11 and 12 in the equivalent circuit shown are configured.
【００１０】以上のようにして形成された４枚のグリー
ンシート１〜４が互いに積層されて熱圧着により一体化
された後、８７０℃２時間焼成され、焼結体が得られ
る。その焼結体をバレル研磨してその焼結体の側面から
内部電極５，６ａ，６ｂを露出させ、それらの内部電極
５，６ａ，６ｂが露出した部分にＡｇを主成分とした導
電性ペーストを塗布し、これにより、図２に示すよう
に、内部電極６ａ，６ｂとそれぞれ接続された電極７，
８および内部電極５と接続された電極９ａ，９ｂを形成
する。これにより、図２に示す形状の容量性バリスタ素
子が２素子内蔵されたチップ容量性バリスタ１０が完成
する。The four green sheets 1 to 4 thus formed are stacked on each other and integrated by thermocompression bonding, and then fired at 870 ° C. for 2 hours to obtain a sintered body. The sintered body is barrel-polished to expose the internal electrodes 5, 6a, 6b from the side surface of the sintered body, and the conductive paste containing Ag as a main component in the exposed portions of the internal electrodes 5, 6a, 6b. As a result, as shown in FIG. 2, the electrodes 7 connected to the internal electrodes 6a and 6b,
8 and electrodes 9a and 9b connected to the internal electrode 5 are formed. As a result, the chip capacitive varistor 10 having two built-in capacitive varistor elements having the shape shown in FIG. 2 is completed.
【００１１】なお、本発明のチップ容量性バリスタは、
２つの容量性バリスタ素子を内蔵するものに限られるも
のではなく、それ以上の数の容量性バリスタを内蔵する
ものであってもよい。The chip capacitive varistor of the present invention is
The number of capacitive varistor elements is not limited to the one that incorporates two capacitive varistor elements, and the number of capacitive varistor elements greater than that may be incorporated.
【００１２】[0012]
【発明の効果】以上説明したように、本発明のチップ容
量性バリスタは、複数の容量性バリスタ素子を内蔵した
ものであるため、１つのチップ部品で複数回路のノイ
ズ，サージ対策を行うことができ、実装密度の向上が図
られる。As described above, since the chip capacitive varistor of the present invention incorporates a plurality of capacitive varistor elements, it is possible to take measures against noise and surge in a plurality of circuits with one chip component. Therefore, the packaging density can be improved.
【図１】２つの容量性バリスタ素子が内蔵されたチップ
容量性バリスタの各グリーンシートの例を示した図であ
る。FIG. 1 is a diagram showing an example of each green sheet of a chip capacitive varistor in which two capacitive varistor elements are incorporated.
【図２】チップ容量性バリスタの外観斜視図である。FIG. 2 is an external perspective view of a chip capacitive varistor.
【図３】チップ容量性バリスタの等価回路図である。FIG. 3 is an equivalent circuit diagram of a chip capacitive varistor.
１，…，４ グリーンシート ５，６ａ，６ｂ 内部電極 ７，８，９ａ，９ｂ 電極 １０ チップ容量性バリスタ 1, ..., 4 Green sheet 5,6a, 6b Internal electrode 7,8,9a, 9b Electrode 10 Chip capacitive varistor
Claims (1)
の基体と、 前記基体を挟む、各ペアを構成する少なくとも一方どう
しが互いに電気的に非接触に形成された複数ペアの内部
電極とを備えたことを特徴とするチップ容量性バリス
タ。1. A sheet-shaped substrate having a voltage non-linear resistance porcelain, and a plurality of pairs of internal electrodes sandwiching the substrate, at least one of which constitutes each pair and which is formed in electrical non-contact with each other. Chip capacitive varistor characterized by having.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6028124A JPH07235406A (en) | 1994-02-25 | 1994-02-25 | Chip capacitive varistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6028124A JPH07235406A (en) | 1994-02-25 | 1994-02-25 | Chip capacitive varistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07235406A true JPH07235406A (en) | 1995-09-05 |
Family
ID=12240048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6028124A Pending JPH07235406A (en) | 1994-02-25 | 1994-02-25 | Chip capacitive varistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07235406A (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6331926B1 (en) | 1997-04-08 | 2001-12-18 | Anthony A. Anthony | Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package |
| US6346871B1 (en) * | 1998-01-09 | 2002-02-12 | Tdk Corporation | Laminate type varistor |
| US6373673B1 (en) | 1997-04-08 | 2002-04-16 | X2Y Attenuators, Llc | Multi-functional energy conditioner |
| US6498710B1 (en) | 1997-04-08 | 2002-12-24 | X2Y Attenuators, Llc | Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package |
| US6509807B1 (en) * | 1997-04-08 | 2003-01-21 | X2Y Attenuators, Llc | Energy conditioning circuit assembly |
| US6580595B2 (en) | 1997-04-08 | 2003-06-17 | X2Y Attenuators, Llc | Predetermined symmetrically balanced amalgam with complementary paired portions comprising shielding electrodes and shielded electrodes and other predetermined element portions for symmetrically balanced and complementary energy portion conditioning |
| US6603646B2 (en) | 1997-04-08 | 2003-08-05 | X2Y Attenuators, Llc | Multi-functional energy conditioner |
| US6636406B1 (en) | 1997-04-08 | 2003-10-21 | X2Y Attenuators, Llc | Universal multi-functional common conductive shield structure for electrical circuitry and energy conditioning |
| US6650525B2 (en) | 1997-04-08 | 2003-11-18 | X2Y Attenuators, Llc | Component carrier |
| US6687108B1 (en) | 1997-04-08 | 2004-02-03 | X2Y Attenuators, Llc | Passive electrostatic shielding structure for electrical circuitry and energy conditioning with outer partial shielded energy pathways |
| US6738249B1 (en) | 1997-04-08 | 2004-05-18 | X2Y Attenuators, Llc | Universal energy conditioning interposer with circuit architecture |
| KR100470115B1 (en) * | 2003-07-30 | 2005-02-04 | 주식회사 이노칩테크놀로지 | Laminated chip element with various equivalent inductance |
| US6995983B1 (en) | 1997-04-08 | 2006-02-07 | X2Y Attenuators, Llc | Component carrier |
| US9001486B2 (en) | 2005-03-01 | 2015-04-07 | X2Y Attenuators, Llc | Internally overlapped conditioners |
| US9019679B2 (en) | 1997-04-08 | 2015-04-28 | X2Y Attenuators, Llc | Arrangement for energy conditioning |
| US9036319B2 (en) | 1997-04-08 | 2015-05-19 | X2Y Attenuators, Llc | Arrangement for energy conditioning |
| US9054094B2 (en) | 1997-04-08 | 2015-06-09 | X2Y Attenuators, Llc | Energy conditioning circuit arrangement for integrated circuit |
-
1994
- 1994-02-25 JP JP6028124A patent/JPH07235406A/en active Pending
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6636406B1 (en) | 1997-04-08 | 2003-10-21 | X2Y Attenuators, Llc | Universal multi-functional common conductive shield structure for electrical circuitry and energy conditioning |
| US9373592B2 (en) | 1997-04-08 | 2016-06-21 | X2Y Attenuators, Llc | Arrangement for energy conditioning |
| US6331926B1 (en) | 1997-04-08 | 2001-12-18 | Anthony A. Anthony | Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package |
| US6498710B1 (en) | 1997-04-08 | 2002-12-24 | X2Y Attenuators, Llc | Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package |
| US6509807B1 (en) * | 1997-04-08 | 2003-01-21 | X2Y Attenuators, Llc | Energy conditioning circuit assembly |
| US6580595B2 (en) | 1997-04-08 | 2003-06-17 | X2Y Attenuators, Llc | Predetermined symmetrically balanced amalgam with complementary paired portions comprising shielding electrodes and shielded electrodes and other predetermined element portions for symmetrically balanced and complementary energy portion conditioning |
| US6594128B2 (en) | 1997-04-08 | 2003-07-15 | X2Y Attenuators, Llc | Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package |
| US6603646B2 (en) | 1997-04-08 | 2003-08-05 | X2Y Attenuators, Llc | Multi-functional energy conditioner |
| US6373673B1 (en) | 1997-04-08 | 2002-04-16 | X2Y Attenuators, Llc | Multi-functional energy conditioner |
| US6650525B2 (en) | 1997-04-08 | 2003-11-18 | X2Y Attenuators, Llc | Component carrier |
| US6738249B1 (en) | 1997-04-08 | 2004-05-18 | X2Y Attenuators, Llc | Universal energy conditioning interposer with circuit architecture |
| US6687108B1 (en) | 1997-04-08 | 2004-02-03 | X2Y Attenuators, Llc | Passive electrostatic shielding structure for electrical circuitry and energy conditioning with outer partial shielded energy pathways |
| US9054094B2 (en) | 1997-04-08 | 2015-06-09 | X2Y Attenuators, Llc | Energy conditioning circuit arrangement for integrated circuit |
| US6995983B1 (en) | 1997-04-08 | 2006-02-07 | X2Y Attenuators, Llc | Component carrier |
| US9036319B2 (en) | 1997-04-08 | 2015-05-19 | X2Y Attenuators, Llc | Arrangement for energy conditioning |
| US9019679B2 (en) | 1997-04-08 | 2015-04-28 | X2Y Attenuators, Llc | Arrangement for energy conditioning |
| US6346871B1 (en) * | 1998-01-09 | 2002-02-12 | Tdk Corporation | Laminate type varistor |
| KR100470115B1 (en) * | 2003-07-30 | 2005-02-04 | 주식회사 이노칩테크놀로지 | Laminated chip element with various equivalent inductance |
| US9001486B2 (en) | 2005-03-01 | 2015-04-07 | X2Y Attenuators, Llc | Internally overlapped conditioners |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20010201 |