JPH07226400A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH07226400A JPH07226400A JP5147567A JP14756793A JPH07226400A JP H07226400 A JPH07226400 A JP H07226400A JP 5147567 A JP5147567 A JP 5147567A JP 14756793 A JP14756793 A JP 14756793A JP H07226400 A JPH07226400 A JP H07226400A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- chip
- wiring
- melting point
- solder ball
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体実装技術に係
り、特に、フリップチップ実装において、基板上の配線
とチップとの接続性を良くし、接続不良を発生しないよ
うにした半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting technique, and more particularly, in flip chip mounting, a semiconductor device which improves the connectivity between a wiring on a substrate and a chip and prevents a defective connection from occurring. It relates to a manufacturing method.
【０００２】[0002]
【従来の技術】ＬＳＩチップを基板上の配線と一度に接
続する方法として、フリップチップ実装あるいはＣＣＢ
（Controlled Collapse Bonding ）と呼ばれる方法があ
るが、これは図１に示すように、パッシベーション膜１
０で覆われたチップ１２のＡl電極１４上に、ハンダボ
ール１６を蒸着によって形成し、これを基板１８上の配
線２０と相対応させて、位置合わせを行い、熱処理炉を
通すことにより、高温雰囲気中でハンダを融かし圧着す
ることにより、接続するものである。2. Description of the Related Art As a method of connecting an LSI chip to wiring on a substrate at once, flip chip mounting or CCB is used.
There is a method called (Controlled Collapse Bonding), which is used for the passivation film 1 as shown in FIG.
A solder ball 16 is formed on the Al electrode 14 of the chip 12 covered with 0 by vapor deposition, and the solder ball 16 is aligned with the wiring 20 on the substrate 18, aligned, and passed through a heat treatment furnace to obtain a high temperature. The connection is made by melting and crimping solder in the atmosphere.
【０００３】ここで、ハンダボールはウェハプロセスの
最終工程でチップ上に一括形成される。従って、電極の
数に依存せず、一度に接続が可能であり、チップの実装
が極めて小容積にできる。Here, the solder balls are collectively formed on the chips in the final step of the wafer process. Therefore, it is possible to connect at one time without depending on the number of electrodes, and the chip can be mounted in an extremely small volume.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、ＣＣＢ
でのハンダを介しての接続は、高温雰囲気の中で周囲よ
り熱を加えるので、表面は暖まるのに芯は暖まっておら
ず、熱分布が不均一で、それが接続不良の原因となり、
更に一般のパッケージリードと配線の接続と異なり、目
視等による後からのチェックが難しいという問題点があ
った。However, the CCB
When connecting via solder in, heat is applied from the surroundings in a high temperature atmosphere, so the surface is warm but the core is not warm, the heat distribution is non-uniform, which causes poor connection,
Further, unlike the general connection between the package lead and the wiring, there is a problem that it is difficult to check later by visual inspection or the like.
【０００５】本発明は、前記従来の問題点を解決するべ
くなされたもので、配線とチップとを加熱圧着する際の
ハンダボールに加わる熱の不均一を緩和し、配線とチッ
プの接続性を良くし、接続不良を発生しないようにした
半導体装置及びその製造方法を提供することを目的とす
る。The present invention has been made to solve the above-mentioned conventional problems, and alleviates unevenness of heat applied to a solder ball when the wiring and the chip are heated and pressure-bonded, thereby improving the connectivity between the wiring and the chip. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that are improved and prevent connection failure.
【０００６】[0006]
【課題を解決するための手段】本発明は、フリップチッ
プ実装により、ＬＳＩチップを基板上の配線に接続して
作られる半導体装置において、ＬＳＩチップ上に形成さ
れるハンダボールが、積層されるようにして前記目的を
達成したものである。According to the present invention, in a semiconductor device made by connecting an LSI chip to wiring on a substrate by flip chip mounting, solder balls formed on the LSI chip are stacked. The above-mentioned object was achieved.
【０００７】本発明は、又、フリップチップ実装によ
り、ＬＳＩチップを基板上の配線に接続して作られる半
導体装置の製造方法において、ＬＳＩチップ上に形成さ
れるハンダボールを、該チップから離れると、融点が高
くなるように多層のハンダで構成し、チップと基板を加
熱圧着する際に、ハンダボールが均一に融けるようにし
た、配線接続工程を含むことにより、同様に前記目的を
達成したものである。The present invention also provides a method of manufacturing a semiconductor device, which is manufactured by connecting an LSI chip to a wiring on a substrate by flip-chip mounting, when a solder ball formed on the LSI chip is separated from the chip. In order to achieve the same purpose as above, by including a wiring connecting step, which is composed of multi-layered solder so that the melting point becomes high, and the solder balls are uniformly melted when the chip and the substrate are heat-pressed. Is.
【０００８】[0008]
【作用】本発明によれば、チップ上に形成するハンダボ
ール１６を図２に示すように、融点の異なるハンダ１６
Ａ、１６Ｂ、１６Ｃの多層構造とし、ここに、各融点は
１６Ａ＜１６Ｂ＜１６Ｃのように、表面側に比べて内側
の融点を低く、チップから離れる程融点を高くすること
で、ハンダボール１６が均一に融けるようにしたもので
ある。According to the present invention, as shown in FIG. 2, the solder balls 16 formed on the chip have different melting points.
The multilayer structure of A, 16B, and 16C, in which each melting point is 16A <16B <16C, in which the melting point on the inner side is lower than that on the surface side and the melting point is increased as the distance from the chip increases, the solder ball 16 Is designed to melt uniformly.
【０００９】ハンダを多層構造にするには、ハンダ中
に、例えば、シリコン等の含有量の異なるハンダを何種
類か用意し、チップ上のＡl 配線蒸着技術等を用いれば
よい。In order to make the solder into a multi-layered structure, several kinds of solder having different contents of silicon or the like may be prepared in the solder and the Al wiring deposition technique on the chip may be used.
【００１０】このようにして、ハンダボール１６が均一
に融けることにより、配線との接続を良くすることがで
きる。In this way, the solder balls 16 are melted uniformly, so that the connection with the wiring can be improved.
【００１１】[0011]
【実施例】以下図面を参照して本発明の実施例を詳細に
説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【００１２】チップと基板上の配線の接続において、ま
ず、図３のように、パッシベーション膜１０で覆われた
チップ１２上のＡl 電極１４上に低融点のハンダ２２Ａ
を蒸着する。In connecting the chip to the wiring on the substrate, first, as shown in FIG. 3, a solder 22A having a low melting point is formed on the Al electrode 14 on the chip 12 covered with the passivation film 10.
Vapor deposition.
【００１３】次に図４に示すように、ハンダ２２Ａの上
に、今度はハンダ２２Ａより融点の高いハンダ２２Ｂを
蒸着し、融点の異なる層からなるハンダボール１６を形
成する。Next, as shown in FIG. 4, a solder 22B having a melting point higher than that of the solder 22A is vapor-deposited on the solder 22A to form solder balls 16 made of layers having different melting points.
【００１４】これを図５に示すように、基板１８上の配
線２０と位置を合わせ熱処理炉を通すと、内部は熱が伝
わり難いが、内部を低融点のハンダ２２Ａとしているた
め、図５の２２に示すように、低融点のハンダ２２Ａと
外側の高融点のハンダ２２Ｂは同じように均一に融け、
接続を確実にすることができる。When this is aligned with the wiring 20 on the substrate 18 and passed through a heat treatment furnace as shown in FIG. 5, it is difficult for heat to be transferred to the inside, but the inside is made of solder 22A having a low melting point. 22, the low melting point solder 22A and the outer high melting point solder 22B are equally melted,
The connection can be secured.
【００１５】なお一例として、Ｓn −Ｐb 系のハンダ
（固相線温度約１８３℃）とＳn −Ｐb −Ｂi 系のハン
ダ（固相線温度約１３５℃）を用いた場合を考える。As an example, consider the case of using Sn-Pb type solder (solidus temperature about 183 ° C) and Sn-Pb-Bi type solder (solidus temperature about 135 ° C).
【００１６】内側にＳn −Ｐb −Ｂi 系、外側にＳn −
Ｐb 系のハンダを用いてハンダボールを形成し、約１８
０℃程度でチップと基板を加熱圧着すると均一のハンダ
ボールのものより短時間にハンダ全体が融け、接続する
ことができる。Sn-Pb-Bi system on the inside, Sn-Pb on the outside
Form a solder ball using Pb-based solder,
When the chip and the substrate are heated and pressure-bonded at about 0 ° C., the entire solder can be melted and connected in a shorter time than that of a uniform solder ball.
【００１７】[0017]
【発明の効果】以上説明した通り、本発明によれば、ハ
ンダボールが均一に融けるため、配線とチップの接続性
が良くなり、接続不良を防止することができるという効
果を有する。As described above, according to the present invention, since the solder balls are uniformly melted, the connection between the wiring and the chip is improved, and the connection failure can be prevented.
【図１】従来のフリップチップ実装技術を示すための側
面図FIG. 1 is a side view showing a conventional flip chip mounting technique.
【図２】本発明の原理であるハンダ積層を示す側面図FIG. 2 is a side view showing a solder stack which is the principle of the present invention.
【図３】本実施例において、まず低融点ハンダの蒸着を
示す側面図FIG. 3 is a side view showing vapor deposition of low melting point solder in the present embodiment.
【図４】本実施例において、低融点ハンダ上に高融点ハ
ンダの蒸着を示す側面図FIG. 4 is a side view showing vapor deposition of high melting point solder on low melting point solder in the present embodiment.
【図５】本実施例において、多層ハンダが均一に融けた
状態を示す側面図FIG. 5 is a side view showing a state in which the multilayer solder is evenly melted in the present embodiment.
１０…パッシベーション膜 １２…チップ １４…Ａl 電極 １６…ハンダ １６Ａ、１６Ｂ、１６Ｃ、２２Ａ、２２Ｂ…融点の異な
るハンダ １８…基板 ２０…配線 ２２…均一に融けたハンダDESCRIPTION OF SYMBOLS 10 ... Passivation film 12 ... Chip 14 ... Al electrode 16 ... Solder 16A, 16B, 16C, 22A, 22B ... Solders with different melting points 18 ... Substrate 20 ... Wiring 22 ... Solder uniformly melted
Claims (2)
を基板上の配線に接続して作られる半導体装置におい
て、 ＬＳＩチップ上に形成されるハンダボールが、積層され
ていることを特徴とする半導体装置。1. A semiconductor device manufactured by connecting an LSI chip to wiring on a substrate by flip-chip mounting, wherein solder balls formed on the LSI chip are laminated.
を基板上の配線に接続して作られる半導体装置の製造方
法において、 ＬＳＩチップ上に形成されるハンダボールを、該チップ
から離れると、融点が高くなるように多層のハンダで構
成し、 チップと基板を加熱圧着する際に、ハンダボールが均一
に融けるようにした、配線接続工程を含むことを特徴と
する半導体装置の製造方法。2. In a method of manufacturing a semiconductor device, which is manufactured by connecting an LSI chip to wiring on a substrate by flip-chip mounting, the melting point becomes high when a solder ball formed on the LSI chip is separated from the chip. A method of manufacturing a semiconductor device, comprising a wiring connection step, which is configured by multi-layered solder so that the solder balls are uniformly melted when the chip and the substrate are heat-pressed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5147567A JPH07226400A (en) | 1993-06-18 | 1993-06-18 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5147567A JPH07226400A (en) | 1993-06-18 | 1993-06-18 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07226400A true JPH07226400A (en) | 1995-08-22 |
Family
ID=15433276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5147567A Pending JPH07226400A (en) | 1993-06-18 | 1993-06-18 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07226400A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001091176A3 (en) * | 2000-05-23 | 2002-04-18 | Unitive Electronics Inc | Trilayer/bilayer solder bumps and fabrication methods therefor |
| US6607613B2 (en) * | 1998-07-10 | 2003-08-19 | International Business Machines Corporation | Solder ball with chemically and mechanically enhanced surface properties |
| DE19706983B4 (en) * | 1996-02-23 | 2009-06-18 | Denso Corporation, Kariya | Surface mounting unit and transducer assemblies using the surface mounting unit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5232670A (en) * | 1975-09-08 | 1977-03-12 | Mitsubishi Electric Corp | Flip chip solder bump |
| JPS57106057A (en) * | 1980-12-23 | 1982-07-01 | Citizen Watch Co Ltd | Bump structure of ic |
| JPS6049652A (en) * | 1983-08-29 | 1985-03-18 | Seiko Epson Corp | Manufacture of semiconductor element |
-
1993
- 1993-06-18 JP JP5147567A patent/JPH07226400A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5232670A (en) * | 1975-09-08 | 1977-03-12 | Mitsubishi Electric Corp | Flip chip solder bump |
| JPS57106057A (en) * | 1980-12-23 | 1982-07-01 | Citizen Watch Co Ltd | Bump structure of ic |
| JPS6049652A (en) * | 1983-08-29 | 1985-03-18 | Seiko Epson Corp | Manufacture of semiconductor element |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19706983B4 (en) * | 1996-02-23 | 2009-06-18 | Denso Corporation, Kariya | Surface mounting unit and transducer assemblies using the surface mounting unit |
| US6607613B2 (en) * | 1998-07-10 | 2003-08-19 | International Business Machines Corporation | Solder ball with chemically and mechanically enhanced surface properties |
| WO2001091176A3 (en) * | 2000-05-23 | 2002-04-18 | Unitive Electronics Inc | Trilayer/bilayer solder bumps and fabrication methods therefor |
| US6492197B1 (en) | 2000-05-23 | 2002-12-10 | Unitive Electronics Inc. | Trilayer/bilayer solder bumps and fabrication methods therefor |
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