JPH07183375A - Forming method for layer insulating film - Google Patents
Forming method for layer insulating filmInfo
- Publication number
- JPH07183375A JPH07183375A JP32538693A JP32538693A JPH07183375A JP H07183375 A JPH07183375 A JP H07183375A JP 32538693 A JP32538693 A JP 32538693A JP 32538693 A JP32538693 A JP 32538693A JP H07183375 A JPH07183375 A JP H07183375A
- Authority
- JP
- Japan
- Prior art keywords
- film
- sog
- wiring
- wafer
- organic sog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体の製造方法に関
するものであり、特に平坦化された層間絶縁膜の形成方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor, and more particularly to a method for forming a planarized interlayer insulating film.
【０００２】[0002]
【従来の技術】近年、ＬＳＩの高集積化に伴い、微細な
多層配線構造が一般に用いられており、層間絶縁膜の平
坦化にはＳＯＧが用いられている。従来、ＳＯＧによる
平坦化にはシラノール：Si(OH)4 を主成分とする無機Ｓ
ＯＧが通常用いられてきた。しかし、配線構造の微細化
に伴い、より配線間隔が狭くアスペクト比の高い下地に
対する平坦化が要求されるようになり、そのため無機Ｓ
ＯＧと比較して厚膜化が可能な、一般式：Ｒx Si(OH)
4-x （Ｒ：アルキル基）で表される有機シリケート化合
物を主成分とする有機ＳＯＧの使用が一般的となってき
ている。2. Description of the Related Art In recent years, with the high integration of LSI, a fine multilayer wiring structure is generally used, and SOG is used for flattening an interlayer insulating film. Conventionally, for planarization by SOG, inorganic S containing silanol: Si (OH) 4 as a main component
OG has been commonly used. However, with the miniaturization of the wiring structure, it has become necessary to flatten the underlayer having a narrower wiring interval and a higher aspect ratio, and therefore the inorganic S
General formula: R x Si (OH), which enables thicker film than OG
It has become common to use an organic SOG containing an organic silicate compound represented by 4-x (R: alkyl group) as a main component.
【０００３】ところが、ＢＰＳＧ膜等のＢやＰを含有す
るＣＶＤ−SiO2膜上に有機ＳＯＧを塗布すると、使用す
る有機ＳＯＧの濃度、溶媒の種類によってパターンのエ
ッジ部分に塗布むらを生じ平坦性を著しく損なう場合が
ある。この塗布むらは塗布条件によっては約3000Å程度
の段差を局所的に形成することになり、後に平坦化のた
めに行うエッチバック工程でより強調され、上層配線の
信頼性を劣化させる原因となる。そのため有機ＳＯＧを
用いる場合、下層膜の種類および有機ＳＯＧの濃度、溶
媒の種類が限定されるという問題が生じている。However, when an organic SOG is applied onto a CVD-SiO 2 film containing B or P such as a BPSG film, unevenness in application occurs at the edge portion of the pattern depending on the concentration of the organic SOG used and the type of the solvent, resulting in flatness. May be significantly impaired. Depending on the coating conditions, this coating unevenness locally forms a level difference of about 3000 Å, which is more emphasized in the etch-back process performed later for planarization, which causes the reliability of the upper wiring to deteriorate. Therefore, when using the organic SOG, there is a problem that the type of the lower layer film, the concentration of the organic SOG, and the type of the solvent are limited.
【０００４】[0004]
【発明が解決しようとする課題】本発明は、前記問題点
を解決し、Ｂおよび／またはＰを含有するＣＶＤ−SiO2
膜上に塗布むらのない有機ＳＯＧ膜を形成して平坦化す
ることにより、配線の信頼性を向上させることを目的と
する。DISCLOSURE OF THE INVENTION The present invention solves the above-mentioned problems and is a CVD-SiO 2 containing B and / or P.
The purpose is to improve the reliability of wiring by forming an organic SOG film having no coating unevenness on the film and planarizing the film.
【０００５】[0005]
【課題を解決するための手段】本発明は、半導体装置
でＳＯＧによる平坦化工程を有する層間絶縁膜の形成方
法において、Ｂおよび／またはＰを含有するＣＶＤ−Si
O2膜を成膜し、その膜上に無機ＳＯＧを塗布した後、そ
の上に有機ＳＯＧを塗布することを特徴とする層間絶縁
膜の形成方法、半導体でＳＯＧによる平坦化工程を有
する層間絶縁膜の形成方法において、Ｂおよび／または
Ｐを含有するＣＶＤ−SiO2膜を成膜し、その膜表面を洗
浄した後、その上に有機ＳＯＧを塗布することを特徴と
する層間絶縁膜の形成方法、半導体装置でＳＯＧによ
る平坦化工程を有する層間絶縁膜の形成方法において、
Ｂおよび／またはＰを含有するＣＶＤ−SiO2膜を成膜
し、その膜表面をプラズマによる表面処理を行った後、
その上に有機ＳＯＧを塗布することを特徴とする層間絶
縁膜の形成方法である。The present invention provides a method of forming an interlayer insulating film in a semiconductor device, which comprises a planarization step by SOG, in which CVD-Si containing B and / or P is used.
O 2 film is formed, inorganic SOG is applied on the O 2 film, and then organic SOG is applied on the O 2 film, forming method of interlayer insulating film, interlayer insulation having planarization step by SOG in semiconductor In the method of forming a film, a CVD-SiO 2 film containing B and / or P is formed, the surface of the film is cleaned, and then organic SOG is applied thereon, forming an interlayer insulating film. A method and a method for forming an interlayer insulating film having a planarization step by SOG in a semiconductor device,
After forming a CVD-SiO 2 film containing B and / or P and subjecting the surface of the film to plasma surface treatment,
It is a method of forming an interlayer insulating film, which is characterized in that an organic SOG is applied thereon.
【０００６】[0006]
【作用】本発明によれば、Ｂおよび／またはＰを含有
するＣＶＤ−SiO2膜上に無機ＳＯＧを塗布した後に有機
ＳＯＧを塗布すること、または、Ｂおよび／またはＰ
を含有するＣＶＤ−SiO2膜を成膜し洗浄した後、有機Ｓ
ＯＧを塗布すること、または、Ｂおよび／またはＰを
含有するＣＶＤ−SiO2膜を成膜しプラズマによる表面処
理を行った後、有機ＳＯＧを塗布することにより、下層
膜の膜質、表面状態および有機ＳＯＧの濃度、溶媒種に
拘らず塗布むらのない有機ＳＯＧ膜を形成できるように
なる。また、塗布むらを生じないので、後の平坦化工程
であるエッチバックによって、よりいっそう平坦化され
良好な形状が得られる。According to the present invention, the organic SOG is applied after the inorganic SOG is applied on the CVD-SiO 2 film containing B and / or P, or B and / or P is applied.
After forming and cleaning a CVD-SiO 2 film containing
By applying OG, or by forming a CVD-SiO 2 film containing B and / or P and performing surface treatment by plasma, applying organic SOG, the film quality, surface state and It becomes possible to form an organic SOG film having no coating unevenness regardless of the organic SOG concentration and solvent type. In addition, since coating unevenness does not occur, further flattening and a good shape can be obtained by etching back which is a flattening step later.
【０００７】良好に平坦化された表面上に形成される配
線は断線せず、配線層の信頼性を損なうという問題は発
生しない。The wiring formed on the well-planarized surface does not break, and the problem of impairing the reliability of the wiring layer does not occur.
【０００８】[0008]
【実施例】ｎ型半導体Siウエハ１表面にLOCOS ２を形成
した後、ゲート電極ポリーシリコン４を形成し、第一層
間膜としてＢおよび／またはＰを含有するＣＶＤ− SiO
x膜３（ＢＰＳＧ膜）を10000 Å成膜、900 ℃でアニー
ルした状態を図１（ａ）に示した。これを、以下の実施
例、比較例の原試料として用いる。EXAMPLE A LOCOS 2 is formed on the surface of an n-type semiconductor Si wafer 1, a gate electrode polysilicon 4 is formed, and a CVD-SiO containing B and / or P as a first interlayer film.
An x film 3 (BPSG film) having a film thickness of 10000 Å and annealed at 900 ° C. is shown in FIG. This is used as an original sample in the following examples and comparative examples.
【０００９】（実施例１）ＢＰＳＧ膜３表面の段差部を
埋め込むため、市販の無機ＳＯＧ５（例えば東京応化工
業（株）製 OCD−Type2 ）塗布液をウエハ中央部に滴下
しウエハ１を所定の回転数で回転してスピンコートしプ
リベークした後、市販の有機ＳＯＧ（例えば東京応化工
業（株）製 OCD−Type7 ）塗布液を同様にスピンコート
する｛図１（ｂ’）参照｝。プリベーク後、窒素雰囲気
中で 400℃、30分ポストベークし、ＳＯＧ膜５および６
を形成する｛図１（ｂ’）参照｝。次にエッチバックを
行いＳＯＧ膜の表面を平坦化し｛図１（ｄ）参照｝、そ
の上に所定パターンのAl配線７を形成し｛図１（ｅ）参
照｝、最後にこのAl配線上に配線保護のためのパッシベ
ーション膜８を形成し、実施例１の半導体装置を製造す
る｛図１（ｆ）参照｝。(Example 1) In order to fill the stepped portion on the surface of the BPSG film 3, a commercially available inorganic SOG5 (for example, OCD-Type2 manufactured by Tokyo Ohka Kogyo Co., Ltd.) coating solution is dripped on the central portion of the wafer to make the wafer 1 predetermined. After spin-coating by rotating at a rotation speed and pre-baking, a commercially available organic SOG (for example, OCD-Type7 manufactured by Tokyo Ohka Kogyo Co., Ltd.) coating solution is similarly spin-coated {see FIG. 1 (b ')}. After pre-baking, post-baking is performed in a nitrogen atmosphere at 400 ° C for 30 minutes to form SOG films 5 and 6
Are formed {see FIG. 1 (b ')}. Next, etch back is performed to flatten the surface of the SOG film {see FIG. 1 (d)}, and an Al wiring 7 having a predetermined pattern is formed thereon {see FIG. 1 (e)}. Finally, on this Al wiring. The passivation film 8 for wiring protection is formed, and the semiconductor device of Example 1 is manufactured {see FIG. 1 (f)}.
【００１０】（実施例２）前述の半導体Siウエハ１をア
ップフロー状態で５分間以上水洗した後｛図１（ｂ”）
参照｝、ＢＰＳＧ膜３表面の段差部を埋め込むため、有
機ＳＯＧ（例えば東京応化工業（株）製 OCD−Type7 ）
塗布液をスピンコートする。プリベーク後、窒素雰囲気
中で 400℃、30分ポストべークし、有機ＳＯＧ膜６を形
成する｛図１（ｃ）参照｝。その後（実施例１）と同様
にエッチバックし、その上にAl配線７を形成しパッシベ
ーション膜を形成し半導体装置を製造する。(Embodiment 2) The above-mentioned semiconductor Si wafer 1 was washed with water for 5 minutes or more in an upflow state {FIG.
Refer to}, since the stepped portion on the surface of the BPSG film 3 is embedded, organic SOG (for example, OCD-Type7 manufactured by Tokyo Ohka Kogyo Co., Ltd.)
Spin-coat the coating solution. After prebaking, post baking is performed at 400 ° C. for 30 minutes in a nitrogen atmosphere to form the organic SOG film 6 (see FIG. 1C). After that, etching back is performed in the same manner as in (Example 1), an Al wiring 7 is formed thereon, and a passivation film is formed to manufacture a semiconductor device.
【００１１】（実施例３）前述の半導体Siウエハ１表面
を各種ガスを用いてプラズマ処理（処理条件：表１参
照）した後｛図１（ｂ”）参照｝、段差部を埋め込むた
め、市販の有機ＳＯＧ（例えば東京応化工業（株）製 O
CD−Type7 ）塗布液をスピンコートする。プリベーク
後、窒素雰囲気中で 400℃、30分ポストベークし、有機
ＳＯＧ膜６を形成する｛図１（ｃ）参照｝。その後（実
施例１）と同様にエッチバックし、その上にAl配線７を
形成し半導体装置を製造する。(Embodiment 3) The surface of the above-mentioned semiconductor Si wafer 1 is subjected to plasma treatment using various gases (treatment condition: see Table 1) {see FIG. 1 (b ")}, and the step portion is buried, so that it is commercially available. Organic SOG (for example, O manufactured by Tokyo Ohka Kogyo Co., Ltd.)
CD-Type7) Spin coat the coating solution. After pre-baking, post-baking is performed in a nitrogen atmosphere at 400 ° C. for 30 minutes to form the organic SOG film 6 (see FIG. 1C). After that, etching back is performed in the same manner as in (Example 1), and an Al wiring 7 is formed thereon to manufacture a semiconductor device.
【００１２】[0012]
【表１】 [Table 1]
【００１３】（比較例）実施例１、２、３と同様にｎ型
半導体Siウエハ表面に図１（ａ）のようにＢＰＳＧ膜３
を形成した後、直ちに市販の有機ＳＯＧ（例えば東京応
化工業（株）製OCD −Type7 ）塗布液をスピンコートす
る。プリベーク後、窒素雰囲気中で 400℃、30分ポスト
ベークし、有機ＳＯＧ膜６を形成する｛図１（ｃ）参
照｝。その後（実施例１）と同様にエッチバックし、そ
の上にAl配線７を形成し半導体装置を製造する。(Comparative Example) Similar to Examples 1, 2 and 3, a BPSG film 3 was formed on the surface of an n-type semiconductor Si wafer as shown in FIG.
Immediately after forming the film, a commercially available organic SOG (for example, OCD-Type7 manufactured by Tokyo Ohka Kogyo Co., Ltd.) coating solution is spin-coated. After pre-baking, post-baking is performed in a nitrogen atmosphere at 400 ° C. for 30 minutes to form the organic SOG film 6 (see FIG. 1C). After that, etching back is performed in the same manner as in (Example 1), and an Al wiring 7 is formed thereon to manufacture a semiconductor device.
【００１４】実施例１〜３、および比較例の方法で形成
した半導体装置をパッケージし、配線の信頼性試験とし
て行った累積故障率の測定結果を図２〜４に示す。図２
は、実施例１と比較例、図３は水洗時間10分のときの実
施例２と比較例、図４は、ガス種が酸素、プラズマ処理
時間15sec の実施例３と比較例をそれぞれ示している。2 to 4 show the results of measurement of the cumulative failure rate, which was performed as a wiring reliability test by packaging the semiconductor devices formed by the methods of Examples 1 to 3 and the comparative example. Figure 2
Shows Example 1 and a comparative example, FIG. 3 shows Example 2 and a comparative example when the washing time is 10 minutes, and FIG. 4 shows Example 3 and a comparative example in which the gas species is oxygen and the plasma treatment time is 15 sec. There is.
【００１５】図２〜４から配線下の層間膜が良好に平坦
化された結果、本発明による半導体装置の配線寿命が従
来方法による半導体装置の約５倍に伸びていることが明
らかである。本実施例では、配線下の第一層間膜として
ＢＰＳＧ膜を採用したが、本発明は第一層間膜がＢＳＧ
膜、ＰＳＧ膜の場合にも同様に効果がある。また第一層
間膜中の不純物濃度、およびアニール条件の相違により
表面状態が変化しても本発明の効果は変わらない。さら
に本発明では、この第一層間膜の形成方法としては常圧
ＣＶＤ、減圧ＣＶＤ、ＰＥ−ＣＶＤのいずれの方法でも
適用でき、原料としてはSiH4系、Si(OC2H5)4（略称TEO
S）系のいずれを用いてもよい。It is apparent from FIGS. 2 to 4 that as a result of the good planarization of the interlayer film under the wiring, the wiring life of the semiconductor device according to the present invention is extended to about 5 times that of the semiconductor device according to the conventional method. In this embodiment, the BPSG film is used as the first interlayer film under the wiring, but in the present invention, the first interlayer film is BSG.
The same effect is obtained in the case of a film or PSG film. Further, the effect of the present invention does not change even if the surface state changes due to the difference in the impurity concentration in the first interlayer film and the annealing condition. Further, in the present invention, any method of atmospheric pressure CVD, low pressure CVD, PE-CVD can be applied as the method for forming the first interlayer film, and SiH 4 system, Si (OC 2 H 5 ) 4 ( Abbreviation TEO
Any of S) system may be used.
【００１６】また、実施例１で使用する無機および有機
ＳＯＧ塗布液の濃度、溶媒種は本発明の効果に影響しな
いことを確認した。図３には、実施例２の水洗時間10分
間の例を示したが、本発明では水洗時間は５分間以上で
あれば同様の効果が得られる。図４には実施例３のガス
種が酸素、処理時間15sec のプラズマ処理の例を示した
が、表１に示したその他の窒素、アンモニアなどのガス
種およびこれらの混合ガスによるプラズマ処理によって
も同様の効果が得られる。さらにプラズマ処理に加え
て、アルゴン又はヘリウムによるスパッタエッチングを
第１層間膜表面に行っても同様の効果が得られる。It was also confirmed that the concentrations of the inorganic and organic SOG coating liquids and solvent species used in Example 1 did not affect the effects of the present invention. FIG. 3 shows an example of the water washing time of 10 minutes in Example 2, but in the present invention, the same effect can be obtained if the water washing time is 5 minutes or more. FIG. 4 shows an example of the plasma treatment in which the gas species of Example 3 is oxygen and the treatment time is 15 seconds. However, it is also possible to perform the plasma treatment with other gas species such as nitrogen and ammonia shown in Table 1 and a mixed gas thereof. The same effect can be obtained. Further, in addition to the plasma treatment, the same effect can be obtained by performing sputter etching with argon or helium on the surface of the first interlayer film.
【００１７】これらの表面処理を行ったＢＰＳＧ膜をＸ
ＰＳ分析した結果、膜表面にＰ−OHおよびＢ−OH結合の
存在が認められた。このことから、本発明の方法により
ＢＰＳＧ膜表面にＰ−OH及びＢ−OH結合を形成すること
によって、有機ＳＯＧ塗布液の濡れ性を改善することが
でき、良好な平坦性を得ることができるようになったも
のと考えられる。The BPSG film subjected to these surface treatments is treated with X
As a result of PS analysis, the presence of P-OH and B-OH bonds was recognized on the film surface. From this, by forming P-OH and B-OH bonds on the surface of the BPSG film by the method of the present invention, the wettability of the organic SOG coating liquid can be improved and good flatness can be obtained. It is thought that it has become like this.
【００１８】[0018]
【発明の効果】本発明では、Ｂおよび／またはＰを含有
するＣＶＤ− SiOx 膜上への無機ＳＯＧ塗布、または膜
の洗浄、またはプラズマ表面処理の後に、有機ＳＯＧを
塗布することにより、下層膜の膜質、表面状態および有
機ＳＯＧの濃度、溶媒種に拘らず塗布むらのない有機Ｓ
ＯＧ膜を形成できる。また、塗布むらを生じないので、
後の平坦化工程であるエッチバックによって、より一層
平坦化された良好な形状が得られる。したがって、本発
明の方法によれば、上層配線層の信頼性を損なうという
問題は発生しない。INDUSTRIAL APPLICABILITY According to the present invention, an inorganic SOG coating on a CVD-SiO x film containing B and / or P, or cleaning of the film, or plasma surface treatment, followed by coating with an organic SOG to form a lower layer Organic S that has no coating unevenness regardless of the film quality, surface condition, organic SOG concentration, and solvent species
An OG film can be formed. In addition, since uneven coating does not occur,
Etching back, which is a flattening step later, makes it possible to obtain a better flattened shape. Therefore, according to the method of the present invention, the problem of impairing the reliability of the upper wiring layer does not occur.
【図１】本発明法の工程を表す半導体装置の断面図であ
る。(a) はウエハ表面にＢＰＳＧ膜を成膜した断面図。
(b')は図１(a) のウエハに無機ＳＯＧ、有機ＳＯＧを塗
布したウエハ断面図、(b")は、図１(a) のウエハに水
洗、プラズマ処理したウエハ断面図。(c) はウエハに有
機ＳＯＧ膜を形成したウエハ断面図。(d) はウエハをエ
ッチバックしたウエハ断面図。(e) はウエハにAl配線を
形成したウエハ断面図。(f) はウエハにパッシベーショ
ン膜を形成したウエハ断面図。FIG. 1 is a cross-sectional view of a semiconductor device showing steps of the method of the present invention. (a) is a cross-sectional view of a BPSG film formed on the wafer surface.
1B 'is a sectional view of the wafer of FIG. 1A coated with inorganic SOG or organic SOG, and FIG. 1B' is a sectional view of the wafer of FIG. 1A washed with water and plasma-treated. ) Is a cross-sectional view of a wafer in which an organic SOG film is formed, (d) is a cross-sectional view of the wafer in which the wafer is etched back, (e) is a cross-sectional view of the wafer in which Al wiring is formed, and (f) is a passivation film on the wafer. FIG.
【図２】実施例１と比較例の半導体装置での断線時間と
累積故障率との関係を示した図。FIG. 2 is a diagram showing a relationship between a disconnection time and a cumulative failure rate in the semiconductor devices of Example 1 and Comparative Example.
【図３】実施例２と比較例の半導体装置での断線時間と
累積故障率との関係を示した図。FIG. 3 is a diagram showing a relationship between a wire breakage time and a cumulative failure rate in semiconductor devices of Example 2 and a comparative example.
【図４】実施例３と比較例の半導体装置での断線時間と
累積故障率との関係を示した図。FIG. 4 is a diagram showing a relationship between a disconnection time and a cumulative failure rate in semiconductor devices of Example 3 and a comparative example.
１ Siウエハ ２ LOCOS ３ ＢＰＳＧ膜 ４ ゲート電極ポリシリコン ５ 無機ＳＯＧ膜 ６ 有機ＳＯＧ膜 ７ Al配線 ８ パッシベーション膜 1 Si Wafer 2 LOCOS 3 BPSG Film 4 Gate Electrode Polysilicon 5 Inorganic SOG Film 6 Organic SOG Film 7 Al Wiring 8 Passivation Film
【手続補正書】[Procedure amendment]
【提出日】平成６年６月７日[Submission date] June 7, 1994
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００９[Correction target item name] 0009
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００９】（実施例１）ＢＰＳＧ膜３表面の段差部を
埋め込むため、市販の無機ＳＯＧ５（例えば東京応化工
業（株）製 OCD−Type2 ）塗布液をウエハ中央部に滴下
しウエハ１を所定の回転数で回転してスピンコートしプ
リベークした後、市販の有機ＳＯＧ（例えば東京応化工
業（株）製 OCD−Type7 ）塗布液を同様にスピンコート
する｛図１（ｂ1 ）参照｝。プリベーク後、窒素雰囲気
中で 400℃、30分ポストベークし、ＳＯＧ膜５および６
を形成する｛図１（ｂ1 ）参照｝。次にエッチバックを
行いＳＯＧ膜の表面を平坦化し｛図１（ｄ）参照｝、そ
の上に所定パターンのAl配線７を形成し｛図１（ｅ）参
照｝、最後にこのAl配線上に配線保護のためのパッシベ
ーション膜８を形成し、実施例１の半導体装置を製造す
る｛図１（ｆ）参照｝。(Example 1) In order to fill the stepped portion on the surface of the BPSG film 3, a commercially available inorganic SOG5 (for example, OCD-Type2 manufactured by Tokyo Ohka Kogyo Co., Ltd.) coating solution is dripped on the central portion of the wafer to make the wafer 1 predetermined. After spin coating at a rotation speed and pre-baking, a commercially available organic SOG (for example, OCD-Type7 manufactured by Tokyo Ohka Kogyo Co., Ltd.) coating solution is similarly spin coated {see FIG. 1 (b 1 )}. After pre-baking, post-baking is performed in a nitrogen atmosphere at 400 ° C for 30 minutes to form SOG films 5 and 6
Are formed {see FIG. 1 (b 1 )}. Next, etch back is performed to flatten the surface of the SOG film {see FIG. 1 (d)}, and an Al wiring 7 having a predetermined pattern is formed thereon {see FIG. 1 (e)}. Finally, on this Al wiring. The passivation film 8 for wiring protection is formed, and the semiconductor device of Example 1 is manufactured {see FIG. 1 (f)}.
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１０[Correction target item name] 0010
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１０】（実施例２）前述の半導体Siウエハ１をア
ップフロー状態で５分間以上水洗した後｛図１（ｂ2 ）
参照｝、ＢＰＳＧ膜３表面の段差部を埋め込むため、有
機ＳＯＧ（例えば東京応化工業（株）製 OCD−Type7 ）
塗布液をスピンコートする。プリベーク後、窒素雰囲気
中で 400℃、30分ポストべークし、有機ＳＯＧ膜６を形
成する｛図１（ｃ）参照｝。その後（実施例１）と同様
にエッチバックし、その上にAl配線７を形成しパッシベ
ーション膜を形成し半導体装置を製造する。[0010] After washing with water (Example 2) or 5 minutes in the semiconductor Si up flow state wafer 1 described above {FIG 1 (b 2)
Refer to}, since the stepped portion on the surface of the BPSG film 3 is embedded, organic SOG (for example, OCD-Type7 manufactured by Tokyo Ohka Kogyo Co., Ltd.)
Spin-coat the coating solution. After prebaking, post baking is performed at 400 ° C. for 30 minutes in a nitrogen atmosphere to form the organic SOG film 6 (see FIG. 1C). After that, etching back is performed in the same manner as in (Example 1), an Al wiring 7 is formed thereon, and a passivation film is formed to manufacture a semiconductor device.
【手続補正３】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１１[Correction target item name] 0011
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１１】（実施例３）前述の半導体Siウエハ１表面
を各種ガスを用いてプラズマ処理（処理条件：表１参
照）した後｛図１（ｂ2 ）参照｝、段差部を埋め込むた
め、市販の有機ＳＯＧ（例えば東京応化工業（株）製 O
CD−Type7 ）塗布液をスピンコートする。プリベーク
後、窒素雰囲気中で 400℃、30分ポストベークし、有機
ＳＯＧ膜６を形成する｛図１（ｃ）参照｝。その後（実
施例１）と同様にエッチバックし、その上にAl配線７を
形成し半導体装置を製造する。(Embodiment 3) After the surface of the above-mentioned semiconductor Si wafer 1 was subjected to plasma treatment using various gases (treatment condition: see Table 1) {see FIG. 1 (b 2 )}, a step portion was buried, so that it was commercially available. Organic SOG (for example, O manufactured by Tokyo Ohka Kogyo Co., Ltd.)
CD-Type7) Spin coat the coating solution. After pre-baking, post-baking is performed in a nitrogen atmosphere at 400 ° C. for 30 minutes to form the organic SOG film 6 (see FIG. 1C). After that, etching back is performed in the same manner as in (Example 1), and an Al wiring 7 is formed thereon to manufacture a semiconductor device.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図面の簡単な説明[Name of item to be corrected] Brief description of the drawing
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明法の工程を表す半導体装置の断面図であ
る。(a) はウエハ表面にＢＰＳＧ膜を成膜した断面図。
(b1)は図１(a) のウエハに無機ＳＯＧ、有機ＳＯＧを塗
布したウエハ断面図、(b 2)は、図１(a) のウエハに水
洗、プラズマ処理したウエハ断面図。(c) はウエハに有
機ＳＯＧ膜を形成したウエハ断面図。(d) はウエハをエ
ッチバックしたウエハ断面図。(e) はウエハにAl配線を
形成したウエハ断面図。(f) はウエハにパッシベーショ
ン膜を形成したウエハ断面図。FIG. 1 is a cross-sectional view of a semiconductor device showing the steps of the method of the present invention.
It (a) is a cross-sectional view of a BPSG film formed on the wafer surface.
(b1) Shows the wafer of Fig. 1 (a) coated with inorganic SOG or organic SOG.
Cross-sectional view of woven wafer, (b 2) Is water on the wafer in FIG.
A cross-sectional view of a wafer that has been washed and plasma processed. (c) is on the wafer
Sectional view of a wafer on which a machine SOG film is formed. (d) is the wafer
FIG. 3 is a sectional view of a wafer that is backed up. (e) shows Al wiring on the wafer
Sectional view of the formed wafer. (f) is the passivation of the wafer
FIG. 3 is a cross-sectional view of a wafer on which a spin film is formed.
【図２】実施例１と比較例の半導体装置での断線時間と
累積故障率との関係を示した図。FIG. 2 is a diagram showing a relationship between a disconnection time and a cumulative failure rate in the semiconductor devices of Example 1 and Comparative Example.
【図３】実施例２と比較例の半導体装置での断線時間と
累積故障率との関係を示した図。FIG. 3 is a diagram showing a relationship between a wire breakage time and a cumulative failure rate in semiconductor devices of Example 2 and a comparative example.
【図４】実施例３と比較例の半導体装置での断線時間と
累積故障率との関係を示した図。FIG. 4 is a diagram showing a relationship between a disconnection time and a cumulative failure rate in semiconductor devices of Example 3 and a comparative example.
【符号の説明】 １ Siウエハ ２ LOCOS ３ ＢＰＳＧ膜 ４ ゲート電極ポリシリコン ５ 無機ＳＯＧ膜 ６ 有機ＳＯＧ膜 ７ Al配線 ８ パッシベーション膜[Explanation of reference numerals] 1 Si wafer 2 LOCOS 3 BPSG film 4 Gate electrode polysilicon 5 Inorganic SOG film 6 Organic SOG film 7 Al wiring 8 Passivation film
【手続補正５】[Procedure Amendment 5]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図１[Name of item to be corrected] Figure 1
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図１】 [Figure 1]
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/316 7352−4Ｍ Ｈ０１Ｌ 21/30 ５７１ 9274−4Ｍ 21/94 Ａ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 21/316 7352-4M H01L 21/30 571 9274-4M 21/94 A
Claims (3)
下ＳＯＧと記載する）による平坦化工程を有する層間絶
縁膜の形成方法において、 Ｂおよび／またはＰを含有するＣＶＤ−SiO2膜を成膜
し、その膜上に無機ＳＯＧを塗布した後、その上に有機
ＳＯＧを塗布することを特徴とする層間絶縁膜の形成方
法。1. A CVD-SiO 2 film containing B and / or P is formed in a method for forming an interlayer insulating film, which comprises a planarization step by SOG (Spin on Glass, hereinafter referred to as SOG) in a semiconductor device. Then, an inorganic SOG is applied on the film, and then an organic SOG is applied on the film, to form an interlayer insulating film.
る層間絶縁膜の形成方法において、 Ｂおよび／またはＰを含有するＣＶＤ−SiO2膜を成膜
し、その膜表面を洗浄した後、その上に有機ＳＯＧを塗
布することを特徴とする層間絶縁膜の形成方法。2. A method for forming an interlayer insulating film which is a semiconductor and has a planarization step by SOG, wherein a CVD-SiO 2 film containing B and / or P is formed, the surface of the film is washed, and then the film is formed thereon. A method for forming an interlayer insulating film, which comprises applying an organic SOG to the substrate.
有する層間絶縁膜の形成方法において、 Ｂおよび／またはＰを含有するＣＶＤ−SiO2膜を成膜
し、その膜表面をプラズマによる表面処理を行った後、
その上に有機ＳＯＧを塗布することを特徴とする層間絶
縁膜の形成方法。3. A method of forming an interlayer insulating film in a semiconductor device, comprising a planarization step by SOG, wherein a CVD-SiO 2 film containing B and / or P is formed, and the surface of the film is subjected to surface treatment by plasma. After going
A method for forming an interlayer insulating film, which comprises applying organic SOG thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32538693A JPH07183375A (en) | 1993-12-22 | 1993-12-22 | Forming method for layer insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32538693A JPH07183375A (en) | 1993-12-22 | 1993-12-22 | Forming method for layer insulating film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07183375A true JPH07183375A (en) | 1995-07-21 |
Family
ID=18176257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32538693A Pending JPH07183375A (en) | 1993-12-22 | 1993-12-22 | Forming method for layer insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07183375A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1174269A (en) * | 1997-08-27 | 1999-03-16 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| CN1122301C (en) * | 1997-03-31 | 2003-09-24 | 日本电气株式会社 | Method for manufacturing semiconductor device using planarization technique |
-
1993
- 1993-12-22 JP JP32538693A patent/JPH07183375A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1122301C (en) * | 1997-03-31 | 2003-09-24 | 日本电气株式会社 | Method for manufacturing semiconductor device using planarization technique |
| JPH1174269A (en) * | 1997-08-27 | 1999-03-16 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
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