JPH071773B2 - Connection structure of electronic parts - Google Patents
Connection structure of electronic partsInfo
- Publication number
- JPH071773B2 JPH071773B2 JP62004802A JP480287A JPH071773B2 JP H071773 B2 JPH071773 B2 JP H071773B2 JP 62004802 A JP62004802 A JP 62004802A JP 480287 A JP480287 A JP 480287A JP H071773 B2 JPH071773 B2 JP H071773B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- connection
- wiring board
- connection structure
- horizontal direction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はLSIチップ等の電子部品を基板に電気接続する
接続構造に関する。The present invention relates to a connection structure for electrically connecting an electronic component such as an LSI chip to a substrate.
多数の接続点を有するLSIチップ等の電子部品（以下、
チップと称す）を配線基板に直接はんだ接続する方法と
してフリップチップボンディングがある。しかし、配線
基板としてセラミックやガラスエポキシ系などの材料を
用いる場合、チップと基板材料の膨張係数が異なるた
め、温度変化による熱歪がはんだ結合部に作用し、結合
破壊寿命を低下させるという問題があった。Electronic components such as LSI chips with many connection points (hereinafter,
There is flip-chip bonding as a method for directly solder-connecting (called a chip) to a wiring board. However, when a material such as ceramic or glass epoxy is used for the wiring board, there is a problem that thermal strain due to temperature change acts on the solder joints and the bond breakdown life is shortened because the expansion coefficient of the chip and the board material is different. there were.
この問題に対し、特開昭61-110441「マイクロエレクト
ロニック素子を電気的に接続するための変形可能のマル
チ結合の製法」において、水平方向の熱歪を吸収する構
造についての報告がある。第４図は上記報告による従来
構造の概念図であるが高さが最小横方向寸法の数倍であ
る板ばね100が２本のピン100a,100bに結合され、各ピン
100a,100bはチップ２及び配線基板３に接続されてい
る。板ばね100がチップ２と配線基板３の水平熱歪を吸
収し、はんだ４のせん断応力を軽減するよう作用し、結
合破壊寿命を伸す働きをする。To solve this problem, there is a report on a structure that absorbs thermal strain in the horizontal direction in Japanese Patent Laid-Open No. 61-110441 "Manufacturing method of deformable multi-coupling for electrically connecting microelectronic elements". FIG. 4 is a conceptual diagram of the conventional structure reported above, but a leaf spring 100 having a height several times as large as the minimum lateral dimension is connected to two pins 100a and 100b.
100a and 100b are connected to the chip 2 and the wiring board 3. The leaf spring 100 absorbs horizontal thermal strain of the chip 2 and the wiring board 3, acts to reduce the shear stress of the solder 4, and extends the bond breaking life.
ところで、上記した従来構造はチップ２の背面（上面）
に熱接続される冷却体の圧力に耐えるために垂直方向に
対して十分な剛性が確保され、垂直方向に変位しない構
造が取られている。このため、チップ２の冷却手段に対
して次のような課題が存在していた。By the way, the conventional structure described above has a back surface (upper surface) of the chip 2.
Sufficient rigidity is secured in the vertical direction in order to withstand the pressure of the cooling body that is thermally connected to, and a structure that does not displace in the vertical direction is adopted. Therefore, the following problems exist for the cooling means of the chip 2.
なお、第４図における５はチップ電極、６は配線基板電
極である。In FIG. 4, 5 is a chip electrode and 6 is a wiring board electrode.
たとえば第５図に示すように、複数個のチップ２を同一
配線基板３に接続する場合、配線基板３の反りやチップ
２の接続高さバラツキにより、それぞれのチップ２の背
面が同一平面にならない。ところが、上記した従来の接
続構造では、チップ２が垂直方向に変位できないため、
各チップ２の背面に習うよう冷却体7aを独立に熱接続す
る必要があった。第５図はベローズ7bを用いて冷却体7a
をチップ２に独立圧着させた概念図であるが、このよう
な接続構造を取る以上、それぞれのチップ２に対し独立
に冷却体7aの位置調整あるいは圧着圧力調整手段が不可
欠であり、冷却構造を相当複雑なものとしていた。For example, as shown in FIG. 5, when a plurality of chips 2 are connected to the same wiring board 3, the back surfaces of the respective chips 2 are not on the same plane due to the warp of the wiring board 3 and the variation in the connection height of the chips 2. . However, in the above-mentioned conventional connection structure, since the chip 2 cannot be displaced in the vertical direction,
It was necessary to independently heat-connect the cooling body 7a so that the back surface of each chip 2 could be learned. FIG. 5 shows a cooling body 7a using a bellows 7b.
Is a conceptual diagram in which the chips 2 are independently pressure-bonded, but as long as such a connection structure is adopted, it is indispensable to independently adjust the position of the cooling body 7a or the pressure-bonding pressure adjustment means for each chip 2, and It was quite complicated.
本発明の目的は上記課題を解決するため、チップ２と配
線基板３の熱歪吸収機能を低下させることなく、垂直方
向にもある限界内で自由に変位可能なチップの電気的接
続構造を提供するにある。In order to solve the above problems, an object of the present invention is to provide a chip electrical connection structure which can be freely displaced within a certain limit in the vertical direction without deteriorating the thermal strain absorbing function of the chip 2 and the wiring board 3. There is.
なお、第５図における７は冷却体本体、８はチップ２と
冷却体7aの熱接続部、10はチップ２と配線基板３との電
気接続部である。In FIG. 5, 7 is a cooling body, 8 is a thermal connection between the chip 2 and the cooling body 7a, and 10 is an electrical connection between the chip 2 and the wiring board 3.
上記目的は、従来接続構造で用いた板ばねの代りに、そ
の縦横比を逆にした接続高さ方向及び水平方向に可撓性
を有するらせん形平面リードを用いることにより、達成
される。The above object is achieved by using a spiral flat lead having flexibility in the connection height direction and the horizontal direction, the aspect ratio of which is reversed, instead of the leaf spring used in the conventional connection structure.
すなわち、高さが最小横方向寸法以下である接続高さ方
向及び水平方向に可撓性を有するらせん形平面リードを
チップ接続構造に採用することで、電気的接続を保持し
ながらある限界内でチップを独立に上方へ移動させるこ
とができる。このため、チップは冷却体に独立に熱接続
が可能となり、冷却系の構造を極端に簡素化できる。That is, by adopting a spiral-shaped planar lead having a flexibility in the connection height direction and the horizontal direction, the height of which is equal to or smaller than the minimum lateral dimension, to the chip connection structure, within a certain limit while maintaining the electrical connection. The chips can be moved upwards independently. Therefore, the chip can be independently thermally connected to the cooling body, and the structure of the cooling system can be extremely simplified.
以下、本発明の実施例を第１図、第２図及び第３図によ
り説明する。An embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 3.
第１図（ａ）は本発明に係る接続高さ方向及び水平方向
に可撓性を有するらせん形平面リードの見取図、（ｂ）
はその平面図、（ｃ）は接続状態を示す正面図（接続高
さ方向及び水平方向に可撓性を有するらせん形平面リー
ド部分は断面図）、第２図は本発明によるチップと配線
基板との接続状態及び冷却系との位置関係図であり、冷
却体に対し熱接続前のチップを（ａ）、熱接続後のチッ
プを（ｂ）、その拡大図を（ｃ）に示した。第３図は本
発明に係るらせん形可撓性平面リードの他の実施例を示
す正面配列図である。第１図及び第２図において、１は
らせん形可撓性平面リード、1a,1bはらせん形可撓性平
面リードの対チップ及び対配線基板端子、２はチップ、
３は配線基板、４ははんだ、５はチップ電極、６は配線
基板電極、７は冷却体本体、８は熱接続部、10は電気接
続部である。FIG. 1 (a) is a schematic view of a spiral planar lead having flexibility in a connection height direction and a horizontal direction according to the present invention, (b).
Is a plan view thereof, (c) is a front view showing a connection state (a cross sectional view of a spiral planar lead portion having flexibility in a connection height direction and a horizontal direction), and FIG. 2 is a chip and a wiring board according to the present invention. FIG. 3 is a diagram showing a connection state with a cooling system and a positional relationship with a cooling system. A chip before heat connection to a cooling body is shown in (a), a chip after heat connection is shown in (b), and an enlarged view thereof is shown in (c). FIG. 3 is a front array view showing another embodiment of the spiral flexible flat lead according to the present invention. In FIGS. 1 and 2, 1 is a spiral flexible flat lead, 1a and 1b are pairs of spiral flexible flat leads for a chip and a pair of wiring board terminals, 2 is a chip,
3 is a wiring board, 4 is solder, 5 is a chip electrode, 6 is a wiring board electrode, 7 is a cooling body, 8 is a thermal connection portion, and 10 is an electrical connection portion.
本発明による一実施例として銅または銅合金による接続
高さ方向及び水平方向に可撓性を有するらせん形平面リ
ード１を第１図に示す。第１図（ａ）はその見取図で、
平面図（ｂ）に示すごとくらせんの中心及び終端がそれ
ぞれ対チップ端子1aと対配線基板端子1bになっている。
第１図（ｃ）に示すように、対チップ端子1aははんだ４
によりチップ電極５に接続され、対配線基板端子1bは溶
接または一体化加工により配線基板電極６に接続されて
いる。As an embodiment of the present invention, FIG. 1 shows a spiral planar lead 1 made of copper or a copper alloy and having flexibility in the connection height direction and the horizontal direction. Figure 1 (a) is a sketch of it.
As shown in the plan view (b), the center and the terminal of the screw are the chip terminal 1a and the wiring board terminal 1b, respectively.
As shown in FIG. 1 (c), the opposite terminal 1a is solder 4
Is connected to the chip electrode 5, and the pair of wiring board terminals 1b is connected to the wiring board electrode 6 by welding or integral processing.
チップの電気的接続構造を上記した構成にすることによ
り、電気的接続を保持しながらある限界内でチップを独
立に上方へ移動させることが可能となる。この機能は第
２図（ａ）（ｂ）に示すように、複数のチップ２を同一
配線基板３に接続する場合、配線基板３の反りやチップ
２の接続高さバラツキを吸収し、冷却体本体７に直接熱
接続することを可能とする。第２図（ｃ）は、接続状態
を示す拡大図であるが、チップ２と配線基板３と熱膨張
差による水平熱歪に対してもこれを吸収できる構造とな
っている。By configuring the electrical connection structure of the chip as described above, it becomes possible to independently move the chip upward within a certain limit while maintaining the electrical connection. As shown in FIGS. 2 (a) and 2 (b), this function absorbs warpage of the wiring board 3 and variations in the connection height of the chips 2 when connecting a plurality of chips 2 to the same wiring board 3 and cools the cooling body. It enables direct thermal connection to the body 7. FIG. 2 (c) is an enlarged view showing the connection state, but it has a structure capable of absorbing horizontal thermal strain due to the difference in thermal expansion between the chip 2 and the wiring board 3 as well.
ところで、第１図において接続高さ方向及び水平方向に
可撓性を有するらせん形平面リードの対チップ端子1aと
対配線基板端子1bの位置を交替しても同一の機能が得ら
れる。また、接続高さ方向及び水平方向に可撓性を有す
るらせん形平面リード１の形状としてらせん型の他、第
３図（ａ）（ｂ）に示すような形状も種々考えられる。By the way, in FIG. 1, the same function can be obtained even if the positions of the pair of chip terminals 1a and the pair of wiring board terminals 1b of the spiral flat lead having flexibility in the connection height direction and the horizontal direction are exchanged. Further, in addition to the spiral shape as the shape of the spiral flat lead 1 having flexibility in the connection height direction and the horizontal direction, various shapes as shown in FIGS.
以上詳述した通り、本発明によるチップの電気的接続構
造によれば、チップと配線基板との熱膨張歪を吸収機能
を損なうことなく、種々のチップを独立に冷却体本体へ
熱接続可能となり、冷却系の構造全体を極めて簡単にで
きる。すなわち、従来個々のチップに対し独立に冷却体
を設け、これにベローズなどの位置調整あるいは圧着圧
力調整手段が不可欠であったものを、本発明では必要と
せず、チップの高密度配列化に対し、優れた組立性を有
する。As described above in detail, according to the electrical connection structure of the chip according to the present invention, various chips can be independently thermally connected to the cooling body without impairing the function of absorbing the thermal expansion strain between the chip and the wiring board. The entire structure of the cooling system can be made extremely simple. That is, it is not necessary in the present invention to provide a cooling body independently for each chip, and a position adjusting means such as a bellows or a pressure-bonding pressure adjusting means has been indispensable for this in the present invention. , Has excellent assemblability.
第１図（ａ）は本発明に係る接続高さ方向及び水平方向
に可撓性を有するらせん形平面リードの見取図、（ｂ）
はその平面図、（ｃ）は接続状態を示す正面図、第２図
はチップ、配線基板及び冷却系との位置関係図、第３図
は本発明に係る接続高さ方向及び水平方向に可撓性を有
するらせん形平面リードの他の実施例を示す正面配列
図、第４図（ａ）は従来の板ばねの見取図、（ｂ）はそ
の平面図、（ｃ）は接続状態を示す正面図、第５図は従
来のチップ配線基板及び冷却系との位置関係図である。 １……接続高さ方向及び水平方向に可撓性を有するらせ
ん形平面リード,1a,1b……接続高さ方向及び水平方向に
可撓性を有するらせん形平面リードの端子,2……チッ
プ,3……配線基板,4……はんだ,5……チップ電極,6……
配線基板電極,7……冷却体本体,7a……冷却体,7b……ベ
ローズ,8……熱接続部,10……電気接続部,100……板ば
ね,100a,100b……ピン。FIG. 1 (a) is a schematic view of a spiral planar lead having flexibility in a connection height direction and a horizontal direction according to the present invention, (b).
Is a plan view thereof, (c) is a front view showing a connected state, FIG. 2 is a positional relationship diagram with a chip, a wiring board, and a cooling system, and FIG. 3 is a connection height direction and a horizontal direction according to the present invention. FIG. 4 (a) is a schematic view of a conventional leaf spring, FIG. 4 (b) is a plan view of the same, and FIG. 4 (c) is a front view showing a connected state. FIG. 5 and FIG. 5 are positional relationship diagrams with a conventional chip wiring board and a cooling system. 1 ... Spiral plane lead having flexibility in connection height direction and horizontal direction, 1a, 1b ... Spiral plane lead terminal having flexibility in connection height direction and horizontal direction, 2 ... Chip , 3 …… wiring board, 4 …… solder, 5 …… chip electrode, 6 ……
Wiring board electrode, 7 ... Cooling body, 7a ... Cooling body, 7b ... Bellows, 8 ... Thermal connection, 10 ... Electrical connection, 100 ... Leaf spring, 100a, 100b ... Pin.
フロントページの続き (72)発明者 村田 旻 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (56)参考文献 特開 昭61−247040（ＪＰ，Ａ) 特開 昭61−287238（ＪＰ，Ａ)Front page continuation (72) Inventor Satoshi Murata 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Production Technology Research Laboratory, Hitachi, Ltd. (56) References JP-A-61-247040 (JP, A) JP-A-61 -287238 (JP, A)
Claims (1)
片を介して基板に電気接続する電子部品の接続構造にお
いて、リード片として高さが最小横方向寸法以下であ
り、かつ接続高さ方向及び水平方向に可撓性を有するら
せん形平面リードを用いたことを特徴とする電子部品の
接続構造。1. A connection structure of an electronic component for electrically connecting an electronic component having a plurality of connection points to a substrate through a lead piece, wherein the height of the lead piece is a minimum lateral dimension or less, and the connection height is A connection structure for electronic parts, characterized in that a spiral flat lead having flexibility in a horizontal direction and a horizontal direction is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62004802A JPH071773B2 (en) | 1987-01-14 | 1987-01-14 | Connection structure of electronic parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62004802A JPH071773B2 (en) | 1987-01-14 | 1987-01-14 | Connection structure of electronic parts |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63174328A JPS63174328A (en) | 1988-07-18 |
| JPH071773B2 true JPH071773B2 (en) | 1995-01-11 |
Family
ID=11593895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62004802A Expired - Fee Related JPH071773B2 (en) | 1987-01-14 | 1987-01-14 | Connection structure of electronic parts |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH071773B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002151550A (en) * | 2000-11-15 | 2002-05-24 | Nec Corp | Semiconductor device, its manufacturing method and coil spring cutting jig and coil spring feeding jig for use therein |
| JP4720069B2 (en) * | 2002-04-18 | 2011-07-13 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61247040A (en) * | 1985-04-24 | 1986-11-04 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS61287238A (en) * | 1985-06-14 | 1986-12-17 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1987
- 1987-01-14 JP JP62004802A patent/JPH071773B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63174328A (en) | 1988-07-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |